Planar complementary mosfet structure to reduce leakages and planar areas

Abstract

This invention discloses a planar complementary metal-oxide-semiconductor (MOSFET) structure for use in the peripheral circuitry of a dynamic random-access memory (DRAM) chip and in the sense amplifier of the array core circuitry of a DRAM chip. The planar complementary MOSFET structure includes: a planar P-type MOSFET with a first conductive region; a planar N-type MOSFET with a second conductive region; and a cross-shaped local isolation region located between the planar P-type and N-type MOSFETs. The cross-shaped local isolation region includes a horizontally extending isolation region that contacts the bottom side of the first and second conductive regions. This invention can also be similarly applied to transistors in complementary MOSFET logic circuits.

Description

Planar CMOS MOSFET structure for reduced leakage and planar area The present invention relates to a novel planar transistor and a planar complementary metal oxide semiconductor field effect transistor (MOSFET) structure, and more particularly to a planar transistor and / or a planar complementary MOSFET structure used in peripheral circuits or sense amplifiers of dynamic random access memory (DRAM), which can reduce leakage current, lower short channel effects, and prevent latch-up effects. While advanced technology nodes (e.g., 3 nm to 7 nm) are frequently used in high-performance computing applications (such as artificial intelligence (AI), central processing units (CPUs), and graphics processing units (GPUs)), mature technology nodes (e.g., 20 nm to 30 nm) remain popular in many integrated circuit (IC) applications, such as power management ICs, microcontrollers (MCUs), and DRAM chips. Taking DRAM as an example, most customized DRAMs are still manufactured using mature technology nodes (e.g., 12 nm to 30 nm). Furthermore, all transistors within the DRAM chip 17 (as shown in FIG. 1A ), including those within the peripheral circuitry 171 (including at least data / address input / output circuitry, address decoders, command logic, and update circuitry) and within the array core circuitry 172 (including the storage memory array and sense amplifiers), are still planar transistors. FIG1B shows a cross-sectional view of a state-of-the-art complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) 10, which is widely used in the peripheral circuits of DRAM chips and the sense amplifiers of the core circuits of the DRAM chip array. CMOSFET 10 comprises a planar N-type metal-oxide-semiconductor (NMOS) transistor 11 and a planar P-type metal-oxide-semiconductor (PMOS) transistor 12, with a shallow trench isolation (STI) region 13 located between NMOS transistor 11 and PMOS transistor 12. The gate structure 14 of the NMOS transistor 11 or PMOS transistor 12 is formed on top of a complementary metal oxide semiconductor (CMOS) transistor using a conductive material (such as metal, polysilicon, or polysilicon-silicide) over an insulator (such as oxide, oxide / nitride, or some high-k dielectric). Its sidewalls are isolated from the sidewalls of other transistors using an insulating material (such as oxide, oxide / nitride, or other dielectric). For the planar NMOS transistor 11, it has a source region and a drain region. These regions are formed by implanting N-type dopants into a P-type substrate (or P-type well) through ion implantation and thermal annealing to form two separate N+ / P junction regions. For the planar PMOS transistor 12, the source region and the drain region are formed by implanting P-type dopants into an N-type well through ion implantation to form two separate P+ / N junction regions. Furthermore, in order to reduce collision ionization and hot carrier injection before the highly doped N+ / P or P+ / N junction, a lightly doped-drain (LDD) region 15 is usually formed under the gate structure. On the one hand, during the aforementioned thermal annealing process, the N-type or P-type dopants implanted in CMOSFET 10 will inevitably diffuse in different directions and expand the areas of the source and drain regions. Furthermore, when forming a capacitor above the access transistor in the array core circuit of a DRAM chip, another thermal annealing process is performed to reduce the connection resistance between the capacitor and the access transistor. This second thermal annealing process again causes the N-type or P-type dopants to diffuse and increases the areas of the source and drain regions. The larger the areas of the source and drain regions caused by the thermal annealing process, the shorter the effective channel length (Leff shown in FIG. 1B ) between the source and drain regions. This reduced effective channel length, Leff, leads to a short channel effect (SCE). Therefore, to reduce the impact of the SCE, a longer gate length is typically retained to accommodate the diffusion of the N-type or P-type dopants caused by the thermal annealing process. Taking the 25 nm technology node (λ) as an example, the retained gate length will be approximately 100 nm, almost four times that of the technology node λ. On the other hand, since the NMOS transistor 11 and the PMOS transistor 12 are respectively located in certain adjacent regions of the P-type substrate and the N-type well formed adjacent to each other, a parasitic junction structure of a parasitic bipolar device called N+ / P / N / P+ (the path marked with a dotted line in Figure 1B is called the N+ / P / N / P+ latch path) is formed. Its outline starts from the N+ region of the NMOS transistor 11, extends to the P-type well, to the adjacent N-type well, and further upward to the P+ region of the PMOS transistor 12. If significant noise occurs at the N+ / P junction or the P+ / N junction, an abnormally large current may flow through the N+ / P / N / P+ junction, potentially halting certain operations of the CMOS circuit and causing overall chip failure. This anomaly, known as latch-up, is detrimental to CMOS operation and must be avoided. One approach to increasing resistance to latch-up, a CMOS weakness, is to increase the distance between the N+ region and the P+ region (labeled the latch-up distance in Figure 1B). Both the N+ and P+ regions must be separated by vertical oxide (or other suitable insulating material) layers, typically shallow trench isolation regions (STIs). For example, at the 25 nm technology node (λ), the remaining latch-up distance is approximately 500 nm, nearly 20 times greater than the λ technology node. More rigorous efforts to prevent latch-up require designing guard spacers that further increase the distance between the N+ and P+ regions and / or adding additional N+ or P+ regions to collect the abnormal charge from the noise source. These isolation schemes always add additional planar area at the expense of die size of the CMOS circuit. Current DRAM designs using planar transistors or complementary MOSFETs introduce or exacerbate other problems: (1) All junction leakage caused by junction formation processes such as forming a lightly doped drain (LDD) structure into the substrate / well region, forming an N+ source / drain structure into a P-type substrate, and forming a P+ source / drain structure into an N-type well becomes increasingly difficult to control because leakage current occurs in the peripheral and bottom regions where lattice defects caused by ion implantation cause additional damage such as empty traps for holes and electrons that is difficult to repair. (2) In addition, because the ion implantation to form the LDD structure (or N+ / P junction or P+ / N junction) works like a bombardment to insert ions from the top of the silicon surface directly down into the substrate, it is difficult to create a uniform material interface with few defects from the source and drain regions to the channel and substrate bulk regions because the doping concentration is unevenly distributed vertically from the higher doping concentration top surface down to the lower doping concentration junction region. (3) It is increasingly difficult to perfectly align the LDD junction edge with the transistor gate structure edge using only traditional self-alignment methods that utilize gates, spacers, and ion implantation. In addition, thermal annealing to remove ion implantation damage must rely on high-temperature processing techniques such as rapid thermal annealing methods or other thermal processes using various energy sources, resulting in a problem called gate-induced drain leakage (GIDL). As shown in Figure 1C (cited from: A. Sen and J. Das, “MOSFET GIDL Current Variation with Impurity Doping Concentration – A Novel Theoretical Approach” IEEE ELECTRON DEVICE LETTERS, VOL. 38, NO. 5, MAY 2017), a metal-oxide-semiconductor field-effect transistor structure with a thin oxide layer close to the gate and drain / source regions has a parasitic metal-gated-diode (MGD). The parasitic MGD formed between the gate and the source / drain regions causes drain leakage current (GIDL). Although GIDL should be minimized to reduce leakage current, it is difficult to control GIDL. Another problem that arises is that it is difficult to control the effective channel length, making it difficult to minimize the short-channel effect.(4) Since it is difficult to make the vertical length of the shallow trench isolation structure deeper while the planar width of the device isolation region must be reduced (otherwise it will result in a poor depth-to-opening aspect ratio for the integrated process of etching, filling, and planarization), the proportion of the planar isolation distance between the N+ region and the P+ region of adjacent transistors reserved to prevent the latch-up effect from occurring at the reduced lambda cannot be reduced, but instead increases, thus being detrimental to the reduction of chip area when shrinking the CMOS device. The present invention discloses several new concepts for understanding novel planar transistor and planar complementary MOSFET structures, particularly for use in peripheral circuits of DRAM chips and sense amplifiers in core circuits of DRAM arrays. These structures significantly improve or even resolve most of the aforementioned issues, such as minimizing leakage current, increasing channel conduction performance and control, optimizing the functions of the source and drain regions, such as achieving seamless and orderly crystal lattice matching to enhance the conductivity of the source and drain regions to metal interconnects and minimize physical integrity of the channel region, increasing the immunity of CMOS circuits to latch-up effects, and minimizing the planar area of ​​the layout isolation region between NMOS and PMOS to prevent latch-up effects. According to one subject matter of the present invention, a DRAM chip or circuit includes: a semiconductor substrate having a semiconductor surface; an array core circuit having a sense amplifier circuit and a plurality of dynamic random access memory cells, wherein the dynamic random access memory cells are electrically coupled to the sense amplifier circuit; and a peripheral circuit electrically coupled to the array core circuit. The sense amplifier circuit or the peripheral circuit has a complementary MOSFET structure, wherein the complementary MOSFET structure includes: a planar P-type MOSFET having a first conductive region; a planar N-type MOSFET having a second conductive region; and a cross-shaped local isolation region located between the planar P-type MOSFET and the planar N-type MOSFET. The cross-shaped local isolation region includes a horizontally extended isolation region located below the semiconductor surface, wherein the horizontally extended isolation region contacts the bottom side of the first conductive region and the bottom side of the second conductive region. According to one aspect of the present invention, the complementary MOSFET structure further includes a first recess formed below the semiconductor surface, the first recess accommodating the first conductive region. According to one aspect of the present invention, the first conductive region includes an undoped semiconductor region and / or a lightly doped semiconductor region, which is independent of the semiconductor substrate. According to one aspect of the present invention, the undoped semiconductor region or the lightly doped semiconductor region is adjacent to a channel region of the planar P-type MOSFET. According to one aspect of the present invention, the first conductive region further includes a heavily doped semiconductor region located in the first recess, wherein the lightly doped semiconductor region and the heavily doped semiconductor region are formed to have the same lattice structure. According to one aspect of the present invention, the first conductive region further includes a metal region located in the first recess and adjacent to the heavily doped semiconductor region. According to one aspect of the present invention, the complementary MOSFET structure further includes a first recess formed below the semiconductor surface, the first recess accommodating a first portion of the horizontally extended isolation region. According to one aspect of the present invention, the planar P-type MOSFET further includes a gate region located above the semiconductor surface, with an edge of the gate region aligned with or substantially aligned with an edge of the first conductive region. According to one aspect of the present invention, the planar P-type MOSFET further includes a gate region, and the entire first portion of the horizontally extended isolation region is not directly located below the gate structure. According to one aspect of the present invention, the planar P-type MOSFET further includes a gate region, and a first portion of the horizontally extended isolation region, which is less than 5%, is directly below the gate structure. According to one aspect of the present invention, the HIR is a composite isolation region. According to one aspect of the present invention, the composite isolation region includes an oxide layer and a nitride layer, wherein the nitride layer is located above the oxide layer. According to one aspect of the present invention, a vertical depth of the oxide layer is smaller than a vertical depth of the nitride layer. According to one aspect of the present invention, the horizontally extended isolation region includes a first horizontally extended isolation region and a second horizontally extended isolation region, the first horizontally extended isolation region shielding the bottom side of the first conductive region from the semiconductor substrate, and the second horizontally extended isolation region shielding the bottom side of the second conductive region from the semiconductor substrate. According to one aspect of the present invention, the cross-shaped local isolation region includes a vertically extended isolation region, which is located between the first horizontally extended isolation region and the second horizontally extended isolation region, wherein a vertical depth of the vertically extended isolation region is greater than the sum of a vertical depth of the first horizontally extended isolation region and a vertical depth of the first conductive region. According to another aspect of the present invention, a DRAM circuit formed at a technology node λ includes: a semiconductor substrate having a semiconductor surface; an array core circuit having a sense amplifier circuit and a plurality of dynamic random access memory cells, the dynamic random access memory cells being coupled to the sense amplifier circuit; and a peripheral circuit electrically coupled to the array core circuit. The sense amplifier circuit or the peripheral circuit has a complementary MOSFET structure, the complementary MOSFET structure comprising: a planar P-type MOSFET including a first source region, a first drain region, and a first gate region, the first gate region being located above the semiconductor surface; and a planar N-type MOSFET including a second source region, a second drain region, and a second gate region, the second gate region being located above the semiconductor surface. Among them, the first source region or the first drain region includes a lightly doped semiconductor region and a heavily doped semiconductor region, and the heavily doped semiconductor region is laterally adjacent to the lightly doped semiconductor region; wherein, a dynamic random access memory cell includes an access transistor and a storage capacitor, the access transistor includes a third source region, a third drain region, and a third gate region, the third source region or the third drain region includes a lightly doped semiconductor region and a heavily doped semiconductor region, and the heavily doped semiconductor region is vertically adjacent to the lightly doped semiconductor region. According to one aspect of the present invention, one edge of the first gate region is aligned with or substantially aligned with an edge of the first source region, and the other edge of the first gate region is aligned with or substantially aligned with an edge of the first drain region. According to one subject of the present invention, the complementary MOSFET structure further includes a local isolation region located between the planar P-type MOSFET and the planar N-type MOSFET, and the local isolation region shields a highly doped P+ region in the first source region or the first drain region from the semiconductor substrate. According to one aspect of the present invention, the local isolation region includes a vertically extending isolation region and a horizontally extending isolation region, and the latch path between the planar P-type MOSFET and the planar N-type MOSFET depends at least on a bottom length of the horizontally extending isolation region. According to another aspect of the present invention, a DRAM circuit includes: a semiconductor substrate having a semiconductor surface; an array core circuit having a sense amplifier circuit and a plurality of dynamic random access memory cells, the dynamic random access memory cells being coupled to the sense amplifier circuit; and a peripheral circuit electrically coupled to the array core circuit. Each dynamic random access memory cell includes an access transistor and a storage capacitor. The sense amplifier circuit or the peripheral circuit has a complementary MOSFET structure, the complementary MOSFET structure including: a planar P-type MOSFET including a first source region, a first drain region, and a first gate region, the first gate region being located above the semiconductor surface; and a planar N-type MOSFET including a second source region, a second drain region, and a second gate region, the second gate region being located above the semiconductor surface. The access transistor includes a third source region, a third drain region, and a third gate region, with at least a portion of the third gate region located below the semiconductor surface. The first source region and the first drain region have a first lattice structure, while the third source region and the third drain region have a second lattice structure, the first lattice structure being different from the second lattice structure. Furthermore, the first source region or the first drain region includes a lower surface that is lower than a lower surface of the first gate region, and the third source region or the third drain region includes a lower surface that is higher than a lower surface of the third gate region. According to one aspect of the present invention, the lower surface of the third source region or the third drain region is aligned with or substantially aligned with an upper surface of the third gate region. According to one aspect of the present invention, the first source region and the first drain region are independent of the semiconductor substrate, and the third source region and the third drain region are independent of the semiconductor substrate. According to one aspect of the present invention, the semiconductor substrate is a silicon substrate, the first source region and the first drain region are selectively grown from the (110) crystal plane of the silicon substrate and extend laterally, and the third source region and the third drain region are selectively grown from the (100) crystal plane of the silicon substrate and extend vertically. These and other objects of the present invention will no doubt become apparent to those skilled in the art to which the present invention pertains after reading the following detailed description of the preferred embodiment as illustrated in the various drawings. The present invention discloses a planar transistor and a planar complementary MOSFET structure, particularly for use in peripheral circuits of DRAM chips and in sense amplifiers of array core circuits of DRAM chips. The proposed method for manufacturing planar NMOS transistors and planar PMOS transistors is exemplarily described as follows: Step 10: Start. Step 20: Based on a semiconductor substrate, define active regions of the NMOS transistor and the PMOS transistor, and form deep shallow trench isolation structures. Step 30: Form a gate structure above the original semiconductor surface of the semiconductor substrate. Step 40: Form a spacer covering the gate structure, and form a recess in the semiconductor substrate. Step 50: Form a local isolation layer in the recess. Step 60: Expose the sidewalls of silicon in the recess, and laterally grow semiconductor regions in the recess from the exposed silicon sidewalls to form source and drain regions of the planar NMOS transistor and the planar PMOS transistor. Referring to Figures 2A and 2B, step 20 may include: Step 202: Forming a pad oxide layer 22 and depositing a pad nitride layer 23. Step 204: Using patterned photoresist (PR) to define active regions of the planar NMOS transistor and the planar PMOS transistor, and removing a portion of the silicon material in the semiconductor substrate outside the patterns of these active regions to create temporary trenches. Step 206: Depositing an oxide layer in the created temporary trenches, followed by etching back and planarizing the oxide layer to form shallow trench isolation features 21, wherein the upper surface of the shallow trench isolation features 21 is aligned with the upper surface of the pad nitride layer 23, as shown in Figure 2B, which is a cross-sectional view taken along the X-axis section line in Figure 2A. Please refer to Figures 3A~3B to 5A~5B. Step 30 of forming the gate structure may include: Step 302: Use another patterned photoresist 31 to define the gate length Lgate of the gate region of the planar NMOS transistor and the planar PMOS transistor, and then remove the portions of the pad oxide layer 22 and the pad nitride layer 23 not covered by the photoresist to form a gate accommodating groove 32, as shown in Figures 3A and 3B, where Figure 3B is a cross-sectional view along the X-axis section line in Figure 3A. Step 304: Then, a gate dielectric layer 331 (such as a thermal oxide or a high-k dielectric material), highly doped polysilicon 332 (N+ polysilicon for MOS and P+ polysilicon for MOS), a titanium / titanium nitride (Ti / TiN) layer 333, and a tungsten (W) layer 334 are formed in the gate-accommodating trench 32, as shown in Figures 4A and 4B, where Figure 4B is a cross-sectional view taken along the X-axis in Figure 4A. Step 306: A nitride capping layer 335 and an oxide capping layer 336 are formed over the tungsten layer 334 to complete the gate regions of the NMOS transistor and the PMOS transistor, as shown in Figures 5A and 5B, where Figure 5B is a cross-sectional view taken along the X-axis in Figure 5A. Next, referring to Figures 6A-6B to 8A-8B, step 40 may include: Step 402: Removing the pad oxide layer 22 and the pad nitride layer 23 between the shallow trench isolation device 21 and the gate region to expose the original silicon surface (OSS) of the substrate, as shown in Figures 6A and 6B, wherein Figure 6B is a cross-sectional view taken along the X-axis section line in Figure 6A. Step 404: Forming a spacer layer on the side of the gate region, wherein the spacer layer may include a thin oxide sub-layer 343 thermally grown on the original silicon surface (OSS) of the substrate, and a thin nitride sub-layer 341 and a thin oxide sub-layer 342 above the thin oxide sub-layer 343, as shown in Figures 7A and 7B, wherein Figure 7B is a cross-sectional view taken along the X-axis section line in Figure 7A. Step 406: Etching a portion of the semiconductor substrate to form recesses in the semiconductor substrate, as shown in FIG8A and FIG8B , where FIG8B is a cross-sectional view taken along the X-axis line in FIG8A . When the semiconductor substrate is a silicon substrate, each recess includes an exposed vertical side surface 36 having a (100) crystal plane. The vertical side surface 36 is located directly below the spacer layer formed in step 404 . Referring to Figures 9A and 9B , step 50 may include thermally growing an oxide layer 41 comprising a vertical oxide layer 411 and a horizontal oxide layer 412. The vertical oxide layer 411 covers the sidewalls of the recess formed in step 406, while the horizontal oxide layer 412 covers the bottom of the recess. A nitride material is then deposited to a sufficient thickness to completely fill the recess. Unnecessary portions of the nitride material are then removed using an etch-back process, leaving only the appropriate nitride layer 42 within the recess, as shown in Figures 9A and 9B , where Figure 9B is a cross-sectional view taken along the X-axis in Figure 9A . It should be noted that the nitride layer 42 may be replaced by any suitable insulating material. It should be noted that the thickness of the oxide layer 411 and the oxide layer 412 shown in FIG. 9B and subsequent figures is for illustrative purposes only, but it is very important to design the thermally grown oxide layer 41 so that the thickness of the oxide layer 411 is very precisely controlled under precisely controlled thermal oxidation temperature, timing, and growth rate. Thermal oxidation on a well-defined silicon surface should result in 40% of the thickness of the oxide layer 411 being subtracted from the silicon substrate from the aforementioned exposed (110) vertical side surface 36, and the remaining 60% of the thickness of the oxide layer 411 being considered as an addition outside the aforementioned exposed (110) vertical side surface 36 (FIG. 9B particularly clearly shows this 40% and 60% distribution on the oxide layer 411). Since the oxide layer 411 is very precisely controlled based on the thermal oxidation process, the edge of the oxide layer 411 can be aligned with the edge of the gate region. Of course, in another embodiment, depending on etching conditions and thermal oxidation growth conditions, a portion (eg, less than 5% to 10%) of the oxide layer 411 may be located below the gate structure. Referring to FIG. 10A and FIG. 10B , step 60 may include: Step 602: Removing the portion of the oxide layer 411 above the nitride layer 42 to expose additional vertical semiconductor sidewalls 501 and 502. Once again, when the semiconductor substrate is a silicon substrate, these vertical semiconductor sidewalls 501 and 502 have a (110) crystal plane. The remaining oxide layer 41 and nitride layer 42 may be referred to as localized isolation into silicon substrate (LISS). Step 604: Laterally growing first semiconductor regions 430 from the exposed vertical semiconductor sidewalls 501 and 502, respectively. Each first semiconductor region 430 may include a lightly doped region (or lightly doped-drain (LDD)) or an undoped region plus a lightly doped region. The first semiconductor regions 430 can be formed by a selective growth method such as Selective Epitaxial Growth (SEG) or Atomic Layer Deposition (ALD). Step 606: Grow second semiconductor regions laterally from these first semiconductor regions 430; each second semiconductor region includes a highly doped region, which can also be formed by a selective growth method. Thus, the drain region of the planar NMOS transistor includes an N-LDD region and an N+ doped region 431, and the source region of the planar NMOS transistor includes another N-LDD region and an N+ doped region 432. Similarly, the drain region of the planar PMOS transistor includes a P-LDD region and a P+ doped region 441, and the source region of the planar PMOS transistor includes another P-LDD region and a P+ doped region 442. It should be noted that each exposed vertical semiconductor sidewall 501 and 502 has a vertical boundary that is aligned (or substantially aligned) with the edge of the gate region, as shown in FIG10B . In other words, the edge of the source or drain region in the planar transistor is aligned (or substantially aligned) with the edge of the gate region. The present invention provides a deep SAPC technology (from gate to source / drain alignment and precise creation of crystal structures to form the source / drain). Thus, the alignment from the edge of the source / drain to the edge of the gate region can be precisely defined or controlled by using thermal oxidation and crystal structures. Furthermore, compared to the traditional method of using LDD implantation for gate edge to LDD alignment, the GIDL effect should be reduced. Furthermore, the new source / drain regions are formed from all (110) crystalline silicon; as explained, the improvement of the conventional method of growing the source / drain regions from two different seed regions results in a mixed lattice of (100) and (110) crystal planes in the silicon substrate. Therefore, the present invention can create a better source / drain to channel conduction mechanism and can also reduce subthreshold leakage. Furthermore, during the formation of the planar transistor, the effective channel length between the source and drain regions can be almost equal to the gate length (Leff shown in FIG. 10B ) because ion implantation and thermal annealing are not required. Since ion implantation is not required to form the LDD region or the source / drain region, there is no need to use a thermal annealing process to reduce defects. Therefore, since no additional defects are generated that are difficult to completely eliminate even through an annealing process once induced, any unexpected leakage current sources should be significantly minimized. Furthermore, even if another thermal annealing process is performed to reduce the connection resistance between the capacitor and the access transistor, since the first semiconductor region 430 of the present invention can include an undoped region plus a lightly doped region, the dopant redistribution caused by the additional thermal annealing process will not significantly reduce the effective channel length (Leff). Therefore, compared with conventional CMOS structures, the design rule for the gate length (Lgate) retained by the gate region according to the present invention can be reduced. For example, for a 20 nm to 30 nm technology node (λ) used in planar transistors, the retained gate length in the present invention will be between 1.5λ and 3λ, for example, 2λ or 2.5λ. At the same time, the source region and drain region of each planar transistor of the present invention are isolated by the insulating material (nitride layer 42 and the remaining oxide layer 41) located on the bottom structure, and are isolated along the three side walls by the layer of the shallow trench isolation element 21. The possibility of junction leakage can only occur in the extremely small area from the first semiconductor region 430 to the channel region (directly below the gate region of the planar transistor), thereby significantly reducing the possibility of junction leakage. In the aforementioned embodiment, before forming the gate structure, a channel region can be formed below and near the original silicon surface OSS by ion implantation (not shown). Then, in addition to the channel region formed by ion implantation, a channel region according to the present invention can be selectively grown. For example, before forming the gate dielectric layer 331 in FIG. 4B , the exposed silicon surface can be etched to form a shallow trench with a depth of 1.5 nm to 3 nm, as shown in FIG. 3-1A and FIG. 3-1B . Next, a channel region 24 is selectively grown in the shallow trench, as shown in FIG. 3-2A and FIG. 3-2B . Thereafter, the processes for forming the gate region, source region, and drain region described in FIG. 4A / 4B to FIG. 10A / 10B can be similarly applied to form another planar transistor structure as shown in FIG. 10C . In yet another embodiment, before forming the gate dielectric layer 331 in FIG. 4B , the exposed silicon surface can be etched to form a shallow trench having an arcuate or curved shape, as shown in FIG. 3-3A and FIG. 3-3B . Subsequently, a channel region 24 is selectively grown along the sidewalls of the shallow trench, as shown in FIG. 3-4A and FIG. 3-4B . Because the semiconductor channel region 24 is grown along the sidewalls of the curved or arcuate shallow trench, the channel length in this embodiment can be longer. Subsequently, the processes for forming the gate, source, and drain regions described in FIG. 4A / 4B through FIG. 10A / 10B can be similarly applied to form another planar transistor. Figures 10-1A and 10-1B illustrate cross-sectional views along the X-axis after laterally growing a semiconductor region from the exposed sidewalls of a recess according to another embodiment. The difference between Figures 10-1A / 10-1B and Figure 10C lies in that, before growing the NMOS LDD region 4302, a vertical P-type layer 4301 is first formed through selective growth. Subsequently, the LDD region 4302 and heavily doped N+ regions 431 / 432 are sequentially formed through selective growth. This vertical P-type layer 4301 reduces leakage current in the NMOS transistor when it is off. In another embodiment, the source (or drain) region may further include some tungsten or other suitable metal material (not shown) located in the recess and contacting the heavily doped region of the selectively grown source (or drain) region. Thus, the source (or drain) region is a composite source (or drain) region. Thus, external contacts can be connected to the metal region of the source (or drain) region, and this metal-to-metal contact has a lower resistance than traditional silicon-to-metal contacts. Furthermore, as shown in Figures 11A-11B, Figure 11A is a top view of the new planar CMOS structure according to the present invention, and Figure 11B is a diagram illustrating a cross-sectional view of the new planar CMOS structure along the section line (Y-axis) of Figure 11A. The planar PMOS transistor and the planar NMOS transistor in Figures 11A-11B are arranged vertically side by side. In Figure 11A, the four sides of the new planar CMOS structure are surrounded by shallow trench isolation elements 21. Furthermore, as shown in Figures 11A-11B, a composite local isolation element (comprising an oxide layer 412 and a nitride layer 42) exists between the P+ doped region 442 (or the P+ doped region 441 (or the drain region)) of the PMOS and the N-type well. Similarly, another composite local isolation element (comprising an oxide layer 412 and a nitride layer 42) exists between the N+ doped region 432 (or the N+ doped region 431 (or the drain region)) of the NMOS and the P-type well or substrate. That is, each drain and source region of the new planar CMOS structure is surrounded by shallow trench isolation elements 21 on three sidewalls and by composite local isolation elements on the lower sidewall. Consequently, the potential latch-up path from the bottom of the PMOS P+ region to the bottom of the NMOS N+ region is completely blocked by the local isolation elements. Therefore, the latch-up distance Xp + Xn (measured on a plane) can be shortened as much as possible without causing serious latch-up problems. On the other hand, in conventional CMOS structures, the N+ and P+ regions are not completely isolated by an insulator. As shown in FIG. 1B or FIG. 12 , a potential latch-up path exists from the N+ / P junction through the P-well / N-well junction to the N / P+ junction, comprising lengths a, b, and c. Furthermore, please refer to Figures 13A-13B according to another embodiment of the present invention. Figure 13A is a top view of a novel planar CMOS structure having a planar NMOS transistor and a planar PMOS transistor. Figure 13B is a diagram illustrating a cross-sectional view of the novel planar CMOS structure taken along the horizontal dashed line in Figure 13A. The planar PMOS transistor and the planar NMOS transistor in Figures 13A-13B are arranged side by side laterally. As shown in Figure 13B, this can be simplified to include a cross-shaped LISS 70 between the PMOS transistor and the NMOS transistor. The cross-shaped LISS 70 includes a vertically extended isolation region (VEI) 71 (e.g., shallow trench isolation device 21, with a vertical depth below the OSS of approximately 150 nm to 300 nm, such as 200 nm, as shown in FIG13B ), a first horizontally extended isolation region (HEIR) 72 (with a vertical depth of approximately 50 nm to 120 nm, such as 100 nm) located on the right-hand side of VEI 71, and a second horizontally extended isolation region (HEIR) 73 (with a vertical depth of approximately 50 nm to 120 nm, such as 100 nm) located on the left-hand side of VEI 71. Each HEIR may include an oxide layer 41 and a nitride layer 42. The vertical depth of the source / drain regions of the PMOS / NMOS transistors may be approximately 30 nm to 150 nm, such as 40 nm. The vertical depth of the gate regions of the PMOS / NMOS transistors may be approximately 40 nm to 60 nm, such as 50 nm as shown in FIG13B . In this embodiment, the first horizontally extended isolation region (HEIR) 72 and the second horizontally extended isolation region (HEIR) 73 are not directly beneath the gate structure or channel of the transistor. The first HEIR 72 (on the right-hand side of the VIR 71) contacts the bottom side of the source / drain region of the PMOS transistor, while the second HEIR 732 (on the left-hand side of the VIR 71) contacts the bottom side of the source / drain region of the NMOS transistor. Therefore, the bottom side of the source / drain regions in the PMOS and NMOS transistors are shielded from the semiconductor substrate. Furthermore, the first HEIR 72 or the second HEIR 73 can be a composite isolation element, comprising two or more different isolation materials (e.g., an oxide layer 41 and a nitride layer 42), or two or more identical isolation materials formed by different processes. As described above and in Figure 1B, a disadvantage of conventional CMOS technology compared to pure NMOS technology is the presence of parasitic bipolar structures such as the N+ / P-type substrate / N-well / P+ junction. Unfortunately, some poorly designed designs are unable to withstand the high current surges caused by noise that triggers latch-up, potentially shutting down the entire chip or permanently damaging its functionality. Conventional CMOS layout and process rules often require a significant distance to separate the N+ source / drain regions of the NMOS from the P+ source / drain regions of the PMOS. This distance, known as the latch-up distance (Figure 1B), consumes significant surface area to mitigate any potential for latch-up. Furthermore, if the source / drain N+ / P and P+ / N semiconductor junction areas are too large, a forward bias event can trigger a high current surge, leading to latch-up. The new planar CMOS structure in FIG. 13B allows for a longer path from the N+ / P junction through the P-well (or P-substrate) / N-well junction to the N / P+ junction. As shown in FIG. 13B , according to the present invention, the potential latch-up path from the LDD-N / P junction through the P-well / N-well junction to the N / LDD-P junction includes the lengths ①, ② (the length of the lower sidewall of one HEIR), ③, ④, ⑤, ⑥, ⑦ (the length of the lower sidewall of another HEIR), and ⑧, as indicated in FIG. 13B . On the other hand, in a conventional CMOS structure, a potential latch-up path from the N+ / P junction through the P-well junction to the N / P+ junction only includes lengths d, e, f, and g (as shown in FIG. 14 ). This type of potential latch-up path in FIG. 13B is longer than the potential latch-up path in FIG. 14 . Therefore, from a device layout perspective, the edge distance (Xn + Xp) retained between the NMOS and PMOS in FIG. 13B according to the present invention can be smaller than the edge distance (Xn + Xp) retained in FIG. 14 . Furthermore, compared to the N+ / P junction to the N / P+ junction in FIG. 14 , in FIG. 13B , the latch-up path starts from the LDD-N / P junction to the N / LDD-P junction. Because the doping concentration in the LDD-N or LDD-P regions in Figure 13B is lower than that in the N+ or P+ regions in Figure 14 , the amount of electrons or holes emitted from the LDD-N or LDD-P regions in Figure 13B is significantly lower than that from the N+ or P+ regions in Figure 14 . This lower carrier emission not only effectively reduces the likelihood of latch-up, but also significantly reduces the current flow even if latch-up does occur. Because the areas of the N+ / P and P+ / N junctions are significantly reduced, even if these junctions experience a sudden forward bias, the magnitude of the abnormal current is reduced, thereby reducing the chance of the latch-up effect shown in Figure 13B . Referring again to FIG. 13B , according to the present invention, the source or drain region of the planar PMOS is surrounded by first horizontally-extended isolation regions 72 and vertically-extended isolation regions 71. Only the LDD region (vertically approximately 10 nm to 50 nm) of the source or drain region of the planar PMOS contacts the semiconductor substrate, forming an LDD-P / N junction, rather than a P+ / N junction. Similarly, the source or drain region of the planar NMOS is surrounded by second horizontally-extended isolation regions 73 and vertically-extended isolation regions 71. Only the LDD region (vertically approximately 40 nm) of the source or drain region of the planar NMOS contacts the semiconductor substrate, forming an LDD-N / P junction, rather than a P+ / N junction. Consequently, the N+ region of the planar NMOS and the P+ region of the planar PMOS are shielded from the substrate or well region. Furthermore, because the first horizontally extended isolation region 72 or the second horizontally extended isolation region 73 is a composite isolation element and is sufficiently thick, the parasitic metal gate diode induced between the source region (or drain region) and the silicon substrate can be minimized. Furthermore, the gate-induced drain leakage (GIDL) effect can be improved. It is expected that the planar latch-up distance reserved for adjacent NMOS and PMOS transistors will be significantly shortened, allowing the planar area of ​​the new planar CMOS to be significantly reduced. Furthermore, this type of source / drain region grown directly from a specific crystal plane of a semiconductor substrate can be applied to access transistors in dynamic random access memory cells within the core circuitry of a DRAM chip array. Each dynamic random access memory cell includes an access transistor and a storage capacitor. As shown in FIG15A , an access transistor Q1 includes a source region 213A connected to a storage capacitor C1, a drain region 213B connected to a bit line BL of the DRAM chip, a gate dielectric layer 209 (e.g., oxide), a gate conductive region 210A (comprising metal or polysilicon), a dielectric gate cap 214A (e.g., oxide / nitride), and a U-shaped channel region 208A surrounding the gate conductive region 210A. Another access transistor Q2 includes a source region 213C connected to a storage capacitor C, a drain region 213B connected to a bit line BL of the DRAM chip, a gate dielectric layer 209 (e.g., oxide), a gate conductive region 210B (comprising metal or polysilicon), a dielectric gate cap 214B (e.g., oxide / nitride), and a U-shaped channel region 208B surrounding the gate conductive region 210B. Access transistors Q1 and Q2 are U-groove transistors or buried-gate transistors and can be formed in the well region 204 of the substrate 201 and surrounded by shallow trench isolation regions 202. It should be noted that the source region 213A, the drain region 213B, and the source region 213C can be selectively grown and vertically grown from the silicon (100) crystal plane exposed in the first recess 216A, the second recess 216B, and the third recess 216C shown in FIG15B. The source region 213A can include an LDD region 217A and a heavily doped region 218A, the drain region 213B can include an LDD region 217B and a heavily doped region 218B, and the source region 213C can include an LDD region 217C and a heavily doped region 218C, as shown in FIG15A. The source region / drain region of the access transistor in the dynamic random access memory cell of the present invention is directly vertically grown from the (100) crystal plane (for example, by selective epitaxial growth technology or atomic layer deposition technology), and their interface forms a seamless connection with the channel region. Furthermore, no ion implantation process is performed during the formation of the source / drain regions, and no thermal annealing process is performed which would make the junction boundary difficult to define and control. In summary, since the source / drain regions of the CMOS structure planar transistors in the peripheral circuits / sense amplifiers of the DRAM chip are directly grown laterally from the (110) crystal plane, their interface forms a seamless connection with the channel region, so the gate length (Lgate) can be precisely controlled. Moreover, the surface of the lightly doped drain (LDD) is grown horizontally from the transistor channel and the substrate body using in-situ doping technology during selective growth, without performing an ion implantation process that can only go from the top of the silicon down to the source / drain region, nor is there a thermal annealing process that makes the interface boundary difficult to define and control. Unlike traditional doped regions formed by ion implantation processes, this selectively grown semiconductor region (such as the undoped region, LDD region, and heavily doped region) is independent of the semiconductor substrate. The present invention can more accurately define the source / drain boundary to the edge of the gate region and can control the effective channel length (Leff) to minimize the short channel effect, GIDL, and junction leakage current. Moreover, in this newly invented planar CMOS structure, the N+ region and the P+ region are completely isolated by isolation elements. The proposed LISS will increase the isolation distance to the silicon substrate to separate the junctions in the NMOS transistor and the PMOS transistor, so that the surface distance between the junctions can be reduced. Furthermore, in the present invention, selective epitaxial growth forms LDDs in heavily doped regions, even including various non-silicon dopants such as germanium or carbon atoms, increasing stress and improving channel mobility. In the selective epitaxial growth / atomic layer deposition (ALD) formation of the source / drain regions according to the present invention, the doping concentration profile is controllable or adjustable. Moreover, in the well-known CMOS process, the conductive material used for the gate of the transistor can be polysilicon or metal, among which polysilicon is used because its work function is compatible with the silicon substrate and is often used in the gate first process. Polysilicon is a material composed of tiny silicon crystals. However, the conductivity of polysilicon is very low, and due to this low conductivity, the accumulation of charge is also low, resulting in a delay in channel formation, which causes unnecessary delays in the circuit. Therefore, polysilicon is usually doped with impurities to make it behave like a perfect conductor and reduce delays. However, in the polysilicon gate CMOS process, the polysilicon gate is doped by ion implantation. Problems arise when the polysilicon gate is not doped enough or the doping is uneven. Therefore, the dopant activation concentration is limited. For example, in PMOS transistors, this dopant activation concentration is usually less than 1x10 20 / cm 3 (For example, 7x10 19 / cm 3 ), and in NMOS transistors, this doping activation concentration is usually less than 4x10 20 / cm 3 (For example, 2.5x10 20 / cm 3 ). In addition, it often causes the polysilicon depletion effect, which is a phenomenon in which the threshold voltage of MOSFET devices changes undesirably when polysilicon is used as the gate material, resulting in unpredictable behavior in electronic circuits. Therefore, a key issue in advanced semiconductor processes for polysilicon gate processes is to have appropriate doping activation in the polysilicon (poly-Si) gate to minimize this polysilicon depletion effect. On the other hand, when high dielectric constant dielectrics (such as hafnium oxide) replace SiO When dielectrics serve as gate oxides in mainstream CMOS technology (especially in the gate-last process), metals are introduced as gate conductive materials. Since polysilicon is not used in the gate structure, a high-k dielectric metal gate (HKMG) is employed to address polysilicon depletion effects. However, this HKMG process is complex and expensive compared to polysilicon gate CMOS processes. The present invention further solves the doping activation problem in traditional polysilicon gate transistors and increases the doping activation concentration in the semiconductor / silicon gate of the NMOS transistor to no less than 3×10 20 / cm 3 (N+), for example, 4×10 20 / cm 3 (N+) or higher. Moreover, the doping activation concentration in the semiconductor / silicon gate of the PMOS transistor of the present invention can be increased to not less than 8x10 19 / cm 3 (P+), for example 1x10 20 / cm 3 (P+) or higher. This high doping activation concentration can reduce the polysilicon depletion effect, reduce the thickness of the gate dielectric layer, and improve the on-current (Ion) and gate control capability. In conventional transistors with polysilicon gate structures, for conventional NMOS transistors, the doping activation concentration in the polysilicon gate is only about 2.5×10 20 / cm 3 , while for traditional PMOS transistors, it is about 7×10 19 / cm 3 In the traditional polysilicon gate fabrication process, a layer of undoped polysilicon is typically deposited above the gate oxide layer. Then, for NMOS transistors, arsenic (As) or phosphorus (P) ions are implanted into the undoped polysilicon, followed by rapid thermal annealing to activate the doping concentration. On the other hand, in the proposed transistor with a highly doped silicon gate structure, for an NMOS transistor, the doping activation concentration in the highly doped silicon gate can be greater than 4x10 20 / cm 3 , while for PMOS transistors, it can be greater than 1x10 20 / cm 3 According to the exemplary manufacturing process of the NMOS transistor shown in FIG. 16 to FIG. 18 of the present invention, in order to increase the doping activation concentration in the gate structure, after forming the gate dielectric layer 331 (such as thermal oxide or high dielectric constant material), first at 500 o C to 650 o C. A thin layer 3321 of undoped or doped amorphous silicon (or polysilicon) is deposited on top of the gate dielectric layer 331, as shown in FIG. 16. Next, at about 1000 o C or higher (e.g. laser annealing, about 1200 o C, plus thermal annealing, about 600 o C) Annealing the amorphous silicon layer to recrystallize it into a silicon layer with larger grains, which may be larger than 1 micron (μm) to 2 microns. For example, see TI KAMINS AND TR CASS, “STRUCTURE OF CHEMICALLY DEPOSITED POLYCRYSTALLINE-SILICON FILMS”, Thin Solid Films, 16 (1973) 147-165; see alsoYasuo Wada and Shigeru Nishimatsu, “Grain Growth Mechanism of Heavily Phosphorus-implanted Polycrystalline Silicon”, J. Electrochem. Soc.: SOLID-STATE SCIENCE AND TECHNOLOGY, Vol. 125, No. 9, 1499-1504, September 1978). Then, as shown in FIG. 17 , a layer of in-situ N+ doped silicon 3323 is selectively grown (e.g., selective epitaxial growth (SEG)) using the larger grain silicon layer 3322 as a seed layer, and then subjected to a rapid thermal annealing (RTA) process at approximately 1000°C. o C or higher temperature, so that the doping activation concentration in the selectively grown silicon layer can be about 4x10 20 / cm 3 (See ZN Weinrich, et al, “Dopant-defect interactions in highly doped epitaxial Si:P thin films”, Thin Solid Films 685 (2019) 1 – 7). Furthermore, because the originally undoped amorphous silicon layer is extremely thin, the rapid thermal annealing described above causes the dopants in the in-situ N+ doped silicon layer to diffuse outward into the recrystallized larger-grained silicon layer, causing the doping concentration of the recrystallized larger-grained silicon layer to be almost equal to that of the in-situ N+ doped silicon layer. Consequently, after the rapid thermal annealing, it is almost impossible to distinguish between the in-situ N+ doped silicon 3323 and the larger-grained silicon layer 3322. To complete the NMOS transistor structure, a standard gate patterning process can be applied to form the gate shape, as shown in Figure 18 . A titanium nitride (TiN) layer 333 and a tungsten layer 334 can be deposited over the in-situ N+ doped silicon 3323. LDD regions and nitride spacers can then be formed, and N+ source / drain regions can be formed by ion implantation and annealing, as shown in Figure 18 . It should be noted that the grain size of the recrystallized silicon layer with larger grains can be larger than 1 μm to 2 μm, as can the in-situ N+ doped silicon layer formed by selective epitaxial growth. After standard gate patterning processes based on technology nodes below 28 nm, the gate length is typically no greater than 150 nm. Therefore, along the gate length of the in-situ N+ doped silicon layer, the in-situ N+ doped silicon layer is essentially a single crystal layer; alternatively, along a tangent line along the gate length, the in-situ N+ doped silicon layer will contain no more than three silicon grains. Similarly, in the process of forming a traditional PMOS transistor, a layer of undoped polysilicon is first deposited on top of the gate oxide layer. Boron (B) ions are then implanted into the undoped polysilicon, followed by a rapid thermal annealing to activate the doping concentration. In this polysilicon gate of a traditional PMOS transistor, the doping activation concentration will not be greater than 1x10 20 / cm 3 On the other hand, FIG. 19 to FIG. 21 illustrate an exemplary process for fabricating a PMOS transistor according to the present invention. Details similar to those in FIG. 16 to FIG. 18 are omitted here. However, the dopant type in the epitaxial silicon gate of the PMOS transistor is different from the dopant type in the epitaxial silicon gate of the NMOS transistor. In such an epitaxial silicon gate of the PMOS transistor according to the present invention, the dopant activation concentration will not be greater than 1x10 20 / cm 3 . Figures 22A and 22B show a comparison between a polysilicon gate transistor manufactured according to a conventional process (Figure 22A) and a polysilicon gate transistor manufactured according to the process of the present invention (Figure 22B). The high dopant activation concentration of the in-situ N+ / P+ doped silicon 3323 can reduce the polysilicon depletion effect, reduce the thickness of the gate dielectric layer 331, and improve the on-state current and gate control capability. In summary, the present invention solves the dopant activation problem in conventional polysilicon gate transistors and increases the dopant activation concentration in the silicon gate of NMOS and PMOS transistors to no less than 4×10 20 / cm 3 (N+) and 1x10 20 / cm 3 (P+). This high doping activation concentration can reduce the depletion effect of polysilicon, reduce the thickness of the gate dielectric layer, and improve the on-state current and gate control capability. The present invention can be applied to all transistors with silicon gates, such as planar transistors, fin-structured transistors, gate-all-around (GAA) transistors, and the like. Moreover, this epitaxial silicon gate transistor can be used not only in logic circuits of semiconductor memories such as DRAM, but also in peripheral circuits. Furthermore, the present invention can be applied to other semiconductor materials used for the gate structure of MOS transistors, such as silicon germanium (SiGe), silicon carbide (SiC), or gallium nitride (GaN), and the like. Figure 23A shows electron backscatter diffraction (EBSD) results of an amorphous silicon layer after annealing in a real sample structure. In this sample structure, the amorphous silicon layer is initially formed on an oxide layer deposited on a silicon substrate. The amorphous silicon layer is then annealed, as shown in the upper left image of Figure 23A. EBSD results reveal numerous grains in the annealed amorphous silicon layer, with a grain size of approximately 1.35 microns. Furthermore, transmission electron microscopy (TEM) results, shown in Figure 23B, reveal polycrystalline planes in the annealed amorphous silicon layer. X-ray diffraction (XRD) results reveal two {110} grains in two designated areas of the annealed amorphous silicon layer in Figure 23B, as shown in the right and left images of Figure 23C. Therefore, the process proposed by the present invention can form larger silicon grains in the amorphous silicon layer after annealing. Those skilled in the art will readily appreciate that various modifications and variations can be made to the apparatus and method while retaining the teachings of the present invention. Therefore, the above disclosure should be interpreted as being limited only by the scope and limits of the appended claims. 10: CMOSFET 11: NMOS transistor 12: PMOS transistor 13: Shallow trench isolation region 14: Gate structure 15: LDD region 17: DRAM chip 21: Shallow trench isolation element 22: Pad oxide layer 23: Pad nitride layer 24: Channel region 31: Patterned photoresist 32: Gate accommodating trench 36: Vertical side surface 41: Oxide layer 42: Nitride layer 70: Cross-shaped LISS 71: Vertically Extended Isolation Region 72: First Horizontally Extended Isolation Region 73: Second Horizontally Extended Isolation Region 171: Peripheral Circuit 172: Array Core Circuit 201: Substrate 202: Shallow Trench Isolation Region 204: Well Region 208A: U-Shaped Channel Region 208B: U-Shaped Channel Region 209: Gate Dielectric Layer 210A: Gate Conductive Region 210B: Gate Conductive Region 213A: Source Region 213B: Drain Region 213C: Source Region 214A: Dielectric Gate Cover Element 214B: Dielectric Gate Cover Element 216A: First Recess 216B: Second Recess 216C: Third Recess 217A: LDD Region 217B: LDD Region 217C: LDD Region 218A: Heavily Doped Region 218B: Heavily Doped Region 218C: Heavily Doped Region 331: Gate Dielectric Layer 332: Highly Doped Polysilicon 33 3: Titanium / titanium nitride layer 334: Tungsten layer 335: Nitride capping layer 336: Oxide capping layer 341: Thin nitride sublayer 342: Thin oxide sublayer 343: Thin oxide sublayer 411: Oxide layer 412: Oxide layer 430: First semiconductor region 431: N+ doped region 432: N+ doped region 441: P+ doped region 442: P+ doped region 501: Vertical semiconductor sidewall 502: Vertical semiconductor sidewall 4301: Vertical P-type layer 3321: Thin layer of undoped or doped amorphous silicon (or polycrystalline silicon) 3322: Silicon layer with larger grains 3323: In-situ N+ doped silicon 4302: LDD region BL: Bit line C1: Storage capacitor C2: Storage capacitor Leff: Effective channel length Lgate: Gate length OSS: Original silicon surface Xn, Xp: Distance FIG. 1A is a diagram illustrating a circuit diagram of a DRAM chip. FIG. 1B is a diagram illustrating a cross-sectional view of a conventional CMOS structure. FIG. 1C is a diagram illustrating a parasitic metal gate diode formed in the gate-to-source / drain region of a MOSFET and the GIDL problem in the MOSFET. FIG. 2A and FIG. 2B are diagrams illustrating a top view and a cross-sectional view along the section line (X-axis) after depositing a pad nitride layer and forming shallow trench isolation elements. FIG. 3A and FIG. 3B are diagrams illustrating a top view and a cross-sectional view along the section line (X-axis) after defining a gate length. FIG. 3-1A and FIG. 3-1B are diagrams illustrating another embodiment of a top view and a cross-sectional view along the section line (X-axis) after forming a shallow trench for a channel region. FIG. 3-2A and FIG. 3-2B are diagrams illustrating another embodiment of a top view and a cross-sectional view along the section line (X-axis) after selectively forming a channel region. Figures 3-3A and 3-3B are diagrams illustrating another embodiment of a top view and a cross-sectional view along the cross-sectional line (X-axis) after forming a shallow trench having an arc shape for the channel region. Figures 3-4A and 3-4B are diagrams illustrating another embodiment of a top view and a cross-sectional view along the cross-sectional line (X-axis) after selectively forming a shallow trench having an arc shape in the channel region. Figures 4A and 4B are diagrams illustrating a top view and a cross-sectional view along the cross-sectional line (X-axis) after forming a gate conductive region. Figures 5A and 5B are diagrams illustrating a top view and a cross-sectional view along the cross-sectional line (X-axis) after forming a gate covering region. Figures 6A and 6B are diagrams illustrating a top view and a cross-sectional view along the cross-sectional line (X-axis) after removing pad nitride and pad oxide outside the gate region. FIG7A and FIG7B are diagrams illustrating a top view and a cross-sectional view along the section line (X-axis) after forming spacers on the sidewalls of the gate region. FIG8A and FIG8B are diagrams illustrating a top view and a cross-sectional view along the section line (X-axis) after forming a recess outside the gate region. FIG9A and FIG9B are diagrams illustrating a top view and a cross-sectional view along the section line (X-axis) after forming a local isolation layer in the recess. FIG10A and FIG10B are diagrams illustrating a top view and a cross-sectional view along the section line (X-axis) after laterally growing a semiconductor region from the sidewalls exposed in the recess. FIG10C is a diagram illustrating another embodiment of a cross-sectional view along the section line (X-axis) after laterally growing a semiconductor region from the sidewalls exposed in the recess. FIG10-1A and FIG10-1B illustrate a cross-sectional view along a section line (X-axis) after laterally growing a semiconductor region from the exposed sidewalls of a recess according to another embodiment. FIG11A and FIG11B illustrate a top view and a cross-sectional view along a vertical dashed section line of an embodiment of a planar CMOS structure in a peripheral circuit / sense amplifier of a DRAM chip according to the present invention.FIG12 illustrates a conventional CMOS structure having N+ and P+ regions that are not completely isolated by an insulator. FIG13A and FIG13B illustrate a top view and a cross-sectional view along a horizontal dashed line of another embodiment of a planar CMOS structure in the peripheral circuitry / sense amplifier of a DRAM chip according to the present invention. FIG14 illustrates a potential latch-up path in a conventional CMOS structure from the N+ / P junction through the P-well / N-well junction to the N / P+ junction structure. FIG15A illustrates a cross-sectional view of an access transistor in the core circuit of an array of a DRAM chip according to the present invention. FIG15B illustrates a cross-sectional view of an access transistor in the core circuit of an array of a DRAM chip according to the present invention after forming recesses for accommodating source / drain regions. FIG16 to FIG18 illustrate cross-sectional views of the steps for forming the semiconductor gate of the proposed NMOS transistor. FIG19 to FIG21 illustrate cross-sectional views of the steps for forming the semiconductor gate of the proposed PMOS transistor. Figure 22A is a cross-sectional view of a conventional polysilicon gate transistor. Figure 22B is a cross-sectional view of the semiconductor gate transistor proposed in accordance with the present invention. Figure 23A shows the electron backscatter diffraction (EBSD) results of the annealed amorphous silicon layer in a real sample structure. Figure 23B shows the transmission electron microscopy (TEM) results of the annealed amorphous silicon layer. Figure 23C shows the X-ray diffraction (XRD) results of two designated areas in the annealed amorphous silicon layer. 331: Gate dielectric layer 333:Titanium / Titanium Nitride layer 334: Tungsten layer 3323: In-situ N+ doped silicon

Claims

1. A semiconductor structure, comprising: A semiconductor substrate; A first dielectric layer is directly disposed on a first portion of the semiconductor substrate, wherein a length of the first dielectric layer is equal to a length of the first portion of the semiconductor substrate; and an undoped semiconductor layer is disposed on the first dielectric layer; wherein the undoped semiconductor layer includes a silicon-containing material, wherein a grain size of the silicon-containing material is greater than 1 micrometer, and a first sidewall and a second sidewall opposite to the first sidewall of the undoped semiconductor layer are covered by a shallow trench isolation element.

2. The semiconductor structure as described in claim 1, wherein, The first dielectric layer comprises an oxide.

3. The semiconductor structure as described in claim 1, wherein, Both the second and third dielectric layers consist of oxides.

4. The semiconductor structure as described in claim 1 further includes a dielectric capping layer located above the undoped semiconductor layer.

5. The semiconductor structure as described in claim 4, further comprising a doped semiconductor layer located between the dielectric capping layer and the undoped semiconductor layer; wherein, The doped semiconductor layer includes a silicon-containing material in which the size of a grain is greater than 1 micrometer.

6. A semiconductor structure, comprising: A semiconductor substrate; A first dielectric layer is directly disposed on a first portion of the semiconductor substrate, wherein a length of the first dielectric layer is equal to a length of the first portion of the semiconductor substrate; a first semiconductor layer is disposed on the first dielectric layer, wherein the first semiconductor layer includes a first silicon-containing material, wherein a grain size of the first silicon-containing material is greater than 1 micrometer; a dielectric capping layer is disposed above the first semiconductor layer; and a second semiconductor layer is disposed between the dielectric capping layer and the first semiconductor layer; wherein the second semiconductor layer includes a second silicon-containing material, wherein a grain size of the second silicon-containing material is greater than 1 micrometer.

7. The semiconductor structure as described in claim 6, wherein, A first sidewall of the first semiconductor layer is covered by a second dielectric layer, and a second sidewall of the first semiconductor layer relative to the first sidewall is covered by a third dielectric layer.

8. The semiconductor structure as described in claim 7, wherein, The first dielectric layer comprises oxide, and both the second and third dielectric layers comprise oxide.

9. A method for manufacturing a semiconductor structure, comprising: Prepare a semiconductor substrate; Define a first portion of the semiconductor substrate; A first dielectric layer is directly formed on the first portion of the semiconductor substrate, wherein a length of the first dielectric layer is equal to a length of the first portion of the semiconductor substrate; an undoped semiconductor layer is formed on the first dielectric layer; the undoped semiconductor layer is annealed; a doped semiconductor layer is formed on the undoped semiconductor layer, wherein the doped semiconductor layer includes a second silicon-containing material, wherein a grain size of the second silicon-containing material is greater than 1 micrometer; and a dielectric capping layer is formed above the undoped semiconductor layer.

10. A method for manufacturing a semiconductor structure as described in claim 9, wherein, The annealing step is performed at a temperature not lower than 1000°C.

11. A method for manufacturing a semiconductor structure as described in claim 9, wherein, The undoped semiconductor layer includes a first silicon-containing material, and after the annealing step, the size of a grain in the first silicon-containing material is greater than 1 micrometer.

12. A method for manufacturing a semiconductor structure, comprising: Prepare a semiconductor substrate; Define a first portion of the semiconductor substrate; A first dielectric layer is directly formed on the first portion of the semiconductor substrate, wherein a length of the first dielectric layer is equal to a length of the first portion of the semiconductor substrate; a first semiconductor layer is formed on the first dielectric layer, wherein the first semiconductor layer includes a first silicon-containing material; the first semiconductor layer is annealed, wherein after annealing, the size of a grain in the first silicon-containing material is greater than 1 micrometer; a second semiconductor layer is formed on the first semiconductor layer, wherein the second semiconductor layer includes a second silicon-containing material, the size of a grain in the second silicon-containing material is greater than 1 micrometer; and a dielectric capping layer is formed above the first semiconductor layer.

13. A method for manufacturing a semiconductor structure as described in claim 12, wherein, The annealing step is performed at a temperature not lower than 1000°C.

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