Video frame codec architectures

Abstract

This invention describes techniques and apparatus for a video frame codec architecture. A frame decompressor decompresses a compressed frame to produce a decompressed frame. A frame decompressor controller arbitrates shared access to the frame decompressor. Multiple cores of a SoC request to receive a decompressed frame from the frame decompressor via the frame decompressor controller. The frame decompressor controller may implement a request queue and may prioritize the service of such requests based on the request or the priority of the requesting core. The frame decompressor controller may also establish a time-sharing agreement for access by the multiple cores. In some embodiments, a video decoder is logically integrated with the frame decompressor and stores a portion of a decompressed frame in a video buffer, and a display controller uses a synchronization mechanism to retrieve such portions for display. Similarly, a frame decompressor controller may arbitrate shared access by the multiple cores to a frame decompressor.

Claims

1. An electronic device comprising: A frame decompressor configured to individually decompress multiple compressed frames at a frame level to generate multiple decompressed frames, and to derive the multiple compressed frames from multiple decoded frames respectively; a frame decompressor controller coupled to the frame decompressor and configured to arbitrate access to the frame decompressor by multiple cores; a first core among the multiple cores coupled to the frame decompressor controller, the first core configured to obtain, via the frame decompressor controller, one of the multiple decompressed frames generated by the frame decompressor at the frame level; and a second core among the multiple cores coupled to the frame decompressor controller, the second core configured to obtain, via the frame decompressor controller, another decompressed frame among the multiple decompressed frames generated by the frame decompressor at the frame level; the first core and the second core are configured to perform video transcoding.

2. The electronic device as claimed in item 1, wherein: The first core is configured to decode a video stream to generate the plurality of decoded frames, and to generate at least one decoded frame of the plurality of decoded frames using the decompressed frames; and the second core is configured to encode one or more of the plurality of decoded frames using another decompressed frame for the video transcoding.

3. The electronic device as described in claim 2, wherein: The first core includes a video decoder comprising a stream decoder configured to decode the video stream to generate the plurality of decoded frames; the frame decompressor is logically integrated with the video decoder; and the second core includes an encoder configured to encode the plurality of decoded frames to at least partially perform the video transcoding.

4. The electronic device as claimed in claim 1, wherein the frame decompressor controller includes: A request queue configured to store multiple requests, each request corresponding to at least one decompressed frame; and a request manager configured to receive the multiple requests from the multiple cores and insert the multiple requests into the request queue.

5. The electronic device as described in request item 4, wherein the frame decompressor controller includes a priority manager configured to prioritize the services of the plurality of requests according to a plurality of priorities corresponding to the plurality of requests.

6. The electronic device of claim 1, wherein the frame decompressor controller includes a time-sharing protocol processor configured to establish a time-sharing protocol for sharing the frame decompressor among the plurality of cores.

7. The electronic device of claim 6, wherein the time-sharing protocol processor is configured to perform at least one of the following: establishing the time-sharing protocol to include multiple time slots assigned to at least one of the multiple cores; or establishing the time-sharing protocol to allow the reception of an interrupt signal from one of the multiple cores, the interrupt signal indicating a request for at least one decompressed frame.

8. The electronic device of claim 1, further comprising: A frame compressor configured to individually compress one or more uncompressed frames at the frame level to produce one or more compressed frames; and a frame compressor controller coupled to the frame compressor and configured to arbitrate access to the frame compressor by the plurality of cores.

9. The electronic device of claim 8, wherein the frame compressor is configured to individually compress the plurality of decoded frames at the frame level to generate the plurality of compressed frames.

10. The electronic device of claim 1, wherein the frame decompressor is configured to implement a lossless frame-level compression algorithm to generate the plurality of decompressed frames from the plurality of compressed frames respectively.

11. A method for sharing frame decompression circuitry among multiple cores, the method comprising: At the frame level, a first decoded frame is compressed to produce a first compressed frame; At the frame level, a second decoded frame is compressed to generate a second compressed frame; a first request for a first decompressed frame is received from a first core; the first compressed frame is individually decompressed at the frame level to generate the first decompressed frame; in response to the first request, the first decompressed frame is provided to the first core; a second request for a second decompressed frame is received from a second core; the second compressed frame is individually decompressed at the frame level to generate the second decompressed frame; in response to the second request, the second decompressed frame is provided to the second core; and video transcoding is performed by the first core and the second core.

12. The method of request item 11, wherein the execution includes: The first core decodes a video stream to generate a plurality of decoded frames, including the first decoded frame and the second decoded frame; And by using the second core to encode the multiple decoded frames to generate another video stream.

13. As in request item 12, wherein: The decoding includes using the first core to decode the video stream using the first decompressed frame to generate at least one of the plurality of decoded frames; and the encoding includes using the second core to encode one or more of the plurality of decoded frames using the second decompressed frame to generate the other video stream.

14. The method of claim 11, further comprising: A third core receives a third request for a third decompressed frame; decompresses the third decompressed frame individually at the frame level to generate the third decompressed frame; and provides the third decompressed frame to the third core in response to the third request, wherein the first request instructs the first core; the second request instructs the second core; and the third request instructs the third core.

15. The method of claim 11, further comprising: A time-sharing protocol is established for accessing the frame decompression circuitry via at least the first core and the second core.

16. The method of request item 15, wherein the establishment includes: An interrupt is received from the second core during one of the time slots corresponding to the first core; In response to the interruption, the process switches from performing decompression on the first core to performing decompression on the second core.

17. The method of claim 11, further comprising: The provision of the first compressed frame and the provision of the second compressed frame shall be performed in an order that depends at least in part on the relative priority of one of the first request and the second request.

18. The method of claim 11, further comprising: Multiple requests are received from multiple cores for each of the multiple compressed frames; Compress multiple decompressed frames to generate the multiple compressed frames respectively; and in response to the multiple requests, provide the multiple compressed frames to the multiple cores.

19. An electronic device comprising: A frame decompressor, configured to decompress multiple compressed frames to generate multiple decompressed frames; A frame decompressor controller coupled to and configured to arbitrate access to the frame decompressor by multiple cores, the frame decompressor controller including a time-sharing protocol handler configured to establish a time-sharing protocol to share the frame decompressor among the multiple cores, the time-sharing protocol handler being configured to perform at least one of the following: establishing the time-sharing protocol to include multiple time slots assigned to at least one of the multiple cores; or establishing the time-sharing protocol to allow receiving an interrupt signal from one of the multiple cores, the interrupt signal indicating a request for at least one decompressed frame; One of the multiple cores, a first core, is coupled to the frame decompressor controller. The first core is configured to obtain one of the decompressed frames generated by the frame decompressor via the frame decompressor controller. A second core, also coupled to the frame decompressor controller, is configured to obtain another decompressed frame from the multiple decompressed frames generated by the frame decompressor via the frame decompressor controller. The first core and the second core are configured to perform video transcoding.

20. The electronic device as claimed in claim 19, wherein: The first core is configured to decode a video stream using the decompressed frame to generate at least one of a plurality of decoded frames; and the second core is configured to encode one or more of the plurality of decoded frames using another decompressed frame.

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