Semiconductor structure, fabrication method and package structure thereof

Abstract

A semiconductor structure includes a substrate, a semiconductor layer, a metal carrier, a top metal layer, a redistribution layer, and a dielectric material. The substrate has a front surface and a bottom surface. The semiconductor layer is disposed on the front surface of the substrate, the metal carrier is disposed below the bottom surface of the substrate, the top metal layer is disposed on the semiconductor layer, the redistribution layer is electrically connected to the top metal layer, and the dielectric material is disposed above the semiconductor layer, with the redistribution layer embedded in the dielectric material.

Description

Technical Field

[0001] This disclosure relates to semiconductor manufacturing technology, and in particular to semiconductor structures suitable for high temperatures and high operating voltages, as well as their manufacturing methods and packaging structures. Prior Technology

[0002] With the development of 5G communication, electric vehicles, and various electronic products, the demand for high-frequency, high-power semiconductor components is growing rapidly. These high-frequency, high-power semiconductor components, such as high-frequency transistors, high-power field-effect transistors, or high electron mobility transistors (HEMTs), generally use compound semiconductors, such as gallium nitride and silicon carbide, which are III-V compound semiconductors. They possess characteristics such as high frequency, high voltage resistance, and low on-resistance, and are typically used under high voltage and high temperature operating conditions. High-frequency, high-power semiconductor components can be mounted on printed circuit boards using traditional packaging methods, such as die bonding, wire bonding, and molding.

[0003] However, traditional semiconductor structures and packaging are generally more suitable for semiconductor devices that operate at low voltage and room temperature. For semiconductor devices that operate at high voltage and high temperature, there is still much room for improvement in semiconductor structure, manufacturing, and packaging. Summary of the Invention

[0004] In view of this, this disclosure proposes a semiconductor structure, its manufacturing method, and packaging structure, suitable for semiconductor devices operating at high voltage and high temperature. According to the semiconductor structure disclosed herein, a metal carrier is disposed under the bottom surface of the thinned substrate to improve heat dissipation efficiency. Furthermore, during the manufacturing process of the semiconductor structure, the metal carrier can support the thinned wafer, thereby preventing cracks in the semiconductor layer. Simultaneously, the placement of the metal carrier is beneficial for subsequent front-side redistribution layers, thereby improving the yield of the semiconductor device.

[0005] According to one embodiment of this disclosure, a semiconductor structure is provided, including a substrate, a semiconductor layer, a metal carrier, a top metal layer, a redistribution layer, and a dielectric material. The substrate has a front surface and a bottom surface, the semiconductor layer is disposed on the front surface of the substrate, the metal carrier is disposed below the bottom surface of the substrate, the top metal layer is disposed on the semiconductor layer, the redistribution layer is electrically connected to the top metal layer, and the dielectric material is disposed above the semiconductor layer, with the redistribution layer embedded in the dielectric material.

[0006] According to one embodiment of this disclosure, a packaging structure is provided, including a lead frame, a semiconductor structure, connecting components, and a packaging material. The semiconductor structure is disposed on the lead frame, wherein a metal substrate is bonded to the lead frame, the connecting components electrically connect a redistribution layer to the lead frame, and the packaging material covers the semiconductor structure and the connecting components, and also covers the lead frame.

[0007] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising the following steps: providing an initial substrate having a front side and a back side; forming a semiconductor layer on the front side of the initial substrate; forming a top metal layer on the semiconductor layer; forming trenches in the semiconductor layer and the initial substrate; after the trenches are formed, grinding the back side of the initial substrate to reduce the thickness of the initial substrate to form a substrate; providing a metal carrier plate bonded to the substrate; forming a redistribution layer above the semiconductor layer and electrically connected to the top metal layer; forming a dielectric material covering the substrate and filling the trenches, wherein the redistribution layer is embedded in the dielectric material; and cutting along the trenches the dielectric material, the substrate, and the metal carrier plate to form a plurality of semiconductor structures separated from each other.

[0008] To make the features of this disclosure clear and easy to understand, embodiments are provided below, along with accompanying drawings, for detailed explanation. Simple Explanation of the Diagram

[0009] To facilitate understanding of the following text, the accompanying drawings and detailed textual descriptions should be consulted while reading this disclosure. The specific embodiments described herein, along with the corresponding drawings, are explained in detail to illustrate the working principles of these embodiments. Furthermore, for clarity, the features in the drawings may not be drawn to scale; therefore, the dimensions of some features in certain drawings may be intentionally enlarged or reduced. Figure 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure. Figure 2 is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of this disclosure. Figure 3 is a cross-sectional schematic diagram of the packaging structure of an embodiment disclosed herein. Figures 4, 5, 6 and 7 are schematic cross-sectional views of some stages of a method for manufacturing a semiconductor structure according to an embodiment of this disclosure. Figure 8 is a cross-sectional schematic diagram of an intermediate stage in a method for manufacturing a semiconductor structure according to another embodiment of this disclosure. Implementation

[0010] This disclosure provides several different embodiments that can be used to implement different features of this disclosure. For the sake of simplicity, this disclosure also describes examples of specific components and arrangements. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following statement regarding "a first feature forming on or above a second feature" may mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments in this disclosure may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any relation between different embodiments and / or configurations.

[0011] Furthermore, regarding the spatially related descriptive terms mentioned in this disclosure, such as "below," "low," "under," "above," "above," "up," "top," "bottom," and similar terms, for ease of description, their usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the diagram. In addition to the orientation shown in the diagram, these spatially related terms are also used to describe the possible orientation of the semiconductor structure during use and operation. As the orientation of the semiconductor structure changes (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should be interpreted in a similar manner.

[0012] Although this disclosure uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or sections, it should be understood that such elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of this disclosure, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0013] The terms "about" or "substantially" used in this disclosure generally mean within 20%, preferably within 10%, and even more preferably within 5%, 3%, 2%, 1%, or 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate; that is, the meaning of "about" or "substantially" may be implied even without specific mention of it.

[0014] The terms “coupled,” “coupled,” and “electrically connected” used in this disclosure include any means of direct or indirect electrical connection. For example, if the text describes a first component as coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other means of connection.

[0015] In this disclosure, "compound semiconductor" refers to a compound semiconductor comprising at least one group III element and at least one group V element, also known as a group III-V compound semiconductor. The group III element can be boron (B), aluminum (Al), gallium (Ga), or indium (In), while the group V element can be nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). Furthermore, "compound semiconductor" can be a binary, ternary, or quaternary compound semiconductor, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), analogs thereof, or combinations of the above compounds, but not limited thereto.

[0016] Although the invention disclosed herein is described below with reference to specific embodiments, the inventive principles of this invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details fall within the scope of knowledge of those skilled in the art.

[0017] This disclosure relates to a semiconductor structure with a metal carrier disposed under the bottom surface of a substrate, as well as its manufacturing method and packaging structure. The metal carrier can significantly improve the heat dissipation efficiency of the semiconductor structure, making it particularly suitable for semiconductor devices operating at high voltages and temperatures, such as high-frequency, high-power semiconductor devices using III-V compound semiconductors. Furthermore, during the manufacturing process of the semiconductor structure, the metal carrier can support the thinned substrate, thereby preventing cracks in the semiconductor layer. Additionally, the presence of the metal carrier facilitates the fabrication of a redistribution layer on the front side of the thinned substrate, preventing wafer warping caused by stress from a thicker redistribution layer, thus improving the yield of the semiconductor device.

[0018] Figure 1 is a cross-sectional schematic diagram of a semiconductor structure 100 according to an embodiment of this disclosure. The semiconductor structure 100 includes a substrate 102, a semiconductor layer 110, a top metal layer 107, a protective layer 109, a redistribution layer (RDL) 120, a dielectric material 130, and a metal carrier 114. The substrate 102 has a front surface and a bottom surface. The semiconductor layer 110 is disposed on the front surface of the substrate 102, and the metal carrier 114 is disposed below the bottom surface of the substrate 102. In addition, the side surfaces of the metal carrier 114, the substrate 102, the semiconductor layer 110, the protective layer 109, and the dielectric material 130 may all be on the same plane.

[0019] In some embodiments, substrate 102 may be a semiconductor substrate, such as a silicon substrate, or substrate 102 may be a composite substrate (QST (Qromis Substrate Technology) substrate). The composite substrate comprises a composite material layer enclosing a core layer, the core layer being, for example, a ceramic substrate composed of silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (Al₂O₃) (or sapphire substrate), or a combination thereof. The composite material layer comprises alternately stacked insulating layers and semiconductor bonding layers, the insulating layers being, for example, composed of silicon oxide, silicon nitride, silicon oxynitride, other suitable insulating materials, or a combination thereof, and the semiconductor bonding layers being, for example, composed of silicon or polycrystalline silicon, but not limited thereto. Compared to monocrystalline silicon substrates, using QST substrates as the base 102 not only offers higher mechanical strength, making it less prone to cracking or bending, but also provides better heat dissipation. For example, the thermal conductivity k-value of silicon substrates is approximately 1.1 W / m·K, while that of QST substrates is approximately 220 W / m·K. A higher thermal conductivity k-value indicates better thermal conductivity.

[0020] According to some embodiments disclosed herein, a QST substrate can provide excellent heat dissipation capabilities. For example, the thermal conductivity of a QST substrate is more than 100 times that of a silicon substrate, thus significantly improving the heat dissipation effect of the semiconductor structure. Furthermore, the addition of the metal carrier 114 of the embodiments disclosed herein further enhances the heat dissipation effect of the semiconductor structure. In some embodiments, the metal carrier 114 is, for example, a copper plate, a steel plate, or a stainless steel plate. Additionally, the thickness T1 of the metal carrier 114 can be 0.5 to 3 times the total thickness T2 of the substrate 102 and the semiconductor layer 110. For example, the thickness T1 of the metal carrier 114 can be approximately 400 μm to less than 300 µm (e.g., approximately 250 µm), and the total thickness T2 of the substrate 102 and the semiconductor layer 110 can be approximately 250 µm to less than 100 μm (e.g., approximately 80 µm), but is not limited to these dimensions. The thickness of the substrate 102 can be adjusted according to product requirements, and the total thickness T2 of the substrate 102 and the semiconductor layer 110 also changes accordingly.

[0021] In one embodiment, the semiconductor structure 100 may optionally include a back metal layer 112 disposed between the substrate 102 and the metal carrier 114. The back metal layer 112 facilitates bonding of the metal carrier 114 to the bottom surface of the substrate 102. The back metal layer 112 may be a single-layer structure or a multi-layer structure. The single-layer structure may be composed of, for example, gold (Au), silver (Ag), copper (Cu), or pre-solder. The multi-layer structure may be selected from the group consisting of Ni / Pd / Au, Ti / Ni / Ag, Ti / NiV / Ag, Cu / Ni / Au, Ti / Ni / Au, Ti / Cu, Ti / Au, Ni / Au, Au / As, and Al / Ni / Ag.

[0022] In some embodiments, the semiconductor layer 110 may comprise silicon, polycrystalline silicon, or a III-V compound semiconductor, and the semiconductor layer 110 may be a single semiconductor layer or a semiconductor stack, wherein the single semiconductor layer may be a silicon layer, a polycrystalline silicon layer, or a III-V compound semiconductor layer. The semiconductor stack may comprise stacked semiconductor sublayers, such as a plurality of III-V compound semiconductor sublayers, each of which may be composed of, for example, gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), aluminum nitride (AlN), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), or indium gallium nitride (InGaN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), or gallium indium arsenide (InGaAs), but is not limited thereto. In one embodiment, as shown in Figure 1, the semiconductor layer 110 may include at least a semiconductor channel layer 104 and a semiconductor barrier layer 106 stacked from bottom to top, wherein the semiconductor channel layer 104 is, for example, gallium nitride (GaN), and the semiconductor barrier layer 106 is, for example, aluminum gallium nitride (AlGaN). The semiconductor layer 110 can be used to fabricate high electron mobility transistors (HEMTs) or other high power transistors.

[0023] A top metal layer (TM) 107, for example, an aluminum-copper (AlCu) layer, is disposed on the semiconductor layer 110. A passivation layer 109 is also disposed on the semiconductor layer 110 and has an opening to expose the top metal layer 107. The passivation layer 109 is composed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. A dielectric material 130 is disposed on the passivation layer 109. According to the embodiments disclosed herein, the dielectric material 130 is composed of a molding compound, which may consist of a resin (e.g., epoxy resin, phenolic resin, or unsaturated polyester resin), a hardener, a filler, and other additives. Compared to other insulating materials (e.g., polyimide) or inorganic dielectric materials (e.g., silicon oxide, silicon nitride, and silicon oxynitride), forming the dielectric material 130 with a molding compound can provide better heat dissipation efficiency.

[0024] The redistribution layer (RDL) 120 includes multiple conductive layers and multiple conductive pillars / vias, embedded in the dielectric material 130. The redistribution layer 120 is electrically connected to the top metal layer 107, allowing transistors in the semiconductor layer 110 to be electrically connected to external circuits via the top metal layer 107 and the redistribution layer 120. Furthermore, the top surface of the redistribution layer 120 and the top surface of the dielectric material 130 may be on the same plane. A bonding pad 125 may also be provided on the top surface of the redistribution layer 120 for wire bonding or other bonding methods. In some embodiments, the redistribution layer 120 comprises copper (Cu) or aluminum (Al), and the bonding pad 125 may be a single-layer structure or a multi-layer structure. For example, the composition of a single-layer structure may include gold (Au) or silver (Ag), while the multi-layer structure may be selected from the group consisting of Ni / Au, Ti / Ni / Au, Ti / Cu, Ti / Au, Ni / Pd / Au, Au / As, Ni / Ag, and combinations thereof.

[0025] Figure 2 is a cross-sectional schematic diagram of a semiconductor structure 100 according to another embodiment of this disclosure. In this embodiment, the semiconductor layer 110 is a silicon layer, a polycrystalline silicon layer, or a combination thereof. Silicon-based transistors, such as trench metal-oxide-semiconductor (TMOS) transistors, laterally diffused metal-oxide-semiconductor (LDMOS) transistors, bipolar junction transistors (BJTs), complementary metal-oxide-semiconductor (CMOS) transistors, double-diffused metal-oxide-semiconductor (DMOS) transistors, or combinations thereof, can be fabricated in the semiconductor layer 110. Furthermore, the semiconductor structure 100 may selectively include a patterned insulating layer 108 disposed between the protective layer 109 and the dielectric material 130. The patterned insulating layer 108 is composed, for example, of polyimide. A patterned insulating layer 108 with fine patterns can be formed using exposure and development processes to further control the pitch between the exposed portions of the top metal layer 107. Additionally, in this embodiment, a back metal layer may not be provided between the substrate 102 and the metal carrier 114. The metal carrier 114 can be bonded to the bottom surface of the substrate 102 using silver paste or solder. Details of other features of the semiconductor structure 100 in Figure 2 can be found in the aforementioned description of the semiconductor structure 100 in Figure 1, and will not be repeated here.

[0026] Figure 3 is a cross-sectional schematic diagram of a packaging structure 200 according to an embodiment of this disclosure. The packaging structure 200 includes a lead frame 202, a semiconductor structure 100, a bonding material 204, a connecting member 206, and a packaging material 208. The semiconductor structure 100 is disposed on the lead frame 202, wherein a metal substrate 114 is bonded to the lead frame 202 via silver paste or solder (not shown). The bonding material 204, such as silver paste or solder, bonds the semiconductor structure 100 to the lead frame 202, and the bonding material 204 contacts the side surfaces of the substrate 102 and the metal substrate 114. A bonding pad 125 is disposed on a redistribution layer 120, and the connecting member 206 is bonded to the bonding pad 125 to electrically connect the redistribution layer 120 to the lead frame 202. In some embodiments, the connecting component 206 may be a wire or a clip or ribbon. The wire may be, for example, gold wire, copper wire, palladium-plated copper (PdCu) ​​wire, or silver wire. The ribbon may be, for example, copper sheet, aluminum ribbon, or tin ribbon. The encapsulation material 208 covers the semiconductor structure 100 and the connecting component 206, and also covers the lead frame 202. The encapsulation material 208 is composed of a molding compound, which may consist of a resin (e.g., epoxy resin, phenolic resin, or unsaturated polyester resin), a curing agent, filler, and other additives. In some embodiments, the composition of the encapsulation material 208 may be the same as the composition of the dielectric material 130 of the semiconductor structure 100.

[0027] In the embodiment shown in Figure 3, the patterned insulating layer 108 shown in Figure 2 may not be provided between the protective layer 109 and the dielectric material 130 of the semiconductor structure 100, and the back metal layer 112 shown in Figure 1 may not be provided between the substrate 102 and the metal carrier 114. Details of other features of the semiconductor structure 100 in Figure 3 can be found in the relevant description of the semiconductor structure 100 in Figure 1 above, and will not be repeated here. In addition, the semiconductor structures 100 in Figures 1 and 2 may also adopt the packaging structure 200 in Figure 3.

[0028] The package structure 200 of the disclosed embodiments is applicable to various package types, such as transistor outline (TO) package, small outline integrated circuit (SOIC) package, quad flat package (QFP), dual flat no-lead (DFN) package, quad flat no-lead (QFN) package, ball grid array (BGA) package, or other types of packages.

[0029] Figures 4, 5, 6, and 7 are schematic cross-sectional views of some stages of a method for manufacturing a semiconductor structure 100 according to an embodiment of the present disclosure. Referring to Figure 4, in step S101, an initial substrate 101 is first provided, having a front side 101F and a back side 101B. The thickness T3 of the initial substrate 101 is, for example, about 600 µm to 800 µm. Using an epitaxial growth process, a semiconductor layer 110, such as a silicon layer, a polycrystalline silicon layer, or a III-V compound semiconductor stack, is formed on the front side 101F of the initial substrate 101. Next, using a deposition and patterning process, a top metal layer 107 is formed on the semiconductor layer 110. Then, using a deposition process, a protective layer 109 is formed on the semiconductor layer 110, and using an etching process, an opening is formed in the protective layer 109 to expose the top metal layer 107. Subsequently, a laser grooving (LGV) process is applied to the front side 101F of the initial substrate 101 to form a trench 103. The trench 103 penetrates at least the protective layer 109 and the semiconductor layer 110, and the bottom surface of the trench 103 can be located in the initial substrate 101. The trench 103 can reduce the internal stress after the initial substrate 101 is subsequently thinned.

[0030] Referring again to Figure 4, in step S103, the back surface 101B of the initial substrate 101 is ground to reduce the thickness T3 of the initial substrate 101, forming substrate 102. The thickness T4 of substrate 102 is less than the thickness T3 of the initial substrate 101. In some embodiments, the thickness T4 of substrate 102 is, for example, about 100 µm to 200 µm. Next, in step S105, a metal substrate 114, such as a copper plate, steel plate, or stainless steel plate, is provided. The metal substrate 114 can be bonded to the bottom surface of substrate 102 using silver paste or solder. In some embodiments, the thickness of the metal substrate 114 is, for example, about 100 µm to 300 µm, and the thickness of the metal substrate 114 can be about 0.5 times to about 3 times the total thickness of substrate 102 and semiconductor layer 110.

[0031] Referring to Figure 5, in step S107, an electroplating process is used to form metal pillars 121 on the top metal layer 107. Next, in step S109, a coating and filling process is used to form a first molding sealant 131 that fills the trench 103 and covers the metal pillars 121. Then, in step S111, the first molding sealant 131 is ground until the surface 131S of the first molding sealant 131 exposes the metal pillars 121.

[0032] Referring to Figure 6, in step S113, an electroplating process is used to form a first conductive layer 122 on the first molding material 131, which is connected to the metal pillar 121. Next, in step S115, a coating and filling process is used to form a second molding material 132, which covers the first conductive layer 122. Then, the second molding material 132 is ground to expose the first conductive layer 122.

[0033] Referring to Figure 7, in step S117, an electroplating process is used to form a second conductive layer 123 on the first conductive layer 122, connecting it to the first conductive layer 122. Then, a coating and filling process is used to form a third molding compound 133, covering the second conductive layer 123. Next, the third molding compound 133 is ground to expose the second conductive layer 123. The metal pillars 121, the first conductive layer 122, and the second conductive layer 123 formed in the aforementioned steps can constitute a redistribution layer 120, and the first molding compound 131, the second molding compound 132, and the third molding compound 133 formed in the aforementioned steps can constitute a dielectric material 130. In some embodiments, the compositions of the first molding compound 131, the second molding compound 132, and the third molding compound 133 can be the same, for example, all composed of epoxy resin. The compositions of the metal pillars 121, the first conductive layer 122, and the second conductive layer 123 can be the same, for example, all composed of copper. In addition, steps S113 and S115 can be repeated to form more layers of conductive material and molding material.

[0034] In step S117, a redistribution layer 120 is formed above the semiconductor layer 110, embedded in the dielectric material 130, and electrically connected to the top metal layer 107. The dielectric material 130 covers the substrate 102 and the metal carrier 114, and fills the trench 103. Next, an electroplating process can be used to form bonding pads 125, such as a Ni / Au stacked structure, on the redistribution layer 120. Then, in step S119, a blade saw or a die-cutting process can be used to cut the dielectric material 130, the substrate 102, and the metal carrier 114 along the trench 103 to form a plurality of separate semiconductor structures 100.

[0035] In this embodiment, before forming the metal pillar 121 in step S107, the thickness of the initial substrate 101 is reduced in step S103 to form the substrate 102, and the metal carrier plate 114 is bonded to the substrate 102 in step S105.

[0036] Figure 8 is a cross-sectional schematic diagram of an intermediate stage in a method for manufacturing a semiconductor structure according to another embodiment of the present invention. First, in step S201, an initial substrate 101 is provided, and a semiconductor layer 110 is formed on the front side 101F of the initial substrate 101 using an epitaxial growth process. A top metal layer 107 is formed on the semiconductor layer 110 using a deposition and patterning process. A protective layer 109 is formed on the semiconductor layer 110 using a deposition and etching process, and has openings to expose the top metal layer 107. Next, a trench 103 is formed using a laser grooving (LGV) process. The trench 103 passes through the protective layer 109 and the semiconductor layer 110, and the bottom surface of the trench 103 is located in the initial substrate 101. Then, a metal pillar 121 is formed on the top metal layer 107 using an electroplating process. Next, a first molding compound 131 is formed using a coating and filling process to cover the initial substrate 101, fill the trench 103, and encapsulate the metal pillar 121. Then, the first molding material 131 is ground until the metal pillar 121 is exposed.

[0037] Referring again to Figure 8, in step S203, the back surface 101B of the initial substrate 101 is ground to reduce the thickness T3 of the initial substrate 101, forming substrate 102. The thickness T4 of substrate 102 is less than the thickness T3 of the initial substrate 101. In some embodiments, the thickness T4 of substrate 102 is, for example, about 100 µm to 200 µm. Next, in step S205, a metal carrier 114 is provided, such as a surface-treated copper plate, steel plate, or stainless steel plate, which can be bonded to the bottom surface of substrate 102 by silver paste or solder. Subsequently, following steps S113 and S115 of Figure 6 and steps S117 and S119 of Figure 7, a plurality of semiconductor structures 100 separated from each other are formed.

[0038] In this embodiment, after forming the metal pillar 121 and grinding the first molding material 131 in step S201, the thickness of the initial substrate 101 is reduced in step S203 to form the substrate 102, and the metal carrier plate 114 is bonded to the substrate 102 in step S205.

[0039] According to some embodiments disclosed herein, during the manufacturing process of semiconductor structures, a metal substrate can support the thinned substrate, preventing cracks in the semiconductor layer. Furthermore, the metal substrate facilitates the fabrication of a redistribution layer on the front side of the thinned substrate, preventing stress from the thicker redistribution layer causing substrate warping, thereby improving the yield of semiconductor devices. In addition, the metal substrate can significantly improve the heat dissipation efficiency of semiconductor structures, making it particularly suitable for semiconductor devices operating at high voltage and high temperature, such as high-frequency, high-power semiconductor devices using III-V compound semiconductors. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0040] 100: Semiconductor Structure 101: Initial base 101F: Front 101B: Back 102: Base 103: Trench 104: Semiconductor Channel Layer 106: Semiconductor barrier layer 107: Top Metal Layer 108: Patterned insulating layer 109: Protective layer 110: Semiconductor layer 112: Backside metal layer 114: Metal Carrier Plate 120: Redistribution layer 121: Metal Column 122: First Conductor Layer 123: Second conductor layer 125: Joint Pad 130: Dielectric materials 131: First mold sealing material 131S: Surface 132: Second mold sealing material 133: Third mold sealing material 200: Package structure 202: Conductor frame 204: Fixation material 206: Connecting components 208: Packaging Material T1, T2, T3, T4: Thickness S101, S103, S105, S107, S109, S111, S113, S115, S117, S119, S201, S203, S205: Steps

Claims

1. A semiconductor structure, comprising: A substrate having a front surface and a bottom surface; a semiconductor layer disposed on the front surface of the substrate; A metal carrier plate is disposed below the bottom surface of the substrate; a top metal layer is disposed on the semiconductor layer; a redistribution layer is electrically connected to the top metal layer; and a dielectric material is disposed above the semiconductor layer, wherein the redistribution layer is embedded in the dielectric material, wherein the dielectric material comprises a molding compound and completely covers the sides of the redistribution layer; wherein the sides of the metal carrier plate, the sides of the substrate, the sides of the semiconductor layer, and the sides of the dielectric material are all on the same plane.

2. The semiconductor structure as claimed in claim 1, wherein the thickness of the metal substrate is 0.5 to 3 times the total thickness of the substrate and the semiconductor layer, and the metal substrate includes a copper plate, a steel plate or a stainless steel plate.

3. The semiconductor structure as claimed in claim 1 further includes a protective layer disposed between the semiconductor layer and the dielectric material, the protective layer having an opening to expose the top metal layer.

4. The semiconductor structure as described in claim 3, wherein the side surface of the protective layer and the side surface of the dielectric material are both on the same plane.

5. The semiconductor structure as described in claim 3 further includes a patterned insulating layer disposed between the protective layer and the dielectric material, wherein the patterned insulating layer comprises polyimide.

6. The semiconductor structure as claimed in claim 1, wherein the substrate includes a semiconductor substrate or a composite substrate, the composite substrate including a core layer and a composite material layer enclosing the core layer.

7. The semiconductor structure as claimed in claim 6, wherein the semiconductor substrate is composed of silicon, the core layer is composed of silicon carbide (SiC), aluminum nitride (AlN) or aluminum oxide (Al2O3), and the composite material layer includes an insulating layer and a semiconductor bonding layer.

8. The semiconductor structure as claimed in claim 1 further includes a high electron mobility transistor or a silicon-based transistor disposed in the semiconductor layer, wherein the semiconductor layer comprises a III-V compound semiconductor, silicon, or polycrystalline silicon.

9. The semiconductor structure as claimed in claim 1, wherein the top surface of the redistribution layer and the top surface of the dielectric material are on the same plane, and the composition of the redistribution layer includes copper or aluminum.

10. The semiconductor structure as claimed in claim 1 further includes a back metal layer disposed between the substrate and the metal carrier, wherein the back metal layer comprises a single-layer structure or a multi-layer structure, the single-layer structure comprising Au, Ag, Cu or pre-solder, and the multi-layer structure being selected from the group consisting of Ni / Pd / Au, Ti / Ni / Ag, Ti / NiV / Ag, Cu / Ni / Au, Ti / Ni / Au, Ti / Cu, Ti / Au, Ni / Au, Au / As and Al / Ni / Ag.

11. A packaging structure, comprising: A conductor frame; A semiconductor structure as described in claim 1 is disposed on the lead frame, wherein the metal substrate is bonded to the lead frame; a connecting member electrically connecting the redistribution layer to the lead frame; and an encapsulation material covering the semiconductor structure and the connecting member, and covering the lead frame.

12. The packaging structure as described in claim 11, wherein the composition of the dielectric material is the same as the composition of the packaging material, including a molding compound.

13. The encapsulation structure as described in claim 11 further includes: A bonding pad is disposed on the redistribution layer, and the connecting member is bonded to the bonding pad; And a fixing material is used to attach the semiconductor structure to the lead frame, wherein the fixing material contacts the side of the substrate and the side of the metal carrier.

14. The packaging structure as described in claim 11, wherein the connecting component includes a metal wire or a metal strip, the metal wire including gold wire, copper wire, palladium-plated copper (PdCu) ​​wire or silver wire, and the metal strip including copper sheet, aluminum strip or tin strip.

15. A method for manufacturing a semiconductor structure, comprising: An initial substrate is provided, having a front side and a back side; A semiconductor layer is formed on the front side of the initial substrate; A top metal layer is formed on the semiconductor layer; a trench is formed in the semiconductor layer and the initial substrate; after the trench is formed, the back side of the initial substrate is ground to reduce the thickness of the initial substrate, thereby forming a substrate; A metal carrier plate is provided and bonded to the substrate; a redistribution layer is formed above the semiconductor layer and electrically connected to the top metal layer; a dielectric material is formed to cover the substrate and fill the trench, wherein the redistribution layer is embedded in the dielectric material; and the dielectric material, the substrate and the metal carrier plate are cut along the trench to form a plurality of semiconductor structures that are separate from each other.

16. A method for manufacturing a semiconductor structure as described in claim 15, wherein forming the redistribution layer and the dielectric material comprises: A metal pillar is formed on the top metal layer; A first sealing material is formed to fill the groove and cover the metal pillar; The first molding material is ground to expose the metal pillar; a first conductive layer is formed on the first molding material and connected to the metal pillar; A second molding material is formed to cover the first conductive layer; the second molding material is ground to expose the first conductive layer; A second conductive layer is formed and connected to the first conductive layer; A third sealing material is formed to cover the second conductive layer; The third molding material is ground to expose the second conductive layer, wherein the metal pillar, the first conductive layer and the second conductive layer constitute the redistribution layer, and the first molding material, the second molding material and the third molding material constitute the dielectric material.

17. A method of manufacturing a semiconductor structure as claimed in claim 16, wherein, prior to forming the metal pillar, the thickness of the initial substrate is thinned to form the substrate, and the metal carrier plate is bonded to the substrate.

18. A method of manufacturing a semiconductor structure as claimed in claim 16, wherein after forming the metal pillar and grinding the first molding material, the thickness of the initial substrate is thinned to form the substrate, and the metal carrier plate is bonded to the substrate.

19. The method for manufacturing the semiconductor structure as described in claim 15, further comprising: A protective layer is formed on the semiconductor layer, the protective layer having an opening to expose the top metal layer, wherein the trench is also formed in the protective layer, and forming the trench includes a laser grooving process applied to the front side of the initial substrate.

20. A method for manufacturing a semiconductor structure as claimed in claim 15, wherein the thickness of the metal substrate is 0.5 to 3 times the total thickness of the substrate and the semiconductor layer, and the metal substrate includes a copper plate, a steel plate, or a stainless steel plate.

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