Semiconductor device and method of manufacturing the same

Abstract

The method includes forming fins protruding from a substrate; forming a dummy gate stack extending beyond the fins, the dummy gate stack including a dummy gate dielectric layer, a dummy gate on the dummy gate dielectric layer, and an oxide layer on the sidewalls of the dummy gate; forming a plurality of gate spacers on the sidewalls of the dummy gate stack; removing the dummy gates; recessing the oxide layer; passivating surface portions of the gate spacers to form a passivation layer on the oxide layer; removing the passivation layer, the oxide layer, and the dummy gate dielectric layer to form a gate trench; depositing a metal gate stack in the gate trench; and recessing the metal gate stack. The top of the passivation layer is wider than the bottom of the passivation layer.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device and a method of forming the same, and more particularly to a process for forming a metal gate. [Previous Technology]

[0002] Semiconductor integrated circuits have experienced exponential growth. Technological advancements in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (i.e., the number of interconnect devices per unit wafer area) typically increases as geometry (i.e., the smallest component or line that the manufacturing process can produce) shrinks. Shrinking processes generally facilitate increased production capacity and reduced associated costs. Shrinking also increases the complexity of handling and manufacturing integrated circuits.

[0003] As technology nodes shrink, some integrated circuit designs have progressed towards replacing polysilicon gates with metal gates to improve device performance in smaller structures. The process of forming a metal gate can be called gate replacement or gate-after-gate fabrication, where the metal gate is fabricated last to reduce the number of subsequent processes. Gate replacement typically involves forming a dummy gate to reserve space for the metal gate, followed by removing the dummy gate to form the gate trench used in the metal gate filler process. In the metal gate filler process, multiple metal layers, such as a work function metal layer and a metal filler layer, can be sequentially deposited in the gate trench. However, implementing this integrated circuit fabrication process remains challenging, especially for smaller integrated circuits at advanced process nodes. One challenge is the narrow opening of the gate trench, which can trap voids (which can also be considered gaps due to their high aspect ratio) within the gate trench during the metal gate filler process. These voids can introduce breakdown defects during the metal gate etch-back process. The narrow opening of the gate trench can also make it difficult to remove the temporarily present interstitial layer from the gate trench. Although the existing methods meet many requirements, further improvements are needed in the formation of metal gates as transistor sizes continue to shrink to the next 10 nanometer technology node. [Summary of the Invention]

[0004] An exemplary embodiment of the present invention relates to a method for manufacturing a semiconductor device. The method includes: interleaving and stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers on a substrate; patterning the first semiconductor layers and second semiconductor layers into fins; forming a dummy gate stack over the fins, the dummy gate stack including a dummy gate dielectric layer and a gate located on the dummy gate dielectric layer; forming a gate sidewall oxide layer on the sidewalls of the dummy gate stack; depositing a plurality of gate spacers on the gate sidewall oxide layer; recessing the dummy gates and the gate sidewall oxide layer to form a gate trench exposing the gate spacers; passivating the tops of the gate spacers, with the passivated tops of the gate spacers decreasing in width from top to bottom; removing the passivated tops of the gate spacers and the gate sidewall oxide layer from the gate trench; removing the dummy gate dielectric layer from the gate trench; removing the first semiconductor layer from the gate trench to release the second semiconductor layer as a plurality of channel components; and depositing a metal gate stack in the gate trench to cover each of the second semiconductor layers.

[0005] Another exemplary embodiment of the present invention relates to a method for manufacturing a semiconductor device. The method includes forming a fin protruding from a substrate; forming a dummy gate stack extending over the fin, the dummy gate stack including a dummy gate dielectric layer, dummy gates located on the dummy gate dielectric layer, and an oxide layer located on the sidewalls of the dummy gates; forming a plurality of gate spacers on the sidewalls of the dummy gate stack; removing the dummy gates; recessing the oxide layer to a first position, the first position being perpendicularly spaced from the upper surface of the fin by a first height; passivating surface portions of the gate spacers to form a passivation layer higher than the oxide layer, the top of the passivation layer being wider than the bottom of the passivation layer; removing the passivation layer, the oxide layer, and the dummy gate dielectric layer to form a gate trench; depositing a metal gate stack in the gate trench; and recessing the metal gate stack to a second position, the second position being perpendicularly spaced from the upper surface of the fin by a second height.

[0006] Another exemplary embodiment of the present invention relates to a semiconductor device. The semiconductor device includes a plurality of channel components vertically suspended on a substrate; a gate stack covering each of the channel components; an epitaxial structure adjacent to the channel components; and a plurality of gate spacers located on the sidewalls of the gate stack. The width of the top of the gate stack decreases in the downward direction, while the width of the middle portion of the gate stack is fixed.

Implementation Method

[0008] The following detailed description is illustrated in conjunction with the accompanying drawings to facilitate understanding of various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity of explanation.

[0009] The different embodiments or examples provided below can implement different structures of the embodiments of the present invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the invention. For example, a description of forming a first component on a second component includes direct contact between the two, or the two being separated by other additional components rather than in direct contact. Various embodiments of the present invention may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0010] Furthermore, spatially relative terms such as "below," "below," "lower," "above," "higher," or similar terms are used to describe the relationship between some elements or structures in the diagram and another element or structure. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is rotated in a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the rotation. In addition, when a numerical value or range is described with terms such as "about," "approximately," or similar terms, it includes + / - 10% of the stated value unless otherwise specified. For example, the term "about 5 nm" includes a size range of 4.5 nm to 5.5 nm.

[0011] The embodiments of the present invention generally relate to semiconductor devices and methods of forming them, and more particularly to the formation process of metal gates, which can be used in a variety of device types.

[0012] Some device types are related to, but not limited to, multi-gate devices. Multi-gate devices have been introduced to improve gate control, reduce off-state current, and reduce short-channel effects by increasing gate-channel coupling. One type of introduced multi-gate device is the fin field-effect transistor (FET). The name fin field-effect transistor comes from the fin-like structure extending from the substrate on which the FET is formed, which forms the channel of the FET. Another multi-gate device introduced to address the performance challenges associated with fin field-effect transistors is the fully wound gate transistor (WWT). The name WWT comes from the fact that its gate structure can extend around the channel region (such as a stack of nanosheets) to access the four sides of the channel. WWT is compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and can maintain gate control and mitigate short-channel effects while significantly reducing the size of the structure. The following description will illustrate various embodiments of the invention with examples of one or more fully wound gates. However, it should be understood that embodiments of the invention are not limited to specific device types unless specifically stated in the claims. For example, embodiments of the present invention can be used to implement finned field-effect transistors or planar field-effect transistors.

[0013] As transistor dimensions continue to shrink to the next 10-nanometer technology node or smaller, dummy gates are defined as gate trenches on fin structures (such as fins used in fin field-effect transistor devices, or patterned stacks of staggered sacrificial and channel layers used in fully wound gate devices), which may have aspect ratios and / or bottleneck profiles. For simplicity, the terms fin structure and fin are used interchangeably in the following description.

[0014] When multiple metal layers are sequentially deposited in a gate trench, voids or gaps may be easily captured in the gate trench due to its high aspect ratio and / or bottleneck profile. During the metal gate etch-back process, the etchant may seep into the gaps and etch the metal layers inconsistently, causing breakdown defects and poor growth of the gate metal cap. The high aspect ratio and / or bottleneck profile of the gate trench also makes it difficult to remove temporary layers (such as sacrificial layers in fins and / or interstitial layers when forming power function metal layers). In some embodiments of the present invention, when removing dummy gates to form a gate trench, the profile of the gate trench is reconstructed to have a wider opening. A gradient passivation process (such as a gradient oxidation process) is performed to passivate the surface portion of the gate spacer facing the gate trench. Due to the gradient passivation process, the passivated surface portion near the opening of the gate trench is thicker, while the passivated surface portion near the bottom of the gate trench is thinner. The passivated surface portion of the gate spacer is then removed using a selective etching process. Removing the passivated surface portion increases the opening of the gate trench. The increased opening facilitates the subsequent deposition of the work function metal layer and metal filler layer to fill the gate trench without trapping voids or gaps. This metal gate formation process improves the consistency and integrity of the gate metal layer, resulting in better transistor performance.

[0015] FIG1 is a flowchart of a method 10 for forming a semiconductor device according to an embodiment of the present invention. Method 10 is merely illustrative and not limited to embodiments of the present invention up to the point not actually described in the claims. Additional steps may be provided before, during, and after method 10, and additional embodiments of the method may substitute, omit, or interchange some of the steps. Method 10 will be described below in conjunction with FIGS. 2 to 36C, which are perspective and cross-sectional views of various fabrication steps of semiconductor device 100 in some embodiments of method 10. Semiconductor device 100 may be an intermediate device for fabricating integrated circuits or portions thereof, which may include static random access memory and / or logic circuits, passive components (such as resistors, capacitors, and inductors), and active components (such as p-type field-effect transistors, n-type field-effect transistors, metal-oxide-semiconductor field-effect transistors, complementary metal-oxide-semiconductor transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, or combinations thereof). Furthermore, the transistors, gate stacks, active regions, isolation structures, and other structures in various embodiments of the present invention are only for simplification and ease of understanding, and are not intended to limit the embodiments to any kind of device, any number of devices, any number of regions, or any configuration of structure or region.

[0016] As shown in Figures 1 and 2, step 12 of method 10 provides or receives a precursor for semiconductor device 100. For ease of explanation, the precursor for semiconductor device 100 may also be considered as device 100. Device 100 may include a substrate 101 and various structures formed therein or on it. In some embodiments, substrate 101 includes a crystalline silicon substrate (such as a wafer). Substrate 101 may include various doped regions (such as p-type wells and / or n-type wells), depending on design requirements. In some embodiments, the doped regions may be doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants such as boron or boron difluoride, n-type dopants such as phosphorus or arsenic, and / or combinations thereof. The doped regions may be configured for n-type transistors or alternatively configured for p-type transistors. In some embodiments, breakdown-resistant implants are made on top of substrate 101 to form breakdown-resistant regions. The conductivity type of the dopants implanted in the breakdown-resistant regions may be the same as the conductivity type of the doped regions (or wells). The breakdown region may extend below the subsequently formed source / drain regions to reduce leakage current from the source / drain regions to the substrate 101. The source / drain regions may be considered individually or together as sources or drains, depending on the context. For clarity, doped regions and breakdown regions are not shown in FIG1 and subsequent figures. In some embodiments, the substrate 101 includes semiconductor elements such as silicon or germanium, semiconductor compounds (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, or gallium arsenide phosphide indium), or combinations thereof.

[0017] The device 100 includes a semiconductor stack 102 formed on a substrate 101. The semiconductor stack 102 may include a plurality of first layers 104 and a plurality of second layers 106 stacked alternately in the Z direction. Although FIG2 only shows three first layers 104 and three second layers 106, the embodiments of the present invention are not limited thereto. In other embodiments, the number of first layers 104 and second layers 106 may be adjusted as needed, such as one, two, or more first layers 104 and second layers 106.

[0018] In some embodiments, the first layer 104 and the second layer 106 comprise different materials. For example, the first layer 104 is a silicon-germanium layer with a germanium atom content between about 15% and 40%, while the second layer 106 is a germanium-free silicon layer. However, the embodiments of the present invention are not limited thereto, and in other embodiments, the first layer 104 and the second layer 106 are materials with different etching selectivity. In some embodiments, the first layer 104 and the second layer 106 are formed by an epitaxial growth process, such as molecular beam epitaxy, metal-organic chemical vapor deposition, or a similar process. In this example, the first layer 104 is an epitaxial silicon-germanium layer, and the second layer 106 is an epitaxial silicon layer. In some other embodiments, the first layer 104 and the second layer 106 are formed by a suitable deposition process, such as chemical vapor deposition, atomic layer deposition, or a similar process. In this example, the first layer 104 is a polycrystalline silicon-germanium layer, and the second layer 106 is a polycrystalline silicon layer.

[0019] The first layer 104 and the second layer 106 may have the same or different thicknesses. In some embodiments, the first layer 104 has the same thickness T1, while the second layer 106 has the same thickness T2. In some embodiments, the thickness T1 is about 5 nm to about 20 nm, and the thickness T2 is about 5 nm to about 20 nm. The first layer 104 from top to bottom may be modified to have different thicknesses, while the second layer 106 from top to bottom may have different thicknesses.

[0020] The device 100 also includes a masking layer 108 formed on the semiconductor stack 102. The masking layer 108 may include a single-layer structure, a double-layer structure, or a multi-layer structure. For example, the masking layer 108 includes a silicon oxide layer and a silicon nitride layer located on the silicon oxide layer. In some embodiments, the masking layer 108 is formed by chemical vapor deposition, atomic layer deposition, or similar methods.

[0021] As shown in Figures 1 and 3, step 14 of method 10 patterns the mask layer 108, the semiconductor stack 102 of the first layer 104 and the second layer 106, and the top of the substrate 101 to form a fin 110. In some embodiments, the mask layer 108 is patterned to form a plurality of mask strips 109. The mask strips 109 are then used as masks to pattern the semiconductor stack 102 and the substrate 101 to form a plurality of trenches 118. In this example, a plurality of fin substrates 111 and a plurality of semiconductor strip stacks such as nanosheet stacks 112 thereon may be formed between the trenches 118. The trenches 118 extend into the substrate 101 and their lengths are parallel to each other. The combination of the fin substrates 111 and the nanosheet stacks 112 thereon can be considered as the fin 110. As shown in Figure 3, the nanosheet stack 112 includes a plurality of first nanosheets 114 and a plurality of second nanosheets 116 stacked alternately along the Z direction and extending along the Y direction.

[0022] In some embodiments, the fin 110 can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the fin, including dual patterning or multiple patterning processes. Dual patterning or multiple patterning processes combine photolithography with a self-alignment process, resulting in a pattern spacing smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 110.

[0023] Although only two fins 110 are shown in Figure 3, the embodiments of the present invention are not limited thereto. In other embodiments, the number of fins 110 can be adjusted as needed, such as one fin, three fins, four fins, or more fins. Furthermore, the masking strip 109 shown in Figure 3 has a flat upper surface. However, the embodiments of the present invention are not limited thereto. In other embodiments, the masking strip 109 may have a domed upper surface due to high aspect ratio etching.

[0024] As shown in Figures 1 and 4, step 16 of method 10 forms an insulating layer 113 in the trench 118. In some embodiments, an insulating material is formed on a substrate 101 to cover the fins 110 and fill the trench 118. In addition to the fins 110, the insulating material also covers a masking tape 109. The insulating material may include silicon oxide, silicon nitride, silicon oxynitride, spin-coated dielectric material, or a low dielectric constant dielectric material. Here, a low dielectric constant dielectric material is a general dielectric material with a dielectric constant below 5.0, such as a dielectric material with a dielectric constant lower than that of silicon oxide (approximately 3.9). The insulating material may be formed by flowable chemical vapor deposition, high-density plasma chemical vapor deposition, sub-pressure chemical vapor deposition, or spin coating. A planarization process may be performed to remove a portion of the insulating material and the masking tape 109 until the fins 110 are exposed. In the example shown in Figure 4, the upper surface 110t of the fin 110 may be substantially coplanar with the upper surface 113t of the planarized insulating layer 113. In some embodiments, the planarization process includes chemical mechanical polishing, etch-back process, a combination of the above, or similar processes.

[0025] As shown in Figures 1 and 5, step 18 of method 10 recesses the insulating layer 113 to form a plurality of isolation regions 115. After recessing the insulating layer 113, the fins 110 may protrude from the upper surface 115t of the isolation regions 115. That is, the upper surface 115t of the isolation regions 115 may be lower than the upper surface 110t of the fins 110. In some embodiments, the nanosheet stack 112 may be exposed from the isolation regions 115. That is, the upper surface 115t of the isolation regions 115 may be substantially coplanar with or lower than the lower surface 112bt of the nanosheet stack 112. Furthermore, the upper surface 115t of the isolation regions 115 may be a flat surface, a convex surface, a recessed surface (such as a disc), or a combination thereof, as illustrated. In some embodiments, the method for recessing the insulating layer 113 may employ a suitable etching process such as a wet etching process with hydrofluoric acid, a dry etching process, or a combination thereof. In some embodiments, the height difference between the upper surface 110t of the fin 110 and the upper surface 115t of the isolation region 115 may be from about 30 nm to about 100 nm. In some embodiments, the isolation region 115 may be a shallow trench isolation region, a deep trench isolation region, or the like.

[0026] As shown in Figures 1 and 6, step 20 of method 10 forms a dummy dielectric layer 120 on the substrate 101. In some embodiments, the dummy dielectric layer 120 compliantly covers the surface of the nanosheet stack 112 and the upper surface 115t of the isolation region 115. In some embodiments, the dummy dielectric layer 120 includes silicon oxide, silicon nitride, silicon oxynitride, or the like, and is formed by chemical vapor deposition, atomic layer deposition, or similar methods. In some embodiments, the thickness of the dummy dielectric layer 120 may be from about 1 nm to about 5 nm. The dummy dielectric layer 120 and the isolation region 115 may have the same or different dielectric materials.

[0027] As shown in Figures 1 and 7, step 22 of method 10 forms a dummy gate stack 122 on a portion of the nanosheet stack 112 and a portion of the isolation region 115. The dummy gate stack 122 may extend along the Y direction, which is perpendicular to the extension direction of the nanosheet stack 112. That is, the dummy gate stack 122 extends beyond the nanosheet stack 112. Specifically, the dummy gate stack 122 may include a dummy gate 124 and a portion of the dummy dielectric layer 120 covered by the dummy gate 124. The step of patterning the dummy gate stack 122 may remove the uncovered portion of the dummy dielectric layer 120. The portion of the dummy dielectric layer 120 covered by the dummy gate 124 described herein can be regarded as the dummy gate dielectric layer 120m. In some embodiments, the dummy gate 124 comprises a silicon-containing material such as polycrystalline silicon, amorphous silicon, or a combination thereof. The dummy gate 124 may be formed using suitable processes such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or a combination thereof. Although the dummy gate 124 shown in FIG. 7 is a single-layer structure, the embodiments of the present invention are not limited thereto. In other embodiments, the dummy gate 124 may be a multilayer structure. The dummy gate stack 122 may also include a hard masking layer 126 on the dummy gate 124. In some embodiments, the hard masking layer 126 includes a single-layer structure, a double-layer structure, or a multilayer structure. Taking FIG. 7 as an example, the hard masking layer 126 includes a silicon oxide layer 126a and a silicon nitride layer 126b located on the silicon oxide layer 126a.

[0028] Although not illustrated, after forming the dummy gate stack 122, method 10 may include a cleaning process to clean the surface of the dummy gate stack 122. The cleaning process may include dry etching, wet etching, or a combination thereof. In some examples, wet cleaning may employ a mixture of deionized water and ammonium hydroxide and hydrogen peroxide, a mixture of deionized water and hydrogen chloride and hydrogen peroxide, a mixture of sulfuric acid and hydrogen peroxide, and / or hydrofluoric acid to remove oxides. Dry cleaning processes may include helium and hydrogen treatment. The cleaning process may passivate the sidewall surface of the dummy gate 124. In some embodiments, the sidewall surface of the dummy gate 124 is oxidized to form an oxide layer 125. For example, when the dummy gate 124 is composed of polycrystalline silicon, the oxide layer 125 may be a thin film of silicon oxide. In some embodiments, the cleaning process may be omitted, but the sidewall surface of the dummy gate 124 may still be oxidized due to exposure to an oxygen-containing environment. Since the oxide layer 125 is formed on the sidewall of the dummy gate stack 122, the oxide layer 125 can also be regarded as a gate sidewall oxide layer. Since the oxide layer 125 is a byproduct of the clean process or native oxidation process, the oxide layer 125 can also be regarded as a native oxide layer. The thickness of the oxide layer 125 can be from about 0.5 nm to about 3 nm, which is less than the thickness of the dummy gate dielectric layer 120 nm. The density of the oxide layer 125 can also be less than the density of the dummy gate dielectric layer 120 nm.

[0029] As shown in FIG. 7, a gate spacer 128 is also formed on the sidewall of the dummy gate stack 122. Similar to the dummy gate stack 122, the gate spacer 128 also extends beyond the nanosheet stack 112. In some embodiments, the gate spacer 128 may be composed of one or more dielectric materials such as silicon carbonitride, silicon carbide, silicon carbonitride, silicon carbonoxide, silicon oxynitride, or a combination thereof. In some embodiments, the gate spacer 128 may include a material with a low dielectric constant, such as less than about 5.0, for example, less than or equal to about 3.9. For example, the gate spacer 128 in some embodiments may include a porous dielectric material, a dielectric material with an extremely low dielectric constant (such as silicon hydroxide), or the like. The gate spacer 128 may or may not include an air gap (not shown) to further reduce its dielectric constant. The low dielectric constant of the gate spacer 128 is beneficial for reducing parasitic capacitance between the subsequently formed metal gate structure and the source / drain junction, particularly in advanced node technologies where the metal gate structure is located close to the source / drain junction. In some embodiments, the thickness of the gate spacer 128 may be from about 1 nm to about 10 nm. The gate spacer 128 may be a single-layer or multi-layer structure. For example, the gate spacer 128 may include a first gate spacer layer and a second gate spacer layer located on the first gate spacer layer, and the two layers are composed of different dielectric materials. The dummy gate stack 122 and the gate spacer 128 cover the middle portion of the nanosheet stack 112, but do not cover and expose the two end portions of the nanosheet stack 112.

[0030] As shown in Figures 1 and 8, step 24 of method 10 recesses the end portion of the nanosheet stack 112 to form a recess. This recess can be considered as a source / drain recess 130. In some embodiments, the end portion of the nanosheet stack 112 may be removed by an anisotropic etching process, an isotropic etching process, or a combination thereof. In some embodiments, the source / drain recess 130 extends further into the fin substrate 111 and is below the upper surface 115t of the isolation region 115. In other words, the end portion of the nanosheet stack 112 is completely removed, and the top of the fin substrate 111 is further removed. In the example shown in Figure 8, the lower surface 130bt of the source / drain recess 130 is below the upper surface 115t of the isolation region 115. In some embodiments, some horizontal portions of the gate spacer 128 are removed, while the remaining vertical portions of the gate spacer 128 are retained on and aligned with the edge of the isolation region 115, and source / drain recesses 130 are formed between the vertical portions of the gate spacer and between the isolation region 115. The vertical portions of the gate spacer 128 cover the sidewalls of the dummy gate stack 122, which includes a dummy gate dielectric layer 120m, a dummy gate 124, and a hard mask layer 126.

[0031] As shown in Figures 1 and 9, step 26 of method 10 forms inner spacers 132 at both ends of the first nanosheet 114. In some embodiments, the ends of the first nanosheet 114 exposed in the source / drain recesses 130 may be selectively recessed to form inner spacer recesses (not shown), and the second nanosheet 116 is not substantially etched. In embodiments where the second nanosheet 116 is substantially composed of silicon and the first nanosheet 114 is substantially composed of silicon-germanium, the method of selectively recessing the first nanosheet 114 may include a silicon-germanium oxide process followed by a process for removing the silicon-germanium oxide. The silicon-germanium oxide process may employ ozone. In some other embodiments, the selective recessing step may be a selective isotropic etching process (such as a selective dry etching process or a selective wet etching process), and the amount of recess in the first nanosheet 114 may be controlled by the time of the etching process. Selective dry etching processes may employ one or more fluorine-based etchants such as fluorine gas or hydrocarbons. Selective wet etching processes may include hydrofluoric acid or ammonium hydroxide etchants. After forming the inner spacer recesses, an inner spacer material layer may be deposited on the semiconductor device 100, including forming in the inner spacer recesses. The inner spacer material layer may include silicon oxide, silicon nitride, silicon oxide carbon, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. The deposited inner spacer material layer is then etched back to remove excess inner spacer material layer on the sidewalls of the gate spacer 128 and the second nanosheet 116, thereby forming the inner spacer 132.

[0032] As shown in Figures 1 and 10, step 28 of method 10 involves epitaxially growing a strained material or a highly doped low-resistivity material from the source / drain recess 130. In some embodiments, the strained material is used to apply stress to the second nanosheet 116 and the fin substrate 111. The strained material described herein can be considered as a source / drain region 140 or a source / drain structure. In this example, the strained material, such as the source / drain region 140, includes a source located on one side of the dummy gate stack 122 and a drain located on the other side of the dummy gate stack 122. The source covers one end of the fin substrate 111, while the drain covers the other end of the fin substrate 111. The source / drain region 140 is adjacent to and electrically connected to the second nanosheet 116, while the inner spacer 132 electrically isolates the source / drain region 140 from the first nanosheet 114. In some embodiments, the source / drain region 140 extends beyond the upper surface of the nanosheet stack 112. However, the embodiments of the present invention are not limited thereto. In other embodiments, the upper surface of the source / drain region 140 is substantially aligned with the upper surface of the nanosheet stack 112. The vertical portion of the gate spacer 128 is sandwiched between the source / drain regions 140, and it can also be regarded as the source / drain sidewall spacer 128SD.

[0033] The source / drain region 140 includes any acceptable material, such as materials suitable for p-type or n-type transistors. For example, the source / drain region 140 may include silicon germanium, silicon germanium boride, germanium, germanium tin, or the like, and is suitable for p-type transistors. In some other embodiments, the source / drain region 140 may include silicon, silicon carbide, silicon carbide phosphide, silicon phosphide, or the like, and is suitable for n-type transistors. In some embodiments, the source / drain region 140 is formed by organic chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, or similar methods. The source / drain region 140 may include one or more semiconductor material layers. For example, the source / drain region 140 may include a bottom semiconductor material layer, an intermediate semiconductor material layer, and a semiconductor material capping layer. Any number of semiconductor material layers may be used as the source / drain region 140. Each of the semiconductor material layers can be composed of different semiconductor materials and can be doped to different dopant concentrations. In an embodiment where the source / drain region 140 includes three semiconductor material layers, a bottom semiconductor material layer can be deposited, an intermediate semiconductor material layer can be deposited on the bottom semiconductor material layer, and a semiconductor material capping layer can be deposited on the intermediate semiconductor material layer.

[0034] In some embodiments, the source / drain region 140 is doped with a conductive dopant. For example, the source / drain region 140 can be epitaxially grown with a p-type dopant such as silicon-germanium or a strained p-type transistor. This is the source / drain region 140 being doped with a p-type dopant to serve as the source and drain of a p-type transistor. The p-type dopant includes boron or boron difluoride, and the source / drain region 140 can be epitaxially grown and in-situ doped using a low-pressure chemical vapor deposition process. As described above, the source / drain region 140 can be a multilayer epitaxially grown with different dopant concentrations, such as a boron-doped silicon-germanium underlayer with a germanium atom percentage of about 45% to 55% and a boron concentration of about 1 x 10²¹ / cm³ to about 2 x 10²¹ / cm³, a boron-doped silicon-germanium intermediate layer with a germanium atom percentage of about 45% to 60% and a boron concentration of about 8 x 10²⁰ / cm³ to about 3 x 10²¹ / cm³, and a boron-doped silicon-germanium capping layer with a germanium atom percentage of about 25% to 45% and a boron concentration of about 1 x 10²⁰ / cm³ to about 8 x 10²⁰ / cm³. In some other embodiments, the source / drain region 140 can be epitaxially grown with silicon carbide, silicon phosphide, combinations thereof, or silicon carbide-phosphide combined with an n-type dopant for straining an n-type transistor. This is the source / drain region 140 doped with n-type dopants to serve as the source and drain of an n-type transistor. The n-type dopants include arsenic and / or phosphorus, and the source / drain region 140 can be epitaxially grown and in-situ doped using a low-pressure chemical vapor deposition process. In some embodiments, the source / drain region 140 can be a multilayer epitaxially grown with different dopant concentrations, such as a phosphorus-doped silicon underlayer with a phosphorus concentration of about 1 x 10²¹ / cm³ to about 2 x 10²¹ / cm³, a phosphorus-doped silicon intermediate layer with a phosphorus concentration of about 1 x 10²¹ / cm³ to about 4 x 10²¹ / cm³, and an arsenic-doped silicon capping layer with an arsenic concentration of about 1 x 10²¹ / cm³ to about 1 x 10²¹ / cm³.

[0035] The epitaxial growth process forming the source / drain region 140 results in a cross-section of the source / drain region 140 that can be diamond-shaped or pentagonal. However, embodiments of the present invention are not limited to this. In other embodiments, the cross-section of the source / drain region 140 can also be hexagonal, columnar, or rod-shaped. In some embodiments shown in FIG10, adjacent source / drain regions 140 remain separated after the epitaxial growth process is completed. Adjacent source / drain regions 140 can be merged instead.

[0036] As shown in Figures 1 and 11, step 30 of method 10 forms an interlayer dielectric layer 144 on the device 100. A contact etch stop layer 142 may also be formed between the source / drain region 140 and the interlayer dielectric layer 144. In some embodiments, the contact etch stop layer 142 compliantly covers the outer sidewall of the source / drain region 140 and the gate spacer 128. The contact etch stop layer 142 may include silicon nitride, silicon oxynitride, silicon nitride having oxygen or carbon elements, and / or other materials, and its formation method may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable methods. The interlayer dielectric layer 144 comprises silicon oxide, silicon nitride, silicon oxynitride, phosphosilicone glass, borosilicate glass, spin-coated glass, fluorosilicone glass, carbon-doped silicon oxide such as silicon hydroxide, silicon carbonitride, silicon carbide, polyimide, and / or combinations thereof. In some other embodiments, the interlayer dielectric layer 144 comprises a dielectric material with a low dielectric constant. In other embodiments, the interlayer dielectric layer 144 comprises one or more dielectric materials and / or one or more dielectric layers. In some embodiments, the interlayer dielectric layer 144 has sufficient thickness, and its formation method may be flowable chemical vapor deposition, chemical vapor deposition, high-density electrostatic chemical vapor deposition, low-pressure chemical vapor deposition, spin coating, sputtering, or other suitable methods. After depositing the interlayer dielectric layer 144, a planarization process planarization apparatus 100 can be used to remove the hard mask layer 126 and expose the dummy gate 124. For example, the planarization process may include a chemical mechanical polishing process.

[0037] As shown in FIG12, in order to protect the interlayer dielectric layer 144 from damage during the subsequent removal step of the dummy gate stack, the interlayer dielectric layer 144 can be selectively recessed to form a top recess, and a capping layer 148 is formed on the top recess. The compositional material of the capping layer 148 may be different from that of the interlayer dielectric layer 144. In some embodiments, the capping layer 148 may include silicon nitride, silicon carbonitride, silicon carbide, or silicon carbonitride oxide. In one embodiment, the capping layer 148 may include silicon nitride. Another planarization process, such as a chemical mechanical polishing process, is performed to remove excess capping layer 148 to expose the dummy gate 124. The planarized capping layer 148, the contact etch stop layer 142, the gate spacer 128, the oxide layer 125, and the upper surface of the dummy gate 124 are substantially coplanar.

[0038] Figure 13 is a partial cross-sectional view of the device 100 after step 30 along section line AA in Figure 12, which is along the length direction of the first nanosheet 114 and the second nanosheet 116. In the embodiment shown in Figure 13, the gate spacer 128 includes a first gate spacer layer 128a and a second gate spacer layer 128b. For example, the first gate spacer layer 128a may be formed on both sidewalls of the dummy gate stack 122, specifically on the oxide layer 125. The second gate spacer layer 128b may be formed on the first gate spacer layer 128a. It should be understood that any number of gate spacer layers may be formed around the dummy gate stack 122, which is still within the scope of the embodiments of the present invention. The first gate spacer layer 128a may be a spacer with a low dielectric constant, and its composition may be a suitable dielectric material such as silicon oxide, silicon oxycarbonate, silicon oxynitride, silicon oxynitride, or the like. The second gate spacer layer 128b may be composed of nitrides such as silicon nitride, silicon oxynitride, silicon carbonitride, similar compounds, or combinations thereof. Any suitable deposition method, such as thermal oxidation, chemical vapor deposition, or similar methods, may be used to form the first gate spacer layer 128a and the second gate spacer layer 128b. In various embodiments, the first gate spacer layer 128a and the second gate spacer layer 128b are composed of different dielectric materials. An oxide layer 125 is stacked between the first gate spacer layer 128a and the dummy gate 124. Since the oxide layer 125 is a native oxide layer, its thickness and density are less than those of the dummy gate dielectric layer 120m.

[0039] As shown in Figure 13, the dummy gate stack 122 may have a high aspect ratio. In the gate replacement process, the dummy gate stack 122 may be removed to form a gate trench. The gate trench continues the high aspect ratio of the dummy gate stack 122, or even develops a bottleneck profile. This gate trench profile may make subsequent steps such as removing the first nanosheet 114 from the gate trench, depositing the interstitial layer into the gate trench, removing the interstitial layer from the gate trench, and depositing the work function metal layer into the gate trench more difficult. As detailed below, the profile of the gate trench is deformed to expand its opening, which may resemble a funnel shape. For clarity, the subsequent steps of deforming the gate trench in method 10 will be illustrated with reference to Figures 14 to 36C, which correspond to a partial cross-sectional view of the device 100 along section AA in Figure 12.

[0040] As shown in Figures 1 and 14, step 32 of method 10 involves etching back the dummy gate 124 to form the gate trench 150. In some embodiments, the etch-back process may be a dry etching process using a fluorine-containing gas such as carbon tetrafluoride, sulfur hexafluoride, or nitrogen trifluoride. In embodiments, the dry etching process may be a plasma etching process using a mixture of nitrogen trifluoride and hydrogen as the etchant. The etchant is selected such that the oxide layer 125 is substantially intact and retained on the sidewall surfaces of the gate spacer 128. In some embodiments, the retained gate height GH1 (measured from the recessed upper surface of the dummy gate 124 to the upper surface 110t of the topmost second nanosheet 116) is approximately 1 nm to approximately 20 nm. As detailed below, the gate height GH1 defines the inflection point of the funnel-shaped profile of the subsequently deformed gate trench 150. The gate height GH1 can be controlled by the etching time of the etch-back process.

[0041] As shown in Figures 1 and 15, step 34 of method 10 involves etching back the oxide layer 125 to expose the upper portion of the sidewall surface of the first gate spacer layer 128a in the gate trench 150. In some embodiments, the etching back process may be a wet etching process using a fluorinated liquid such as a diluted hydrofluoric acid solution. In an embodiment, the ratio of diluted hydrofluoric acid used in the wet etching process may be approximately 1:500. The etchant is selected to make the dummy gate 124 substantially intact. Due to the presence of the dummy gate 124, the upper portion of the oxide layer 125 above the dummy gate 124 is removed.

[0042] As shown in Figures 1 and 16, step 36 of method 10 completely removes the dummy gate 124 using an etch-back process and extends the gate trench 150 to the dummy gate dielectric layer 120m. In some embodiments, the etch-back process may be a wet etching process using an ammonium hydroxide solution or a tetramethylammonium hydroxide solution. An etchant is selected such that the oxide layer 125 is substantially intact with the dummy gate 124. The tip of the oxide layer 125 marks the inflection point TP of the funnel-shaped profile of the subsequently deformed gate trench 150 on the sidewall surface of the first gate spacer layer 128a. The inflection point TP is higher than the upper surface 110t of the topmost second nanosheet 116 to define the gate height GH1. The inflection point TP can also be considered as an adjustment point, as the passivation process in step 38 will adjust the exposed portion of the gate spacer 128 above the gate height GH1.

[0043] As shown in Figures 1 and 17, step 38 of method 10 converts the surface portion of the gate spacer 128 (specifically, the surface portion of the first gate spacer layer 128a in the embodiment) into a passivation layer 152. In some embodiments, the passivation process is an oxidation process, and the passivation layer 152 is an oxide layer formed by oxidizing the surface portion of the first gate spacer layer 128a using any suitable oxidation process (such as an oxygen plasma process, for example, plasma treatment using oxygen and / or ozone as oxidants). After the passivation treatment, the oxygen concentration in the passivation layer 152 is higher than the oxygen concentration in other portions of the gate spacer 128, while the carbon and nitrogen concentrations in the passivation layer 152 are lower than the carbon and nitrogen concentrations in other portions of the gate spacer 128. The oxygen concentrations between the passivation layer 152 and the oxide layer 125 may also differ. In one example, the oxygen concentration in the passivation layer 152 is higher than the oxygen concentration in the oxide layer 125. In another example, the oxygen concentration of the passivation layer 152 is lower than that of the oxide layer 125. In some embodiments, surface portions of the device 100 outside the gate trench 150 (such as the gate spacer 128, the contact etch stop layer 142, and the capping layer 148) may also be converted into passivation layers. In other words, the horizontal portion of the passivation layer 152 extends to the upper surface of the device 100 outside the gate trench 150.

[0044] In one example of the process, the oxygen plasma process uses a mixture of oxidant (such as oxygen and / or ozone) and helium (the ratio of oxidant to helium is between about 10:100 and about 50:100), the RF plasma power is between about 1 kW and about 2 kW, the RF bias power is between about 10 W and about 150 W, the process pressure is between about 10 mTorr and about 30 mTorr, and the thermal environment is between about 250°C and about 450°C. In some embodiments, the passivation environment is controlled such that the concentration of oxidant (such as oxygen and / or ozone) is higher on the upper surface of the device 100, and the concentration of oxidant gradually decreases from the upper surface of the device toward the bottom of the gate trench 150. Thus, the oxidized surface portion of the first gate spacer layer 128a is thicker closer to the upper surface of the device 100. The thickness of the passivation layer 152 gradually decreases downward toward the gate trench 150. In summary, the oxidation process can also be viewed as a gradient oxidation process. Specifically, the retained portion of the oxide layer 125 protects the lower portion of the first gate spacer layer 128a it covers from the passivation process, allowing the passivation layer 152 to extend to the inflection point TP and stop there. The gradient thickness of the passivation layer 152 defines the gate trench profile, with its maximum width at the top, narrowing downwards in the middle, and its width below the inflection point TP being substantially fixed.

[0045] In the embodiment shown in FIG. 17, the maximum thickness D1 of the passivation layer 152 (measured on its upper surface) can be about 0.1 nm to about 10 nm, while the thickness D2 of the first gate spacer layer 128a can be about 0.2 nm to about 15 nm. The difference between thickness D2 and thickness D1 (i.e., D2-D1) can be about 0.1 nm to about 5 nm. The ratio between thickness D1 and thickness D2 (i.e., D1 / D2) can be greater than about 0.1, and can be approximately or even greater than 1. A ratio greater than 1 indicates that the passivation layer extends into the second gate spacer layer 128b. The vertical distance D3 from the inflection point TP to the upper surface of the device 100 can be about 1 nm to about 99 nm, while the vertical distance D4 (D4=D3+GH 1) from the upper surface 110t to the upper surface of the device 100 can be about 5 nm to about 100 nm. The ratio between vertical distances D3 and D4 (i.e., D3 / D4) can be from about 0.1 to about 0.99.

[0046] Method 10 can be modified by removing the dummy gate 124 in step 36 after forming the passivation layer 152 in step 38, as shown in other embodiments of FIG18. After forming the passivation layer 152, the dummy gate 124 is removed by a selective etching process. After performing steps 36 and 38 in any order, step 40 of method 10 is performed.

[0047] As shown in Figures 1 and 19, step 40 of method 10 performs an isotropic passivation process on the gate spacer 128, causing the thickness of the oxide layer (including the passivation layer 152 and the oxide layer 125) formed on the gate trench 150 to grow. In some embodiments, the isotropic passivation process is an anodic oxidation process, which uses oxygen free radicals in the process chamber instead of plasma. The isotropic passivation process can grow an oxide layer of uniform thickness. In Figure 19, the dashed line 154 indicates the additional exterior of the gate spacer 128 that is converted into an oxide layer (specifically, a portion of the first gate spacer layer 128a). Since the additional converted portion has a substantially uniform thickness, the width of the gate trench 150 can be substantially uniformly expanded from top to bottom when the oxide layer is removed, but the shape of the passivation layer 152 still defines the width difference of the funnel-shaped profile of the gate trench 150.

[0048] In one example of the process, the anodizing treatment uses an oxidant (such as oxygen free radicals and / or oxygen), nitrogen, a mixture of nitrogen and hydrogen, and diimine as the carrier gas. The process pressure is between about 3 mTorr and about 3000 mTorr, the thermal environment is between about 100°C and about 500°C, and the time is between about 10 seconds and about 1000 seconds. It is worth noting that the isotropic passivation process is adjusted in this way so that its strength is insufficient to penetrate the harder and thicker dummy gate dielectric layer, so that the thickness of the dummy gate dielectric layer 120m at step 40 remains substantially unchanged. After the anodizing treatment, the oxygen concentration in the additional conversion portion is higher than the oxygen concentration in the other untreated portions of the gate spacer 128, and the carbon and nitrogen concentrations in the additional conversion portion are lower than the carbon and nitrogen concentrations in the other untreated portions of the gate spacer 128. The oxygen concentration between the additional conversion portion and the oxide layer 125 may also be different. In one example, the oxygen concentration in the additional conversion portion is higher than the oxygen concentration in the oxide layer 125. In another example, the oxygen concentration in the additional conversion section is lower than the oxygen concentration in oxide layer 125. The structure of the device 100 resulting after step 40 is shown in Figure 20. After the anodizing treatment, the oxide layer 125 and the passivation layer 152 are thickened to the same degree, but the thickness of the dummy gate dielectric layer 120m remains substantially unchanged. The thickened passivation layer 152 and the thickened oxide layer 125 can be considered together as an oxide layer.

[0049] As shown in Figures 1 and 21, step 42 of method 10 removes the oxide layer (including the passivation layer 152 and the oxide layer 125) from the sidewall of the gate trench 150 during the trimming process to expose the first gate spacer layer 128a in the gate trench 150. In some embodiments, the trimming process may be a wet etching process, which may use a liquid containing hydrofluoric acid, such as a diluted solution of hydrofluoric acid. In an embodiment, the wet etching process may use diluted hydrofluoric acid at a ratio of 1:500. An etchant is selected to retain a large amount of the dummy gate dielectric layer 120m. Even if the dummy gate dielectric layer 120m is etched away, the etching rate of the dummy gate dielectric layer 120m is still less than the etching rate of the passivation layer 152 and the oxide layer 125 due to the relatively high density of the dummy gate dielectric layer 120m. The final gate trench 150 has an extended width and a funnel-shaped profile, specifically a substantially uniform width between substantially vertical sidewalls below the inflection point TP, and a gradually expanding width between tapered sidewalls above the inflection point TP.

[0050] After removing the passivation layer 152 and oxide layer 125, method 10 may repeat steps 40 and 42 (as in a cycle process) multiple times to passivate and remove the exterior of the gate spacer 128, thereby further expanding the gate trench 150 uniformly from top to bottom. The cycle process may be repeated once, twice, three times, or more times until the gate trench 150 expands to a suitable width. During the cycle process, a dummy gate dielectric layer 120m is retained as a process stop layer to protect the underlying second nanosheet 116. As shown in Figures 22 and 23, after one cycle process, additional surface portions of the gate spacer 128 along all sidewalls of the gate trench 150 may be oxidized, and then the oxidized portions are removed. Through the cycle process, the opening of the gate trench 150 can be uniformly expanded from top to bottom. The width difference between the top and bottom of the gate trench 150 remains the same, and the width difference is defined by the passivation layer 152 as described above. It is worth noting that, depending on the number of times the cycle process is repeated, the extended tapered sidewalls of the gate trench 150 can be cut into the second gate spacer layer 128b or even the contact etch stop layer 142, as described below.

[0051] As shown in Figures 1 and 24, step 44 of method 10 removes the dummy gate dielectric layer 120m to expose the upper surface 110t (and sidewall surface) of the fin 110. For example, dry etching or wet etching can be performed to remove the dummy gate dielectric layer 120m. In some embodiments, dry etching may use a mixture of ammonia and hydrofluoric acid as the etchant. In some embodiments, wet etching may use a fluorinated liquid such as diluted hydrofluoric acid. The etchant is selected such that the first nanosheet 114 and the second nanosheet 116 in the fin 110 are substantially intact. During the removal of the dummy gate dielectric layer 120m, the capping layer 148 protects the interlayer dielectric layer 144 and the underlying source / drain region 140. In the embodiment shown in Figure 24, the top of the gate trench 150 has a gradually widening width, with its maximum width D5 measured at the top opening of the gate trench 150; the middle portion of the gate trench 150 has a substantially fixed width D6, measured at the height of the inflection point TP; and the bottom of the gate trench 150 has a bottom width D7, measured at the upper surface 110t of the fin 110. In some embodiments, the fixed width D6 can be from about 5 nm to about 200 nm, while the maximum width D5 can be about 0.1 nm to about 10 nm larger than the fixed width D6. In some embodiments, the ratio between width D5 and width D6 (i.e., D5 / D6) can be from about 1.01 to about 3. The bottom width D7 can be greater than or less than the fixed width D6, depending on how much the gate trench 150 expands during the cycle of steps 40 and 42. That is, in the embodiment shown, the bottom width D7 is slightly larger than the fixed width D6. However, if the gate trench 150 expands beyond the width of the dummy gate dielectric layer 120m due to the cycle process, the bottom width D7 can be smaller than the fixed width D6. The ratio between width D7 and width D6 (i.e., D7 / D6) can be from about 0.5 to about 5.

[0052] As shown in Figures 1 and 25, step 46 of method 10 involves an etching process to remove the first nanosheet 114. In this example, the first nanosheet 114 is completely removed to form a plurality of gaps 158 between the second nanosheets 116. Thus, the second nanosheets 116 are spaced apart by gaps 158. Furthermore, the bottommost second nanosheet 116 may be spaced apart from the fin substrate 111 by gaps 158. In this way, the second nanosheets 116 are suspended. In some embodiments, the height of the gaps 158 may be from about 5 nm to about 20 nm. In this embodiment, the second nanosheets 116 comprise silicon, and the first nanosheet 114 comprises silicon germanium. A method for selectively removing the first nanosheet 114 may be to oxidize the first nanosheet 114 using a suitable oxidant such as ozone. The oxidized first nanosheet 114 can then be selectively removed from the gate trench 150. In some embodiments, the etching process includes a dry etching process to selectively remove the first nanosheet 114, such as by applying hydrogen chloride gas at a temperature of about 20°C to about 300°C, or by applying a mixture of carbon tetrafluoride, sulfur hexafluoride, and fluoroform. The two ends of the suspended second nanosheet 116 are dry-connected to the source / drain region 140. The suspended second nanosheet 116 can be considered as a channel assembly. The etching process can be considered as a channel assembly release process. The upper surface of the fin 110 can be considered as the top surface 110t of the channel, which is the uppermost channel assembly such as the upper surface of the second nanosheet 116.

[0053] As shown in Figures 1 and 26, step 48 of method 10 forms a gate dielectric layer 162 and a gate 164 in the gate trench 150 and the gap 158. The gate 164 and the gate dielectric layer 162 constitute a gate stack 160. The gate stack 160 can be considered as a metal gate stack due to its metallic composition. The deformed gate trench 150 has a funnel-shaped profile, which can provide a larger opening and facilitate the deposition of various layers of the gate stack 160 into the gate trench 150. In some embodiments, the gate dielectric layer 162 includes an interface layer 162a formed on the surface of a channel assembly such as a second nanosheet 116 and the upper surface of a fin substrate 111, and a high dielectric constant dielectric layer 162b covering the interface layer 162a and the channel assembly such as the second nanosheet 116 below it. A high-dielectric-constant dielectric layer 162b may also be located on the sidewall surfaces of the gate spacer 128 in the gate trench 150. The interface layer 162a is very thin and may be composed of silicon dioxide, SiOx (0 < x < 2), or a combination thereof. In some embodiments, the interface layer 162a is formed by applying an oxidant to the surface of a channel assembly such as the second nanosheet 116. For example, a liquid containing hydrogen peroxide may be applied or provided to the surface of the channel assembly such as the second nanosheet 116 to form the interface layer 162a. The high-dielectric-constant dielectric layer 162b may comprise a high-dielectric-constant dielectric material. Examples of high-dielectric-constant dielectric materials include hafnium oxide, hafnium silicon oxide, hafnium oxysilicon, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, lanthanum oxide, aluminum oxide, titanium oxide, hafnium oxide-aluminum oxide alloys, other suitable high-dielectric-constant dielectric materials, and / or combinations thereof. The high-dielectric-constant dielectric layer 162b can be formed by chemical vapor deposition, atomic layer deposition, or any suitable method. In one embodiment, the high-dielectric-constant dielectric layer 162b is formed using a highly compliant deposition process such as atomic layer deposition to ensure that the high-dielectric-constant dielectric layer has a uniform thickness around the channel assembly, such as the second nanosheet 116. In some embodiments, the thickness of the high-dielectric-constant dielectric layer 162b can be from about 0.5 nm to about 3 nm.

[0054] The gate layer 164 may include a variety of conductive materials such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicate, cobalt silicate, titanium nitride, tungsten nitride, titanium aluminum, titanium aluminum nitride, tantalum carbonitride, tantalum carbide, tantalum silicon nitride, metal alloys, other suitable materials, and / or combinations thereof. The gate layer 164 may include one or more layers of conductive materials, such as a work function layer and a metal filler layer (not shown). The metal filler layer, as a conductive filler layer, may completely fill the remaining space of the gate trench 150.

[0055] The work function layer can be used to provide the work function required by the transistor to improve device performance, such as improving the threshold voltage. In some embodiments, the work function layer is used to form a p-type metal-oxide-semiconductor device. The work function layer is a p-type work function layer. The p-type work function layer can provide a work function suitable for the device, such as greater than or equal to about 4.8 eV. The p-type work function layer may include a metal, a metal carbide, a metal nitride, other suitable materials, or a combination thereof. For example, p-type metals include tantalum nitride, tungsten nitride, titanium, titanium nitride, one or more other suitable materials, or a combination thereof. In some other embodiments, the work function layer is used to form an n-type metal-oxide-semiconductor device. The work function layer is an n-type work function layer. The n-type work function layer can provide a work function value suitable for the device, such as less than or equal to about 4.5 eV. The n-type work function layer may include a metal, a metal carbide, a metal nitride, or a combination thereof. For example, the n-type work function layer includes titanium nitride, tantalum, tantalum nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the n-type work function layer is an aluminum-containing layer. The aluminum-containing layer may be composed of or include aluminum titanium carbide, aluminum titanium oxide, aluminum titanium nitride, one or more other suitable materials, or combinations thereof. The work function layer may also be composed of or include hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (such as hafnium carbide, zirconium carbide, titanium carbide, or aluminum carbide), aluminides, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or combinations thereof. The thickness and / or combination of the work function layer can be finely adjusted to adjust the work function level. The work function layer can be deposited on the gate dielectric layer 162 using atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, one or more other feasible processes, or combinations thereof.

[0056] In some embodiments, a barrier layer (not shown) is formed before the formation of the work function layer to create an interface between the gate dielectric layer 162 and the subsequently formed work function layer. The barrier layer can also be used to prevent diffusion between the gate dielectric layer 162 and the subsequently formed work function layer. The barrier layer may be composed of or include a metal-containing material. The metal-containing material may include titanium nitride, tantalum nitride, one or more other suitable materials, or a combination thereof. The barrier layer may be deposited using atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, one or more other feasible processes, or a combination thereof.

[0057] In some embodiments, the metal filler layer may be composed of or include a metallic material. The metallic material may include tungsten, ruthenium, aluminum, copper, cobalt, titanium, titanium nitride, titanium aluminum, titanium aluminum carbide, one or more other suitable materials, or combinations thereof. The metal filler layer may be deposited on the work function layer, and the deposition method may employ chemical vapor deposition, atomic layer deposition, physical vapor deposition, electroplating, electroless plating, spin coating, one or more other feasible processes, or combinations thereof. In some embodiments, the metal filler layer does not extend into the gap 158 because the gap 158 is small and is filled with other structures such as the gate dielectric layer 162 and the work function layer. In some embodiments, the lower surface of the metal filler layer may be higher than the upper surface 110t of the channel. However, the embodiments of the present invention are not limited thereto. In some other embodiments, a portion of the metal filler layer may extend into the large gap 158.

[0058] As shown in Figures 1 and 27A to 27C, step 50 of method 10 performs a planarization process, such as a chemical mechanical polishing process, until the interlayer dielectric layer 144 is exposed. The planarization process also causes the gate stack 160 to be recessed. The three embodiments shown in Figures 27A to 27C are the final device 100 after step 50. One difference is the recessed gate height of the gate stack 160 after the planarization process (labeled as heights GHa, GHb, and GHc, respectively). The corresponding positions of the three gate heights GHa, GHb, and GHc can also be marked as the dashed lines in Figure 26 for clarity. In Figure 27A, the recessed upper surface of the gate stack 160 is below the inflection point TP (GHa < GH 1), so the top with tapered sidewalls can be removed and the middle portion with a uniform thickness can be retained. The vertical portion of the first gate spacer layer 128a also has a substantially uniform thickness. In Figure 27B, the recessed upper surface of the gate stack 160 is above the inflection point TP (GHb > GH 1), thus partially preserving the top with tapered sidewalls. The lower portion of the vertical portion of the first gate spacer layer 128a has a uniform thickness, while the thickness of the upper portion gradually decreases. In Figure 27C, the recessed upper surface of the gate stack 160 is above the inflection point TP (GHc > GH 1) to substantially preserve the top with tapered sidewalls. The lower portion of the vertical portion of the first gate spacer layer 128a has a uniform thickness, while the thickness of the upper portion gradually decreases.

[0059] Figures 28, 29, and 30A to 30C show other embodiments. In Figure 28, the gate trench is deformed in such a way that the opening is expanded, so that the funnel-shaped conical sidewalls can cut through the top of the first gate spacer layer 128a and into the second gate spacer layer 128b. In Figure 29, after the gate stack 160 is formed in the gate trench 150, the high-dielectric-constant dielectric layer 162b contacts the first gate spacer layer 128a and the second gate spacer layer 128b. In Figure 30, the recessed upper surface of the gate stack 160 is below the inflection point TP (GHa < GH 1), so the top with the conical sidewalls is removed, leaving the middle portion with a uniform width. The vertical portion of the first gate spacer layer 128a also has a substantially uniform thickness. In Figure 30B, the recessed upper surface of the gate stack 160 is above the inflection point TP (GHb > GH 1) to partially retain the top with tapered sidewalls. The lower portion of the vertical portion of the first gate spacer layer 128a has a uniform thickness, while the upper portion has a gradually decreasing thickness. In Figure 30C, the recessed upper surface of the gate stack 160 is above the inflection point TP (GHc > GH 1) to substantially retain the top with tapered sidewalls. The lower portion of the vertical portion of the first gate spacer layer 128a has a uniform thickness, while the upper portion has a gradually decreasing thickness. The lower portion of the vertical portion of the second gate spacer layer 128b has a uniform thickness, while the upper portion has a gradually decreasing thickness. A high-dielectric-constant dielectric layer 162b contacts the first gate spacer layer 128a and the second gate spacer layer 128b.

[0060] Figures 31, 32, and 33A to 33C show another embodiment. In Figure 31, the gate trench is deformed to expand the opening, while the funnel-shaped tapered sidewalls cut through the tops of the first gate spacer layer 128a and the second gate spacer layer 128b, and further into the contact etch stop layer 142. In Figure 32, after the gate stack 160 is formed in the gate trench 150, the high-dielectric-constant dielectric layer 162b contacts the first gate spacer layer 128a, the second gate spacer layer 128b, and the contact etch stop layer 142. In Figure 33A, the recessed upper surface of the gate stack 160 is below the inflection point TP (GHa < GH 1), thus removing the top with tapered sidewalls and retaining the middle portion with a consistent width. The vertical portion of the first gate spacer layer 128a also has a substantially consistent thickness. In Figure 33B, the recessed upper surface of the gate stack 160 is above the inflection point TP (GHb > GH 1), thus partially retaining the top with tapered sidewalls. The lower portion of the vertical portion of the first gate spacer layer 128a has a uniform thickness, while the upper portion has a gradually decreasing thickness. The lower portion of the vertical portion of the second gate spacer layer 128b has a uniform thickness, while the upper portion has a gradually decreasing thickness. A high-dielectric-constant dielectric layer 162b contacts the first gate spacer layer 128a and the second gate spacer layer 128b. In Figure 33C, the recessed upper surface of the gate stack 160 is above the inflection point TP (GHc > GH 1) to substantially retain the top with tapered sidewalls. The lower portion of the vertical portion of the first gate spacer layer 128a has a uniform thickness, while the upper portion has a gradually decreasing thickness. The lower portion of the vertical portion of the second gate spacer layer 128b has a uniform thickness, while the upper portion has a gradually decreasing thickness. The top of the second gate spacer layer 128b is higher than the top of the first gate spacer layer 128a. The lower portion of the vertical portion of the contact etch stop layer 142 has a uniform thickness, while the upper portion has a gradually decreasing thickness. A high-dielectric-constant dielectric layer 162b contacts the first gate spacer layer 128a, the second gate spacer layer 128b, and the contact etch stop layer 142.

[0061] Figures 34, 35, and 36A to 36C show another embodiment. In Figure 34, the gate trench deformation can be achieved by completely etching back the oxide layer 125 to set the inflection point TP on the upper surface of the dummy gate dielectric layer 120m, so that the tapered sidewall of the gate trench 150 starts from or approaches the upper surface of the dummy gate dielectric layer 120m. In Figure 35, after the gate stack 160 is formed in the gate trench 150, the high dielectric constant dielectric layer 162b contacts the first gate spacer layer 128a. In Figure 36A, the recessed upper surface of the gate stack 160 is higher than the inflection point TP (GHa > GH 1), the tapered sidewall is retained due to the decrease in the inflection point TP, and there is no longer a uniformly wide middle portion because the tapered sidewall starts from the upper surface of the dummy gate dielectric layer 120m. The vertical portion of the first gate spacer layer 128a has a gradually decreasing thickness. In Figure 36B, the recessed upper surface of the gate stack 160 is above the inflection point TP (GHb > GH 1). The tapered sidewalls extend from the inflection point TP. The vertical portion of the first gate spacer layer 128a has a gradually decreasing thickness. In Figure 36C, the recessed upper surface of the gate stack 160 is above the inflection point TP (GHc > GH 1). The tapered sidewalls extend from the inflection point TP. The vertical portion of the first gate spacer layer 128a has a gradually decreasing thickness. Although the top opening of the gate trench 150 shown in Figures 30A to 30C remains within the boundary of the first gate spacer layer 128a, the variations shown in Figures 30C, 33B, and 33C can also be used in the embodiments of Figures 36A to 36C, wherein the second gate spacer layer 128b and / or the contact etch stop layer 142 can also contact the high dielectric constant dielectric layer 162b.

[0062] One or more embodiments of the present invention provide numerous advantages to semiconductor devices and methods of forming thereof, but are not limited thereto. For example, embodiments of the present invention provide a gradient passivation and etching process to enlarge the gate trench. Enlarged gate trenches facilitate subsequent deposition and / or removal of material layers without leaving residues and / or trapping gaps in the gate trench, which may increase device performance after gate replacement processes. Furthermore, the predetermined steps for forming the metal gate can be easily integrated into existing semiconductor fabrication processes.

[0063] An exemplary embodiment of the present invention relates to a method for manufacturing a semiconductor device. The method includes: interleaving and stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers on a substrate; patterning the first semiconductor layers and second semiconductor layers into fins; forming a dummy gate stack over the fins, the dummy gate stack including a dummy gate dielectric layer and a gate located on the dummy gate dielectric layer; forming a gate sidewall oxide layer on the sidewalls of the dummy gate stack; depositing a plurality of gate spacers on the gate sidewall oxide layer; recessing the dummy gates and the gate sidewall oxide layer to form a gate trench exposing the gate spacers; passivating the tops of the gate spacers, with the passivated tops of the gate spacers decreasing in width from top to bottom; removing the passivated tops of the gate spacers and the gate sidewall oxide layer from the gate trench; removing the dummy gate dielectric layer from the gate trench; removing the first semiconductor layer from the gate trench to release the second semiconductor layer as a plurality of channel components; and depositing a metal gate stack in the gate trench to cover each of the second semiconductor layers. In some embodiments, the step of passivating the top of the gate spacer includes an oxidation process, and the passivated top of the gate spacer is an oxide. In some embodiments, the oxidation process is an oxygen plasma process. In some embodiments, the method further includes oxidizing the layered structure of the gate spacer beneath the passivated top and gate sidewall oxide layers of the gate spacer before removing the passivated top and gate sidewall oxide layers of the gate spacer. In some embodiments, the oxidized layered structure beneath the passivated top and gate sidewall oxide layers of the gate spacer has a substantially uniform width. In some embodiments, the step of removing the passivated top and gate sidewall oxide layers of the gate spacer includes removing the oxidized layered structure. In some embodiments, the method further includes oxidizing a surface layer of the gate spacer after removing the passivated top and gate sidewall oxide layers of the gate spacer; and removing the oxidized surface layer to widen the gate trench. In some embodiments, a dummy gate is completely removed before passivating the top of the gate spacer. In some embodiments, the method further includes completely removing the dummy gate after passivating the top of the gate spacers. In some embodiments, the method further includes laterally recessing the end portion of the first semiconductor layer; forming a plurality of inner spacers on the end portion of the first semiconductor layer; and forming an epitaxial structure adjacent to the end portion of the second semiconductor layer. The inner spacers are sandwiched between the epitaxial structure and the first semiconductor layer.

[0064] Another exemplary embodiment of the present invention relates to a method for manufacturing a semiconductor device. The method includes forming a fin protruding from a substrate; forming a dummy gate stack extending over the fin, the dummy gate stack including a dummy gate dielectric layer, dummy gates located on the dummy gate dielectric layer, and an oxide layer located on the sidewalls of the dummy gates; forming a plurality of gate spacers on the sidewalls of the dummy gate stack; removing the dummy gates; recessing the oxide layer to a first position, the first position being perpendicularly spaced from the upper surface of the fin by a first height; passivating surface portions of the gate spacers to form a passivation layer higher than the oxide layer, the top of the passivation layer being wider than the bottom of the passivation layer; removing the passivation layer, the oxide layer, and the dummy gate dielectric layer to form a gate trench; depositing a metal gate stack in the gate trench; and recessing the metal gate stack to a second position, the second position being perpendicularly spaced from the upper surface of the fin by a second height. In some embodiments, the gate trench has a maximum width at its opening and a substantially fixed width in the middle portion of the gate trench. In some embodiments, the second height is less than the first height. In some embodiments, the second height is greater than the first height. In some embodiments, the gate spacer includes a first gate spacer layer and a second gate spacer layer, wherein the first gate spacer layer covers the second gate spacer layer such that the second gate spacer layer does not contact the metal gate stack. In some embodiments, the gate spacer includes a first gate spacer layer and a second gate spacer layer, wherein both the first gate spacer layer and the second gate spacer layer contact the metal gate stack. In some embodiments, the method further includes extending the thickness of the passivation layer and the oxide layer into the gate spacer.

[0065] Another exemplary embodiment of the present invention relates to a semiconductor device. The semiconductor device includes a plurality of channel components vertically suspended on a substrate; a gate stack covering each of the channel components; an epitaxial structure adjacent to the channel components; and a plurality of gate spacers located on the sidewalls of the gate stack. The width of the top of the gate stack decreases in the downward direction, while the width of the middle portion of the gate stack is fixed. In some embodiments, the bottom width of the bottom of the gate stack is greater than the fixed width of the middle portion of the gate stack. In some embodiments, the gate spacers include a first gate spacer layer and a second gate spacer layer, and the gate stack contacts the first gate spacer layer and the second gate spacer layer.

[0066] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention. [Simplified Explanation of the Diagram]

[0007] Figure 1 is a flowchart of a method for forming a semiconductor device according to various embodiments of the present invention. Figures 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and 12 are perspective views of the semiconductor structure during the fabrication stage of the method in Figure 1 according to various embodiments of the present invention. Figures 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27A, 27B, 27C, 28, 29, 30A, 30B, 30C, 31, 32, 33A, 33B, 33C, 34, 35, 36A, 36B, and 36C are cross-sectional views of the semiconductor structure during the fabrication stage of the method in Figure 1 according to various embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: Multiple first semiconductor layers and multiple second semiconductor layers are staggered and stacked on a substrate; the first semiconductor layers and the second semiconductor layers are patterned into a fin; a dummy gate stack is formed over the fin, the dummy gate stack including a dummy gate dielectric layer and a dummy gate located on the dummy gate dielectric layer; a gate sidewall oxide layer is formed on the sidewall of the dummy gate stack; multiple gate spacers are deposited on the gate sidewall oxide layer; the dummy gate and the gate sidewall oxide layer are recessed to form a gate trench exposing the gate spacers; the tops of the gate spacers are passivated, and the width of the passivated tops of the gate spacers decreases from top to bottom; the passivated tops of the gate spacers and the gate sidewall oxide layer are removed from the gate trench; the dummy gate dielectric layer is removed from the gate trench. The removal of the first semiconductor layers from the gate trench to release the second semiconductor layers as a plurality of channel components; and the deposition of a metal gate stack in the gate trench to cover each of the second semiconductor layers.

2. A method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of passivating the tops of the gate spacers includes an oxide process, and the passivated tops of the gate spacers are oxides.

3. A method for manufacturing a semiconductor device as described in claim 2, wherein the oxidation process is an oxygen plasma process.

4. The method for manufacturing a semiconductor device as described in claim 1 further includes: Before removing the passivation tops and the oxide layer of the gate spacers, oxidize a layer of the gate spacers beneath the passivation tops and the oxide layer of the gate sidewalls.

5. A method for manufacturing a semiconductor device, comprising: A fin-like structure protrudes from a substrate; A dummy gate stack is formed to extend beyond the fin, the dummy gate stack including a dummy gate dielectric layer, a dummy gate on the dummy gate dielectric layer, and an oxide layer on the sidewall of the dummy gate; a plurality of gate spacers are formed on the sidewall of the dummy gate stack; the dummy gate is removed; the oxide layer is recessed to a first position, the first position being perpendicularly separated from the upper surface of the fin by a first height; the surface portions of the gate spacers are passivated to form a passivation layer higher than the oxide layer, the top of the passivation layer being wider than the bottom of the passivation layer; the passivation layer, the oxide layer, and the dummy gate dielectric layer are removed to form a gate trench; a metal gate stack is deposited in the gate trench; and the metal gate stack is recessed to a second position, the second position being perpendicularly separated from the upper surface of the fin by a second height.

6. A method of manufacturing a semiconductor device as claimed in claim 5, wherein the gate trench has the largest width at the opening of the gate trench and the width of the middle portion of the gate trench is substantially fixed.

7. A method of manufacturing a semiconductor device as described in claim 5 or 6, wherein the second height is smaller than the first height.

8. A semiconductor device, comprising: Multiple channel components are vertically suspended on a substrate; A gate stack covering each of the channel components; an epitaxial structure adjacent to the channel components; and a plurality of gate spacers located on the sidewalls of the gate stack; wherein the top of the gate stack has a decreasing width in the downward direction, while the middle portion of the gate stack has a fixed width, and wherein the bottom of the gate stack has sloping sidewalls.

9. The semiconductor device as claimed in claim 8, wherein the bottom width of the bottom of the gate stack is greater than the fixed width of the middle portion of the gate stack.

10. The semiconductor device as claimed in claim 8 or 9, wherein the gate spacers include a first gate spacer layer and a second gate spacer layer, and wherein the gate stack contacts the first gate spacer layer and the second gate spacer layer.

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