Integrated chip and method of forming the same

Abstract

An integrated wafer and a method for forming the same are provided. The integrated wafer includes a first source / drain region and a second source / drain region along a semiconductor substrate. A channel region extends along the substrate from the first source / drain region to the second source / drain region. A gate electrode is located between the first and second source / drain regions. The gate electrode has first and second outer walls and a bottom surface extending from the first outer wall to the second outer wall. A gate dielectric layer is located between the gate electrode and the channel region. A lateral portion of the gate dielectric layer extends laterally along the bottom surface of the gate electrode. First and second vertical portions of the gate dielectric layer extend upward from the lateral portion along the first and second outer walls of the gate electrode.

Description

Prior Technology

[0001] Modern integrated chips (ICs) comprise millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). ICs can use many different types of semiconductor devices depending on the application. For example, many ICs include low-voltage transistor devices, medium-voltage transistor devices, and / or high-voltage transistor devices. Simple Explanation of the Diagram

[0002] The best understanding of all aspects of this disclosure can be obtained from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity. Figure 1 shows a cross-sectional view of some embodiments of an integrated wafer including transistors along a semiconductor substrate. Figure 2 shows a top view of some embodiments of the integrated wafer of Figure 1. Figures 3 and 4 show cross-sectional views of some embodiments of the integrated wafer of Figure 2. Figure 5 shows a top view of some other embodiments of the integrated wafer of Figure 1. Figure 6 shows a cross-sectional view of some embodiments of the integrated wafer of Figure 5. Figure 7 shows a cross-sectional view of some embodiments of the integrated wafer of Figure 1, wherein multiple well regions are in the semiconductor substrate. Figures 8 and 9 show top views of some embodiments of the integrated wafer of Figure 7. Figures 10 and 11 show cross-sectional views of some embodiments of the integrated wafer of Figure 7, wherein the gate electrode of the transistor includes multiple metal layers. Figure 12 shows a top view of some embodiments of the integrated wafers of Figures 10 and 11. Figures 13 and 14 show cross-sectional views of some embodiments of the integrated wafer of Figure 10, wherein the gate electrode includes multiple base metal layers and multiple work function metal layers. Figures 15-17 show top views of some embodiments of the integrated wafers of Figures 13 and 14. Figure 18 shows cross-sectional views of some embodiments of the integrated wafers of Figures 16 and 17. Figures 19-21 show top views of some other embodiments of the gate electrode and gate dielectric layer of a transistor. Figures 22-25 show cross-sectional views of some other embodiments of the integrated wafer of Figure 18. Figures 26-37 show cross-sectional views of some embodiments of a method for forming an integrated wafer comprising transistors along a semiconductor substrate. Figure 38 shows flowcharts of some embodiments of a method for forming an integrated wafer comprising transistors along a semiconductor substrate. Implementation

[0003] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0004] Additionally, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0005] An integrated wafer includes a transistor along a semiconductor substrate. The transistor includes a pair of source / drain regions along the semiconductor substrate. A channel region extends along the semiconductor substrate between the source / drain regions. A gate electrode is located above the channel region and between the source / drain regions. A gate dielectric layer is located between the gate electrode and the channel region.

[0006] In some cases, reducing the thickness of the gate dielectric layer can improve transistor performance, reduce the short-channel effect (SCE), and reduce transistor mismatch on the integrated wafer (e.g., reducing performance variations between similar transistors on the integrated wafer). However, in other cases, reducing the thickness of the gate dielectric layer can decrease its reliability. For example, reducing the thickness of the gate dielectric layer can reduce its integrity (e.g., making the gate dielectric layer more susceptible to breakdown).

[0007] Conversely, in some cases, increasing the thickness of the gate dielectric layer can improve its reliability. However, in other cases, increasing the thickness of the gate dielectric layer can reduce transistor efficiency, increase SCE (Strain Coefficient), and increase transistor mismatch.

[0008] In the various embodiments disclosed herein, the gate dielectric layer has a reduced thickness at the center of the channel region and an increased thickness at opposite ends of the channel region to improve the balance between transistor performance and reliability. For example, a lateral portion of the gate dielectric layer extends laterally along the bottom surface of the gate electrode. The lateral portion has a reduced thickness to improve transistor performance. Furthermore, a first vertical portion of the gate dielectric layer extends upward from the lateral portion along the first outer sidewall of the gate electrode, and a second vertical portion of the gate dielectric layer extends upward from the lateral portion along the second outer sidewall of the gate electrode. The vertical portion has an increased thickness to improve transistor reliability. By reducing the thickness of the gate dielectric layer directly below the gate electrode and increasing the thickness of the gate dielectric layer along the sidewall of the gate electrode, the balance between transistor performance and reliability can be improved, and transistor mismatch can be reduced.

[0009] Figure 1 shows a cross-sectional view 100 of some embodiments of an integrated wafer including a transistor 101 along a semiconductor substrate 102. Figure 1 is shown in the xz plane formed by axes 101x and 101z.

[0010] Transistor 101 includes a first source / drain region 104 and a second source / drain region 106 arranged along semiconductor substrate 102. Channel region 108 extends along semiconductor substrate 102 from the first source / drain region 104 to the second source / drain region 106. The source / drain regions may refer individually or collectively to the source or drain depending on the context.

[0011] Transistor 101 includes a gate electrode 110 located above channel region 108 and between first source / drain region 104 and second source / drain region 106. Gate electrode 110 has a first outer sidewall 110a, a second outer sidewall 110b, a bottom surface 110c extending from the bottom of the first outer sidewall 110a to the bottom of the second outer sidewall 110b, and a top surface 110d extending from the top of the first outer sidewall 110a to the top of the second outer sidewall 110b.

[0012] Transistor 101 includes a gate dielectric layer 112 located between gate electrode 110 and channel region 108. A lateral portion 114 of the gate dielectric layer 112 extends laterally along the bottom surface 110c of gate electrode 110. A first vertical portion 116 of the gate dielectric layer 112 extends upward from the lateral portion 114 along the first outer sidewall 110a of gate electrode 110. A second vertical portion 118 of the gate dielectric layer 112 extends upward from the lateral portion 114 along the second outer sidewall 110b of gate electrode 110.

[0013] The lateral portion 114 is defined by the first upper surface 112a, bottom surface 112b, first outer sidewall 112c, and second outer sidewall 112d of the gate dielectric layer 112. The first vertical portion 116 is defined by the second upper surface 112e, bottom surface 112b, first outer sidewall 112c, and first inner sidewall 112f of the gate dielectric layer 112. The second vertical portion 118 is defined by the third upper surface 112g, bottom surface 112b, second outer sidewall 112d, and second inner sidewall 112h of the gate dielectric layer 112.

[0014] The transverse portion 114 has a first thickness 120 (e.g., the distance between the upper surface 112a and the bottom surface 112b measured along the axis 101z). The first vertical portion 116 has a second thickness 122 (e.g., the distance between the upper surface 112e and the bottom surface 112b measured along the axis 101z). The second vertical portion 118 has a third thickness 124 (e.g., the distance between the upper surface 112g and the bottom surface 112b measured along the axis 101z). The second thickness 122 and the third thickness 124 are greater than the first thickness 120.

[0015] By reducing the thickness 120 of the gate dielectric layer 112 along the lateral portion 114 (e.g., directly below the center of the gate electrode 110), the performance of the transistor 101 can be improved and the short-channel effect (SCE) reduced. Furthermore, by increasing the thickness 122, 124 of the gate dielectric layer 112 along the vertical portions 116, 118 (e.g., along the edge of the gate electrode 110), the reliability of the transistor 101 can be improved (e.g., the integrity of the gate dielectric layer 112 can be improved). By improving the performance and reliability of the transistor 101, mismatches between the transistor 101 and other similar transistors (not shown) on the integrated wafer can be reduced.

[0016] In some embodiments, the thickness 120 ranges from 50 angstroms to 300 angstroms, 100 angstroms to 250 angstroms, or other suitable ranges. In some embodiments, the thicknesses 122 and 124 range from 70 angstroms to 400 angstroms, 150 angstroms to 350 angstroms, or other suitable ranges.

[0017] The first lightly doped source / drain region 126 is located below the first source / drain region 104 in the semiconductor substrate 102, and the second lightly doped source / drain region 128 is located below the second source / drain region 106 in the semiconductor substrate 102. In some embodiments, the first lightly doped source / drain region 126 and the second lightly doped source / drain region 128 extend below the gate dielectric layer 112 and below the gate electrode 110.

[0018] A shallow trench isolation (STI) structure 130 surrounds a portion of the semiconductor substrate 102, including a first source / drain region 104, a second source / drain region 106, a channel region 108, a first lightly doped source / drain region 126, and a second lightly doped source / drain region 128. In some embodiments, the STI structure 130 defines an active device region of the semiconductor substrate 102.

[0019] The first sidewall spacer 132 extends along the first outer sidewall 110a of the gate electrode 110, and the second sidewall spacer 134 extends along the second outer sidewall 110b of the gate electrode 110. The first sidewall spacer 132 is located above the first vertical portion 116 of the gate dielectric layer 112, and the second sidewall spacer 134 is located above the second vertical portion 118 of the gate dielectric layer 112.

[0020] Dielectric structure 136 is located on semiconductor substrate 102 and gate electrode 110. Dielectric structure 136 includes one or more dielectric layers (e.g., interlayer dielectric layer, intermetallic dielectric layer, etch stop layer, dielectric pad layer, etc.). First contact 138 extends through dielectric structure 136 to first source / drain region 104. Second contact 140 extends through dielectric structure 136 to second source / drain region 106. Third contact 142 extends through dielectric structure 136 to gate electrode 110.

[0021] In some embodiments, the gate electrode 110 is located below and above the top surface 102a of the semiconductor substrate 102, and directly between the first source / drain region 104 and the second source / drain region 106. In some such embodiments, the gate dielectric layer 112 is located below the top surface 102a of the semiconductor substrate 102. For example, the first outer sidewall 112c of the gate dielectric layer 112 extends from the upper surface 112e to the bottom surface 112b along the first sidewall (not shown) of the semiconductor substrate 102, the second outer sidewall 112d of the gate dielectric layer 112 extends from the upper surface 112g to the bottom surface 112b along the second sidewall (not shown) of the semiconductor substrate 102, and the bottom surface 112b of the gate dielectric layer 112 extends from the sidewall 112c to the sidewall 112d along the upper surface (not shown) of the semiconductor substrate 102. In these embodiments, the horizontal line (e.g., line A-A') intersects the source / drain regions 104, 106, the sidewalls 110a, 110b of the gate electrode 110, and the sidewalls 112c, 112f, 112h, 112d of the gate dielectric layer 112. In some embodiments, the top of the gate dielectric layer 112 (e.g., the upper surfaces 112e and 112g) is substantially coplanar with the top surface 102a of the semiconductor substrate 102.

[0022] In some embodiments, the semiconductor substrate 102 comprises silicon or other suitable semiconductors. In some embodiments, the semiconductor substrate 102 has a first doping type (e.g., p-type) and the source / drain regions 104, 106, 126, 128 have a second doping type (e.g., n-type) different from the first doping type. In some embodiments, the gate electrode 110 comprises aluminum, tungsten, hafnium, zirconium, titanium, tantalum, ruthenium, palladium, platinum, cobalt, nickel, or other suitable conductive materials. In some embodiments, the gate dielectric layer 112 comprises silicon oxide, hafnium oxide, aluminum oxide, or other suitable dielectric materials. In some embodiments, the STI structure 130 comprises silicon oxide, silicon nitride, or other suitable materials. In some embodiments, the sidewall spacers 132, 134 comprise silicon oxide, silicon nitride, or other suitable materials. In some embodiments, the dielectric layer of the dielectric structure 136 comprises silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or other suitable materials. In some embodiments, contacts 138, 140, 142 comprise tungsten, aluminum, or other suitable materials.

[0023] Figure 2 shows a top view 200 of some embodiments of the integrated wafer of Figure 1. Figure 3 shows a cross-sectional view 300, and Figure 4 shows a cross-sectional view 400 of some embodiments of the integrated wafer of Figure 2. In some embodiments, the top view 200 of Figure 2 is taken along line A-A' of Figure 1. In some embodiments, line B-B' of cross-sectional view 300 corresponds to line B-B' of top view 200, and line C-C' of cross-sectional view 400 corresponds to line C-C' of top view 200. Figure 2 is shown in the xy plane formed by axes 101x and 101y. Figure 3 is shown in the xz plane formed by axes 101x and 101z. Figure 4 is shown in the yz plane formed by axes 101y and 101z.

[0024] Figure 5 shows a top view 500 of some other embodiments of the integrated wafer of Figure 1. Figure 6 shows a cross-sectional view 600 of some embodiments of the integrated wafer of Figure 5. In some embodiments, the top view 500 of Figure 5 is taken along line A-A' of Figure 1. In some embodiments, line D-D' of cross-sectional view 600 corresponds to line D-D' of top view 500. Figure 5 is shown in the xy plane formed by axes 101x and 101y. Figure 6 is shown in the yz plane formed by axes 101y and 101z.

[0025] Referring to Figures 2-6, the gate electrode 110 and the gate dielectric layer 112 extend along axis 101y. In some embodiments (e.g., in the embodiments shown in Figures 2-4), the gate dielectric layer 112 (e.g., the vertical portion of the gate dielectric layer 112) laterally surrounds a portion of the gate electrode 110 in a closed path. For example, the gate electrode 110 is located directly between the sidewalls 112f and 112h of the gate dielectric layer 112, and directly between the sidewalls 112i and 112j of the gate dielectric layer. In some such embodiments, the upper surface 112e and the upper surface 112g are a continuous surface that laterally surrounds the gate electrode 110 in a closed path. In some other embodiments (e.g., in the embodiments shown in Figures 5-6), the gate dielectric layer 112 is located on opposite sides of the gate electrode 110, but does not surround the gate electrode 110 in a closed path. In some such embodiments, the upper surface 112e and the upper surface 112g are separate surfaces, spaced apart on opposite sides of the gate electrode 110.

[0026] In some embodiments, the distance 202 between the sidewalls 112f and 112h of the gate dielectric layer 112 (e.g., measured along axis 101x) ranges from 0.1 μm to 10 μm, 0.2 μm to 8 μm, or other suitable distances. In some embodiments, the distance 204 between the sidewalls 112c and 112f of the gate dielectric layer 112 and the distance 206 between the sidewalls 112d and 112h of the gate dielectric layer 112 (e.g., measured along axis 101x) ranges from 0.01 μm to 5 μm, 0.05 μm to 5 μm, or other suitable distances.

[0027] In some embodiments (e.g., FIG. 2), the distance 208 between the sidewalls 112i and 112j of the gate dielectric layer 112 (e.g., measured along axis 101y) ranges from 0.1 μm to 10 μm, 0.2 μm to 8 μm, or other suitable distances. In some embodiments, the distance 210 between the sidewall 112i of the gate dielectric layer 112 and the first edge of the active region of the transistor 101, and the distance 212 between the sidewall 112j of the gate dielectric layer 112 and the second edge of the active region of the transistor 101 (e.g., measured along axis 101y) range from 0.01 μm to 5 μm, 0.05 μm to 5 μm, or other suitable distances.

[0028] Figure 7 shows a cross-sectional view 700 of some embodiments of the integrated wafer of Figure 1, wherein multiple well regions are located in the semiconductor substrate 102. Figure 8 shows a top view 800 of some embodiments of the integrated wafer of Figure 7. Figure 9 shows a top view 900 of some embodiments of the integrated wafer of Figure 7. In some embodiments, the top view 800 of Figure 8 is taken along line E-E' of Figure 7. In some embodiments, the top view 900 of Figure 9 is taken along line F-F' of Figure 7.

[0029] The integrated wafer includes a transistor 101 and a second transistor 701 laterally spaced from the transistor 101. The transistor 701 includes a first source / drain region 702, a second source / drain region 704, a channel region 706, a gate electrode 708, a gate dielectric layer 710, a first lightly doped source / drain region 712, a second lightly doped source / drain region 714, a first sidewall spacer 716, and a second sidewall spacer 718. A first contact 726 extends through a dielectric structure 136 to the source / drain region 702. A second contact 728 extends through the dielectric structure 136 to the source / drain region 704. A third contact 730 extends through the dielectric structure 136 to the gate electrode 708. In some embodiments, an STI structure 130 surrounds the transistors 101 and 701 and extends directly between the transistors 101 and 701 to isolate the transistors 101 and 701.

[0030] A heavily doped well region 720 is located in a semiconductor substrate 102. In some embodiments, the heavily doped well region 720 has a first doping type. A first lightly doped well region 722 is located in the heavily doped well region 720. A second lightly doped well region 724 is located in the heavily doped well region 720 and laterally spaced from the first lightly doped well region 722. The heavily doped well region 720 surrounds the first lightly doped well region 722 and the second lightly doped well region 724 and extends directly between the first lightly doped well region 722 and the second lightly doped well region 724. The first lightly doped well region 722 and the second lightly doped well region 724 have a first doping type. Source / drain regions 104, 106, 126, and 128 have a second doping type different from the first doping type. The semiconductor substrate 102 has either a first doping type or a second doping type. The doping concentration of the heavily doped well region 720 is greater than the doping concentration of the first lightly doped well region 722 and greater than the doping concentration of the second lightly doped well region 724. In some embodiments, the STI structure 130 surrounds the first lightly doped well region 722 and the second lightly doped well region 724, and extends directly between the first lightly doped well region 722 and the second lightly doped well region 724.

[0031] Transistor 101 is disposed along a first lightly doped well region 722, while transistor 701 is disposed along a second lightly doped well region 724. For example, source / drain regions 104, 106 (and lightly doped source / drain regions 126, 128) and channel region 108 are located in the first lightly doped well region 722, while source / drain regions 702, 704 (and lightly doped source / drain regions 712, 714) and channel region 706 are located in the second lightly doped well region 724.

[0032] By including lightly doped well regions 722 and 724, the doping concentration along channel regions 108 and 706 can be reduced. Furthermore, reducing the doping concentration along channel regions 108 and 706 can reduce the short-channel effect of transistors 101 and 701. Moreover, reducing the short-channel effect can reduce the mismatch between transistors 101 and 701.

[0033] In some embodiments, the distance 902 between the first lightly doped well region 722 and the second lightly doped well region ranges from 0.1 μm to 0.9 μm, 0.2 μm to 0.8 μm, or other suitable ranges. In some embodiments, the distance 802 between the periphery of the source / drain region (e.g., source / drain region 106) of the first transistor and the periphery of the first lightly doped well region 722 ranges from 0.1 μm to 0.9 μm, 0.2 μm to 0.8 μm, or other suitable ranges. In some embodiments, the distance 804 between the periphery of the source / drain region (e.g., source / drain region 702) of transistor 701 and the periphery of the second lightly doped well region 724 ranges from 0.1 μm to 0.9 μm, 0.2 μm to 0.8 μm, or other suitable ranges. In some embodiments, the distances 902, 802, and 804 can be adjusted to adjust the threshold voltage of transistors 101 and 701 and reduce mismatch between transistors 101 and 701.

[0034] Figure 10 shows a cross-sectional view 1000, and Figure 11 shows a cross-sectional view 1100 of some embodiments of the integrated wafer of Figure 7, wherein the gate electrode 110 includes multiple metal layers. Figure 12 shows a top view 1200 of some embodiments of the integrated wafer of Figures 10 and 11. In some embodiments, the top view 1200 of Figure 12 is taken along line G-G' of Figure 10 and line H-H' of Figure 11.

[0035] The gate electrode 110 includes a first base metal layer 1002 and a first work function metal layer 1004. The first base metal layer 1002 laterally surrounds the first work function metal layer 1004 along its sidewalls. The first base metal layer 1002 contains a first metal. The first work function metal layer 1004 contains a second metal different from the first metal. The first work function metal layer 1004 (e.g., the second metal) has a first "type" of work function, while the source / drain regions 104, 106 have a second "type" of work function different from the first "type". For example, in an embodiment where the transistor 101 is an N-channel transistor (e.g., NMOS), the first source / drain region 104 and the second source / drain region 106 are N-type source / drain regions (e.g., source / drain regions with N-type work function and N-type doping), and the first work function metal layer 1004 contains a P-type work function metal (e.g., a work function metal with P-type work function). In embodiments where transistor 101 is a P-channel transistor (e.g., PMOS), the first source / drain region 104 and the second source / drain region 106 are P-type source / drain regions (e.g., source / drain regions having a P-type work function and P-type doping), and the first work function metal layer 1004 comprises an N-type work function metal (e.g., a work function metal having an N-type work function). In some embodiments, the N-type work function is in the range of about 3.5 electron volts (eV) to 4.5 electron volts, less than about 4.5 electron volts, less than about 4.3 electron volts, less than about 4.1 electron volts, or other suitable values. In some embodiments, the P-type work function is in the range of about 4.5 electron volts to 5.5 electron volts, greater than about 4.5 electron volts, greater than about 4.7 electron volts, greater than about 4.9 electron volts, or other suitable values.

[0036] By including a first work function metal layer 1004 (having a work function of a different type than that of the source / drain regions 104, 106) in the gate electrode 110, the critical voltage of the transistor 101 can be increased and / or adjusted (e.g., to counteract the critical voltage reduction caused by short-channel effects or similar factors). Increasing the critical voltage of the transistor 101 can reduce the mismatch between the transistor 101 and other transistors on the integrated wafer.

[0037] In some embodiments, a P-type work function metal is a material comprising a metal and having a work function in the range of about 4.5 eV to 5.5 eV, greater than about 4.5 eV, greater than about 4.7 eV, greater than about 4.9 eV, or other suitable values. In some embodiments, a P-type work function metal includes, for example, titanium nitride, tantalum nitride, tungsten carbonitride, platinum, palladium, nickel, combinations thereof, or other suitable materials.

[0038] In some embodiments, an N-type work function metal is a material comprising a metal and having a work function in the range of about 3.5 eV to 4.5 eV, less than about 4.5 eV, less than about 4.3 eV, less than about 4.1 eV, or other suitable values. In some embodiments, an N-type work function metal includes, for example, titanium, titanium aluminide, titanium aluminum carbide, tantalum, tantalum aluminide, tantalum aluminum carbide, zirconium, hafnium, combinations thereof, or other suitable materials.

[0039] In some embodiments, the integrated wafer includes silicon layers 1006 and 1008 located between contacts 138 and 140 and source / drain regions 104 and 106, wherein contacts 138 and 140 contact source / drain regions 104 and 106, respectively.

[0040] Figure 13 shows a cross-sectional view 1300, and Figure 14 shows a cross-sectional view 1400 of some embodiments of the integrated wafer of Figures 10-12, wherein the gate electrode 110 includes multiple base metal layers and multiple work function metal layers. Figures 15-17 show top views 1500-1700 of some embodiments of the integrated wafer of Figures 13 and 14. Figure 18 shows a cross-sectional view 1800 of some embodiments of the integrated wafer of Figures 16 and 17. In some embodiments, the top view 1500 of Figure 15 is taken along lines I-I' of Figure 13 and J-J' of Figure 14. In some embodiments, the top view 1600 of Figure 16 is taken along lines K-K' of Figure 18. In some embodiments, the top view 1700 of Figure 17 is taken along lines I-I' of Figure 13 and J-J' of Figure 14. In some other embodiments, the top view 1700 of Figure 17 is taken along lines K-K' of Figure 18.

[0041] In some embodiments, the gate electrode 110 includes a first base metal layer 1002 and a second base metal layer 1302, the second base metal layer 1302 being located above and between the sidewalls of the first base metal layer 1002. Furthermore, the gate electrode 110 includes a first work function metal layer 1004 and a second work function metal layer 1304, the second work function metal layer 1304 being located above and between the sidewalls of the first work function metal layer 1004. By including multiple work function metal layers and multiple base metal layers in the gate electrode 110, the threshold voltage of the transistor 101 can be further adjusted.

[0042] The base metal layers 1002 and 1302 contain tungsten, aluminum, or other suitable materials. The work function metal layers 1004 and 1304 contain hafnium, zirconium, titanium, tantalum, ruthenium, palladium, platinum, cobalt, nickel, or other suitable materials.

[0043] In some embodiments (e.g., as shown in Figures 15 and 17), a first portion and a second portion of the work function metal layers 1004 and 1304 are laterally spaced apart, and a base metal layer 1002 and 1302 laterally surround the first and second portions of the work function metal layers 1004 and 1304 and extend between the first and second portions of the work function metal layers 1004 and 1304. A portion of the work function metal layers 1004 and 1304 extends along axis 101x. In some embodiments (e.g., as shown in Figure 17), a third portion of the work function metal layers 1004 and 1304 is spaced between the first and second portions. In some embodiments (e.g., as shown in Figure 16), the work function metal layers 1004 and 1304 extend continuously from a first edge of the active region of the transistor 101 to a second edge of the active region. By adjusting the position of the work function metal layers 1004 and 1304 in the gate electrode 110, the threshold voltage of the transistor 101 can be further adjusted.

[0044] In some embodiments, the width of a portion of the work function metal layers 1004, 1304 (e.g., measured along axis 101x) ranges from 0.01 micrometers to 1 micrometer, 0.1 micrometers to 0.2 micrometers, or other suitable ranges. In some embodiments, the length of a portion of the work function metal layers 1004, 1304 (e.g., measured along axis 101y) ranges from 0.5 micrometers to 10 micrometers, 1 micrometer to 8 micrometers, or other suitable ranges.

[0045] Figures 19-21 show top views 1900-2100 of some other embodiments of the gate electrode 110 and gate dielectric layer 112 of Figures 15-17.

[0046] In some embodiments (e.g., as shown in FIG. 19), the first work function metal layer 1004 of the gate electrode 110 extends laterally from the first sidewall of the first base metal layer 1002 of the gate electrode 110, through the second base metal layer 1302 of the gate electrode 110, to the second sidewall of the first base metal layer 1002. In some embodiments (e.g., as shown in FIG. 20), the second base metal layer 1302 of the gate electrode 110 laterally surrounds the first work function metal layer 1004 of the gate electrode 110. In some embodiments (e.g., as shown in FIG. 21), the first work function metal layer 1004 of the gate electrode 110 extends laterally through the second base metal layer 1302 of the gate electrode 110 and into the first base metal layer 1002 of the gate electrode 110.

[0047] Figures 22-25 show cross-sectional views 2200-2500 of some other embodiments of the integrated wafer of Figure 18.

[0048] In some embodiments (e.g., as shown in FIG. 22), both the gate dielectric layer 112 and the gate electrode 110 are located below and above the top surface 102a of the semiconductor substrate 102. In some other embodiments (e.g., as shown in FIG. 23), the gate dielectric layer 112 is located below and above the top surface 102a of the semiconductor substrate 102, while the bottom surface 110c of the gate electrode 110 is spaced above the top surface 102a of the semiconductor substrate 102. In some other embodiments (e.g., as shown in FIG. 24 and FIG. 25), the gate dielectric layer 112 is located on the top surface 102a of the semiconductor substrate 102, while the bottom surface 110c of the gate electrode 110 is spaced above the top surface 102a of the semiconductor substrate 102. In some embodiments (e.g., as shown in FIG. 25), the gate dielectric layer 112 extends laterally along the top surface 102a of the semiconductor substrate 102 beyond the sidewall spacers 132, 134.

[0049] By adjusting the positions of the gate electrode 110 and the gate dielectric layer 112, the position of the channel region 108 can be adjusted, thereby adjusting the performance and reliability of the transistor 101.

[0050] Figures 26-37 show cross-sectional views 2600-3700 of some embodiments of a method for forming an integrated wafer including a transistor 101 along a semiconductor substrate 102. Although Figures 26-37 describe a method, it should be understood that the structures disclosed in Figures 26-37 are not limited to such a method, but can exist independently of the method.

[0051] As shown in the cross-sectional view 2600 of FIG26, the STI structure 130 is formed along the semiconductor substrate 102. The STI structure 130 surrounds a portion of the semiconductor substrate 102. In some embodiments, forming the STI structure 130 includes etching the semiconductor substrate 102 to form trenches in the semiconductor substrate 102, depositing a dielectric material in the trenches, and performing a planarization process (e.g., chemical mechanical planarization, etch planarization, or other suitable planarization process) on the dielectric material and the semiconductor substrate 102. In some embodiments, the STI structure 130 comprises silicon oxide or other suitable materials.

[0052] Furthermore, as shown in the cross-sectional view 2600 of FIG26, a heavily doped well region 720 is formed in the semiconductor substrate 102, a lightly doped well region 722 is formed in the heavily doped well region 720, and a pair of lightly doped source / drain regions 126, 128 are formed in the lightly doped well region 722. In some embodiments, the semiconductor substrate 102 comprises silicon or other suitable semiconductors. In some embodiments, the heavily doped well region 720 has a first doping type, the lightly doped well region 722 has a first doping type, and the lightly doped source / drain regions 126, 128 have a second doping type, different from the first doping type. In some embodiments, the heavily doped well region 720 is formed by a first ion implantation process or other suitable process, the lightly doped well region 722 is formed by a second ion implantation process or other suitable process, and the pair of lightly doped source / drain regions 126, 128 are formed by a third ion implantation process or other suitable process.

[0053] Figures 27-29 show cross-sectional views 2700-2900 of some embodiments of the method for forming a gate dielectric layer 112 and a dummy gate structure 2902 along a semiconductor substrate 102.

[0054] As shown in the cross-sectional view 2700 of FIG27, the semiconductor substrate 102 is etched to form trenches 2702 in the semiconductor substrate 102 between lightly doped source / drain regions 126, 128. In some embodiments, a masking layer 2704 is formed on the semiconductor substrate 102, and etching is performed based on the masking layer 2704. In some embodiments, etching includes dry etching processes, such as plasma etching, reactive ion etching, ion beam etching, or other suitable processes. In some embodiments, the trenches 2702 extend into the semiconductor substrate 102 to a depth less than the depth of the lightly doped source / drain regions 126, 128.

[0055] As shown in the cross-sectional view 2800 of Figure 28, a gate dielectric layer 112 is deposited in trench 2702. In some embodiments, the gate dielectric layer 112 comprises silicon oxide, hafnium oxide, aluminum oxide, or other suitable materials and is deposited using epitaxial growth, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. In some embodiments, after the gate dielectric layer 112 is deposited onto the semiconductor substrate 102, a planarization process is performed on the gate dielectric layer 112 and the semiconductor substrate 102 such that the top surface of the gate dielectric layer 112 and the top surface of the semiconductor substrate 102 are substantially coplanar. In some other embodiments, the gate dielectric layer 112 extends above the top surface of the semiconductor substrate 102 (e.g., as shown by dashed line 2802).

[0056] As shown in the cross-sectional view 2900 of FIG29, a dummy gate structure 2902 is formed on the gate dielectric layer 112, and a pair of sidewall spacers 132, 134 are formed along the sidewalls of the dummy gate structure 2902. In some embodiments, the dummy gate structure 2902 comprises polycrystalline silicon or other suitable materials and is deposited by CVD, PVD, ALD or other suitable processes. In some embodiments, the sidewall spacers 132, 134 comprise silicon oxide, silicon nitride or other suitable materials and are deposited by CVD, PVD, ALD or other suitable processes.

[0057] Figure 30 shows a cross-sectional view 3000 of some other embodiments of the method for forming a gate dielectric layer 112 and a dummy gate structure 2902 along a semiconductor substrate 102.

[0058] As shown in the cross-sectional view 3000 of Figure 30, the step of etching the semiconductor substrate 102 to form the trench 2702 is omitted. Instead, a gate dielectric layer 112 is deposited on the top surface of the semiconductor substrate 102. Furthermore, a dummy gate structure 2902 is formed on the gate dielectric layer 112, and sidewall spacers 132, 134 are formed along the sidewalls of the dummy gate structure 2902. In some embodiments, the gate dielectric layer 112 is etched to define the gate dielectric layer 112. In some other embodiments, the gate dielectric layer 112 extends laterally along the semiconductor substrate 102 beyond the sidewall spacers 132, 134, as shown by dashed line 3002.

[0059] As shown in the cross-sectional view 3100 of Figure 31, a pair of source / drain regions 104, 106 are formed along the semiconductor substrate 102 on opposite sides of the dummy gate structure 2902, and are respectively formed in lightly doped source / drain regions 126, 128. In some embodiments, the source / drain regions 104, 106 are formed by an ion implantation process or other suitable process. The source / drain regions 104, 106 have a second doping type. The doping concentration of the source / drain regions 104, 106 is greater than the doping concentration of the lightly doped source / drain regions 126, 128.

[0060] As shown in the cross-sectional view 3200 of Figure 32, one or more dielectric layers of dielectric structure 136 are formed over semiconductor substrate 102 and dummy gate structure 2902. Furthermore, a planarization process is performed on the dielectric layer of dielectric structure 136 to remove the dielectric layer over dummy gate structure 2902. In some embodiments, the dielectric layer of dielectric structure 136 comprises silicon oxide, silicon nitride, or other suitable materials and is deposited by CVD, PVD, ALD, or other suitable processes. In some embodiments, the planarization process includes chemical mechanical planarization or other suitable processes.

[0061] As shown in the cross-sectional view 3300 of FIG33, the dummy gate structure 2902 is removed from between the sidewall spacers 132, 134 and above the gate dielectric layer 112, thereby leaving an opening 3302 at the location of the dummy gate structure 2902. Furthermore, a portion of the gate dielectric layer 112 is removed to form a trench 3304 in the gate dielectric layer 112. In some embodiments, removing the dummy gate structure 2902 and a portion of the gate dielectric layer 112 includes etching the dummy gate structure 2902 and the gate dielectric layer 112 using a dry etching process or other suitable process according to the masking layer 3306. In some embodiments, the gate dielectric layer 112 laterally surrounds the trench 3304 in a closed path (e.g., as shown in FIG2). In some other embodiments, the gate dielectric layer 112 is located on the opposite side of the trench 3304 (e.g., as shown in FIG5).

[0062] As shown in the cross-sectional view 3400 of FIG34, a gate electrode 110 is formed in the opening 3302 and the trench 3304 to replace the dummy gate structure 2902 and fill the trench 3304. The gate electrode 110 is formed by depositing a first base metal layer 1002 in the opening 3302 and the trench 3304. In some embodiments, the first base metal layer 1002 fills the opening 3302 and the trench 3304. In some other embodiments, one or more additional base metal layers are deposited over the first base metal layer 1002 in the opening 3302 and the trench 3304. For example, in some embodiments, a second base metal layer 1302 is deposited over the first base metal layer 1002 in the opening 3302 and the trench 3304. In some embodiments, the first base metal layer 1002 comprises a first metal and is deposited by a first deposition process, while the second base metal layer 1302 comprises a second metal and is deposited by a second deposition process. In some embodiments, the first metal and / or the second metal comprises tungsten, aluminum, or other suitable materials. In some embodiments, the first deposition process and / or the second deposition process includes any one of CVD, PVD, ALD, or other suitable processes. In some embodiments, a planarization process is performed on the base metal layer after deposition.

[0063] As shown in the cross-sectional view 3500 of FIG35, the base metal layer of the gate electrode 110 is etched to form a trench 3502 in the base metal layer. For example, in some embodiments, a second base metal layer 1302 and a first base metal layer 1002 are etched to form the trench 3502 in the second base metal layer 1302 and the first base metal layer 1002. In some embodiments, the second base metal layer 1302 and the first base metal layer 1002 are etched using a dry etching process or other suitable etching process according to the masking layer 3504. In some embodiments, the etching exposes the upper surface of the gate dielectric layer 112.

[0064] As shown in the cross-sectional view 3600 of FIG36, the gate electrode 110 is further formed by depositing a first work function metal layer 1004 in a trench 3502. In some embodiments, the first work function metal layer 1004 fills the trench 3502. In some other embodiments, one or more additional work function metal layers are deposited over the first work function metal layer 1004 in the trench 3502. For example, in some embodiments, a second work function metal layer 1304 is deposited over the first work function metal layer 1004 in the trench 3502. In some embodiments, the first work function metal layer 1004 comprises a third metal and is deposited by a third deposition process, while the second work function metal layer 1304 comprises a fourth metal and is deposited by a fourth deposition process. In some embodiments, the third metal and / or the fourth metal comprises any one of hafnium, zirconium, titanium, tantalum, ruthenium, palladium, platinum, cobalt, nickel, or other suitable materials. In some embodiments, the third deposition process and / or the fourth deposition process includes any one of CVD, PVD, ALD, or other suitable processes. In some embodiments, a planarization process is performed on the work function metal layer after deposition.

[0065] As shown in the cross-sectional view 3700 of FIG37, contacts are formed over a semiconductor substrate 102 and in contact with a transistor. For example, a first contact 138 is formed on a first source / drain region 104, a second contact 140 is formed on a second source / drain region 106, and a third contact (not shown) is formed on a gate electrode 110. In some embodiments, contacts are formed by etching a dielectric structure 136 to expose portions of the first source / drain region 104, the second source / drain region 106, and the gate electrode 110, and then depositing metal (e.g., tungsten, aluminum, or other suitable material) on the etched dielectric structure 136 (e.g., using a CVD process, PVD process, ALD process, or other suitable process). In some embodiments, a silicate layer is formed along the bottom of the contacts. For example, in some embodiments, a first silicate layer 1006 is formed along the bottom of the first contact 138, and a second silicate layer 1008 is formed along the bottom of the second contact 140.

[0066] Figure 38 illustrates flowcharts of some embodiments of a method 3800 for forming an integrated wafer comprising transistors along a semiconductor substrate. While method 3800 is illustrated and described below as a series of operations or events, it should be understood that the order in which these operations or events are illustrated should not be interpreted in a limiting sense. For example, some operations may occur in a different order than those illustrated and / or described herein, and / or simultaneously with other operations or events. Furthermore, not all illustrated operations need to implement one or more aspects or embodiments described herein. Further, one or more operations described herein may be performed in one or more independent operations and / or stages.

[0067] In block 3802, a heavily doped well region is formed in the semiconductor substrate, and a lightly doped well region is formed within the heavily doped well region. In some embodiments, a pair of lightly doped source / drain regions are formed in the lightly doped well region. Figure 26 shows a cross-sectional view 2600 corresponding to some embodiments of block 3802.

[0068] In block 3804, a gate dielectric layer is deposited along the semiconductor substrate. In some embodiments, a trench is formed in the semiconductor substrate, and the gate dielectric layer is deposited in the trench. In some other embodiments, the gate dielectric layer is deposited on the top surface of the semiconductor substrate. Figure 28 shows a cross-sectional view 2800 corresponding to some embodiments of block 3804. Figure 30 shows a cross-sectional view 3000 corresponding to some other embodiments of block 3804.

[0069] In block 3806, a dummy gate structure is formed on top of the gate dielectric layer. Figure 29 shows a cross-sectional view 2900 corresponding to some embodiments of block 3806. Figure 30 shows a cross-sectional view 3000 corresponding to some other embodiments of block 3806.

[0070] In block 3808, a pair of source / drain electrodes are formed in the lightly doped well regions on opposite sides of the dummy gate structure. Figure 31 shows a cross-sectional view 3100 corresponding to some embodiments of block 3808.

[0071] In block 3810, the dummy gate structure is removed above the gate dielectric layer. Figure 33 shows a cross-sectional view 3300 corresponding to some embodiments of block 3810.

[0072] In block 3812, a portion of the gate dielectric layer is removed to form a first trench in the gate dielectric layer. Figure 33 shows a cross-sectional view 3300 corresponding to some embodiments of block 3812.

[0073] In block 3814, a first metal layer is deposited in the first trench to form a gate electrode in the first trench. Figure 34 shows a cross-sectional view 3400 corresponding to some embodiments of block 3814.

[0074] In block 3816, a first metal layer is etched to form a second trench in the first metal layer. Figure 35 shows a cross-sectional view 3500 corresponding to some embodiments of block 3816.

[0075] In block 3818, a second metal layer is deposited in the second trench. The second metal has a different work function type than the source / drain. Figure 36 shows a cross-sectional view 3600 corresponding to some embodiments of block 3818.

[0076] Accordingly, in some embodiments, this disclosure relates to an integrated wafer including a semiconductor substrate, a first source / drain region, a second source / drain region, a gate electrode, and a gate dielectric layer. The first source / drain region and the second source / drain region are along the semiconductor substrate. A channel region extends along the semiconductor substrate from the first source / drain region to the second source / drain region. The gate electrode is located between the first source / drain region and the second source / drain region. The gate electrode has a first outer sidewall, a second outer sidewall, and a bottom surface extending from the first outer sidewall to the second outer sidewall. The gate dielectric layer is located between the gate electrode and the channel region. A lateral portion of the gate dielectric layer extends laterally along the bottom surface of the gate electrode. A first vertical portion of the gate dielectric layer extends upward from the lateral portion along the first outer sidewall of the gate electrode. A second vertical portion of the gate dielectric layer extends upward from the lateral portion along the second outer sidewall of the gate electrode.

[0077] In other embodiments, this disclosure relates to an integrated wafer including a semiconductor substrate, a first source / drain region, a second source / drain region, a gate dielectric layer, and a gate electrode. The first and second source / drain regions are along the semiconductor substrate. A channel region extends along the semiconductor substrate from the first source / drain region to the second source / drain region. The gate dielectric layer is located above the channel region and between the first and second source / drain regions. The gate dielectric layer has a first inner sidewall, a second inner sidewall, and a first upper surface extending from the bottom of the first inner sidewall to the bottom of the second inner sidewall. The gate electrode is located between the first and second source / drain regions. The gate electrode is located above the first upper surface of the gate dielectric layer and between the first and second inner sidewalls of the gate dielectric layer. A horizontal line intersects the gate electrode, the first inner sidewall of the gate dielectric layer, and the second inner sidewall of the gate dielectric layer.

[0078] In other embodiments, this disclosure relates to a method of forming an integrated wafer. The method includes depositing a gate dielectric layer along a semiconductor substrate. The method includes forming a dummy gate structure over the gate dielectric layer. The method includes forming a first source / drain region and a second source / drain region on opposite sides of the dummy gate structure along the semiconductor substrate. The method includes etching the dummy gate structure to remove the dummy gate structure over the gate dielectric layer. The method includes etching the gate dielectric layer to remove a portion of the gate dielectric layer to form a first trench in the gate dielectric layer. The method includes forming a gate electrode over the gate dielectric layer and in the first trench.

[0079] The features of the above embodiments are designed to facilitate understanding of this disclosure by those skilled in the art. Those skilled in the art should understand that this disclosure can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of this disclosure, and changes, substitutions, or modifications can be made without departing from the spirit and scope of this disclosure.

[0080] 100, 300, 400, 600, 700, 1000, 1100, 1300, 1400, 1800, 2200, 2300, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, 3200, 3300, 3400, 3500, 3600, 3700: Sectional View 101x, 101y, 101z: Axes 101: Transistor 102: Semiconductor substrate 102a, 110d: Top surface 104,702: First source / drain region, source / drain region 106,704: Second source / drain region, source / drain region 108,706: Passage Area 110,708: Gate electrode 110a, 112c: First outer lateral wall / sidewall 110b, 112d: Second lateral wall / sidewall 110c, 112b: Bottom surface 112,710: Gate dielectric layer 112a: First upper surface / upper surface 112e: Second upper surface / upper surface 112f: First inner wall / side wall 112g: Third upper surface / upper surface 112h: Second inner wall / side wall 112i, 112j: Sidewall 114: Horizontal section 116: First vertical section 118: Second vertical section 120: First thickness 122: Second thickness 124: Third Thickness 126,712: First lightly doped source / drain region, lightly doped source / drain region, source / drain region 128,714: Second lightly doped source / drain region, lightly doped source / drain region, source / drain region 130: Shallow Trench Insulation (STI) Structure 132,716: First sidewall spacer / sidewall spacer 134,718: Second sidewall spacer / sidewall spacer 136: Dielectric Structure 138,726: First contact / contact 140,728: Second contact / contact 142,730: Third contact / contact 200, 500, 800, 900, 1200, 1500, 1600, 1700, 1900, 2000, 2100: Top View 202,204,206,208,210,212,802,804,902: Distance 701: Second Transistor / Transistor 720: Heavily doped well region 722: First lightly doped well region / lightly doped well region 724: Second lightly doped well region / lightly doped well region 1002: First base metal layer / base metal layer 1004: First work function metal layer / work function metal layer 1006: First silicide layer / silicide layer 1008: Second silicide layer / silicide layer 1302: Second base metal layer / base metal layer 1304: Second work function metal layer / work function metal layer 2702, 3304, 3502: Trench 2704, 3306, 3504: Masking layer 2802, 3002: Dashed lines 2902: Virtual gate structure 3302: Opening 3800: Method Blocks 3802, 3804, 3806, 3808, 3810, 3812, 3814, 3816, and 3818: A-A',B-B',C-C',D-D',E-E',F-F',G-G',H-H',I-I',J-J',K-K': line

Claims

1. An integrated chip, comprising: Semiconductor substrate; A first source / drain region and a second source / drain region are arranged along the semiconductor substrate in a first direction, wherein a channel region extends along the semiconductor substrate from the first source / drain region to the second source / drain region; a gate electrode is located between the first source / drain region and the second source / drain region, the gate electrode having a first outer sidewall, a second outer sidewall, and a bottom surface extending from the first outer sidewall to the second outer sidewall; and a gate dielectric layer is located between the gate electrode and the channel region, a lateral portion of the gate dielectric layer extending laterally along the bottom surface of the gate electrode, a first vertical portion of the gate dielectric layer extending upward from the lateral portion along the first outer sidewall of the gate electrode, and a second vertical portion of the gate dielectric layer extending upward from the lateral portion along the second outer sidewall of the gate electrode. The gate dielectric layer laterally surrounds a first portion of the gate electrode. The first portion of the gate electrode includes a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall. The first sidewall is formed by the first outer sidewall, the second sidewall is formed by the second outer sidewall, the third sidewall connects between the first sidewall and the second sidewall in a second direction, and the fourth sidewall connects between the first sidewall and the second sidewall in the second direction and is opposite to the third sidewall. The first direction is parallel to the top surface of the semiconductor substrate and perpendicular to the second direction. The first vertical portion of the gate dielectric layer is adjacent to the first sidewall, the second vertical portion of the gate dielectric layer is adjacent to the second sidewall, the third vertical portion of the gate dielectric layer is adjacent to the third sidewall, and the fourth vertical portion of the gate dielectric layer is adjacent to the fourth sidewall. The second portion of the gate electrode is located on the first portion of the gate electrode and extends in the second direction, covering the third vertical portion and the fourth vertical portion.

2. The integrated wafer as claimed in claim 1, wherein the top of the first vertical portion and the top of the second vertical portion are above the bottom surface of the gate electrode and below the top surface of the gate electrode.

3. The integrated wafer as claimed in claim 1, wherein the distance between the top of the first vertical portion and the bottom of the lateral portion and the distance between the top of the second vertical portion and the bottom of the lateral portion are greater than the distance between the top of the lateral portion and the bottom of the lateral portion.

4. The integrated wafer as claimed in claim 1, wherein the lateral portion is partially formed by a bottom surface of the gate dielectric layer and a first upper surface of the gate dielectric layer extending along the bottom surface of the gate electrode, wherein the first vertical portion is formed by the bottom surface of the gate dielectric layer, a first inner wall of the gate dielectric layer extending upward from the first upper surface of the gate dielectric layer along the first outer wall of the gate electrode, a first outer wall of the gate dielectric layer extending upward from the bottom surface of the gate dielectric layer, and a portion extending from the first inner wall of the gate dielectric layer to... The second upper surface of the gate dielectric layer is partially formed on the first outer sidewall of the gate dielectric layer, and wherein the second vertical portion is partially formed by the bottom surface of the gate dielectric layer, the second inner sidewall of the gate dielectric layer extending upward from the first upper surface of the gate dielectric layer along the second outer sidewall of the gate electrode, the second outer sidewall of the gate dielectric layer extending upward from the bottom surface of the gate dielectric layer, and the third upper surface of the gate dielectric layer extending from the second inner sidewall of the gate dielectric layer to the second outer sidewall of the gate dielectric layer.

5. An integrated chip, comprising: Semiconductor substrate; A first source / drain region and a second source / drain region are arranged along the semiconductor substrate in a first direction, wherein a channel region extends along the semiconductor substrate from the first source / drain region to the second source / drain region; a gate dielectric layer is located above the channel region and between the first source / drain region and the second source / drain region, the gate dielectric layer having a first inner sidewall, a second inner sidewall, and a first upper surface extending from the bottom of the first inner sidewall to the bottom of the second inner sidewall; A gate electrode is provided, located between the first source / drain region and the second source / drain region. The gate electrode is situated above the first upper surface of the gate dielectric layer and between the first inner sidewall and the second inner sidewall of the gate dielectric layer. The gate dielectric layer laterally surrounds a first portion of the gate electrode. The first portion of the gate electrode includes a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall. The first sidewall is connected to the first inner sidewall, the second sidewall is connected to the second inner sidewall, the third sidewall connects between the first and second sidewalls in a second direction, and the fourth sidewall connects between the first and second sidewalls in the second direction and is opposite to the third sidewall. The first direction is parallel to the top surface of the semiconductor substrate and perpendicular to the second direction. The gate dielectric layer includes: a first vertical portion adjacent to the first sidewall; a second vertical portion adjacent to the second sidewall; a third vertical portion adjacent to the third sidewall; and a fourth vertical portion adjacent to the fourth sidewall. The second portion of the gate electrode is located on the first portion of the gate electrode and extends in the second direction, and covers the third vertical portion and the fourth vertical portion.

6. The integrated wafer as claimed in claim 5, wherein the bottom surface of the gate electrode and the first upper surface of the gate dielectric layer are below the top surface of the semiconductor substrate, the top of the first source / drain region, and the top of the second source / drain region, wherein the first inner sidewall of the gate dielectric layer is located between the first outer sidewall of the gate electrode and the first source / drain region, and wherein the second inner sidewall of the gate dielectric layer is located between the second outer sidewall of the gate electrode and the second source / drain region.

7. The integrated wafer of claim 5, wherein the bottom surface of the gate electrode and the first upper surface of the gate dielectric layer are above the top surface of the semiconductor substrate, the top of the first source / drain region, and the top of the second source / drain region, and wherein the bottom surface of the gate dielectric layer is below the top surface of the semiconductor substrate, the top of the first source / drain region, and the top of the second source / drain region.

8. The integrated wafer of claim 5, wherein the bottom surface of the gate electrode and the first upper surface of the gate dielectric layer are above the top surface of the semiconductor substrate, the top of the first source / drain region and the top of the second source / drain region, and wherein the bottom surface of the gate dielectric layer is located on the top surface of the semiconductor substrate.

9. A method for forming an integrated wafer, the method comprising: Deposit a gate dielectric layer along the semiconductor substrate; A virtual gate structure is formed on the gate dielectric layer; A first source / drain region and a second source / drain region are formed on opposite sides of the dummy gate structure in a first direction along the semiconductor substrate; the dummy gate structure is etched to remove the dummy gate structure from the gate dielectric layer; The gate dielectric layer is etched to remove a portion of the gate dielectric layer, thereby forming a first trench in the gate dielectric layer, wherein the gate dielectric layer includes: a lateral portion exposed by the first trench; a first vertical portion adjacent to a first sidewall of the first trench; a second vertical portion adjacent to a second sidewall of the first trench, the first sidewall and the second sidewall being opposite each other in a first direction; a third vertical portion adjacent to a third sidewall of the first trench, the third sidewall being connected between the first sidewall and the second sidewall in the first direction; and a fourth vertical portion adjacent to a fourth sidewall of the first trench, the fourth sidewall being connected between the first sidewall and the second sidewall in the first direction, and the fourth sidewall being opposite to the third sidewall in a second direction, wherein the first direction and the second direction are parallel to the top surface of the semiconductor substrate, and the first direction and the second direction are perpendicular; and a gate electrode is formed above the third vertical portion and the fourth vertical portion of the gate dielectric layer and in the first trench.

10. The method as described in claim 9, further comprising: The semiconductor substrate is etched to form a second trench in the semiconductor substrate, wherein the gate dielectric layer is deposited in the second trench.

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