Semiconductor device manufacturing method

Abstract

A memory device in one embodiment includes: a first memory cell array; a second memory cell array disposed relative to the first memory cell array in a first direction; a first contact plug extending in the first memory cell array along the first direction; and a second contact plug extending in the second memory cell array along the first direction and electrically connected to the first contact plug. The first memory cell array includes a plurality of first electrode layers stacked in the first direction and a first semiconductor pillar penetrating the plurality of first electrode layers. The second memory cell array includes a plurality of second electrode layers stacked in the first direction and a second semiconductor pillar penetrating the plurality of second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar.

Description

Technical Field

[0001] The embodiment relates to a memory device. Prior Art

[0002] The industry is promoting the development of memory devices including memory cells with a three-dimensional configuration. For example, a NAND (Not AND) type memory device includes a plurality of stacked electrode layers and semiconductor pillars disposed in memory holes that penetrate the plurality of electrode layers in the stacking direction. Memory cells are disposed at portions where the semiconductor pillars intersect the electrode layers and are arranged along the semiconductor pillars. By increasing the number of stacked electrode layers and by miniaturizing the memory holes to increase the number of the memory holes, such a memory device can increase the memory capacity. However, there is a limit to increasing the number of memory holes and the number of stacked electrode layers within the limited chip size of the memory device. Summary of the Invention

[0003] The embodiment provides a memory device capable of increasing the memory capacity.

[0004] The memory device of the embodiment includes: a first memory cell array; a second memory cell array disposed in a first direction with respect to the first memory cell array; a first contact plug extending in the first direction in the first memory cell array; and a second contact plug extending in the first direction in the second memory cell array and electrically connected to the first contact plug. The first memory cell array includes: a plurality of first electrode layers stacked in the first direction; and a first semiconductor pillar penetrating the plurality of first electrode layers in the first direction. The second memory cell array includes: a plurality of second electrode layers stacked in the first direction; and a second semiconductor pillar penetrating the plurality of second electrode layers in the first direction. The first contact plug is electrically connected to the first semiconductor pillar. The second contact plug is electrically connected to the second semiconductor pillar. Brief Description of the Drawings

[0005] FIG. 1 is a schematic cross-sectional view showing a memory device according to the first embodiment. FIGS. 2A and 2B are schematic plan views showing the configuration of a memory cell array of the memory device according to the first embodiment. FIG. 3 is a schematic plan view showing the upper surface of a memory cell array of the memory device according to the first embodiment. FIG. 4 is a schematic cross-sectional view showing a memory cell array of the memory device according to the first embodiment. Figs. 5A to 8B, Fig. 9, and Fig. 10 are schematic cross-sectional views showing the manufacturing process of the memory cell array of the memory device according to the first embodiment. Fig. 11 is a schematic top view showing the configuration of the memory cell array of the memory device according to the second embodiment. Figs. 12A and 12B are schematic views showing the memory cell array of the memory device according to the second embodiment. Figs. 13A to 13C are schematic views showing the manufacturing process of the memory cell array of the memory device according to the second embodiment. Figs. 14A to 14C are schematic views showing the manufacturing process of the memory cell array of the memory device according to a modification of the second embodiment. Figs. 15A to 15C are schematic views showing the manufacturing process of the memory cell array of the memory device according to another modification of the second embodiment. Figs. 16A and 16B are schematic cross-sectional views showing the manufacturing process of the memory device according to the third embodiment. Figs. 17A to 17C are schematic cross-sectional views showing the manufacturing process of the memory device according to a modification of the third embodiment. Figs. 18A and 18B are schematic cross-sectional views showing the manufacturing process of the memory device according to another modification of the third embodiment. Figs. 19A and 19B are schematic top views showing the memory device according to the fourth embodiment. Fig. 20 is another schematic top view showing the memory device according to the fourth embodiment. Fig. 21 is a schematic cross-sectional view showing the memory device according to the fourth embodiment. Fig. 22 is another schematic cross-sectional view showing the memory device according to the fourth embodiment. Figs. 23A and 23B are schematic cross-sectional views showing the memory device according to a modification of the fourth embodiment. Embodiments

[0006] Hereinafter, the embodiments will be described with reference to the drawings. The same parts in the drawings are denoted by the same reference numerals, and their detailed descriptions are appropriately omitted, and different parts will be described. The drawings are schematic diagrams or conceptual diagrams, and the relationships between the thicknesses and widths of the respective parts, the ratios of the sizes between the parts, etc. are not necessarily the same as in reality. Furthermore, even when showing the same part, there are cases where the mutual dimensions or ratios are shown differently according to the drawings.

[0007] Furthermore, the arrangement and configuration of each part will be described using the X-axis, Y-axis, and Z-axis shown in the respective figures. The X-axis, Y-axis, and Z-axis are mutually orthogonal and represent the X-direction, Y-direction, and Z-direction, respectively. Furthermore, for convenience, there are cases where the description is made according to the upper and lower sides in the figure, but it is not intended to represent all common upper and lower relationships. [First Embodiment]

[0008] FIG. 1 is a schematic cross-sectional view showing a memory device 1 according to the first embodiment. The memory device 1 is, for example, a NAND-type flash memory device and has a structure in which memory cell arrays 20, 30, and 40 are stacked on a drive circuit 10. Also, in FIG. 1, insulating films provided between the respective components are omitted in order to show the structure of the memory device 1.

[0009] The drive circuit 10 has, for example, a substrate 11 on which electronic devices such as CMOS (Complementary Metal Oxide Semiconductor) transistors are provided, and a wiring layer 13 provided on the substrate 11. The substrate 11 is, for example, a silicon substrate. A CMOS-type integrated circuit is provided on the upper surface side of the substrate 11.

[0010] The memory cell array 20 has a plurality of electrode layers 21 stacked in the Z direction, a plurality of semiconductor pillars 23, and a source line 25. The semiconductor pillars 23 respectively penetrate the electrode layers 21 and extend in the Z direction. One end of the semiconductor pillar 23 is electrically connected to the source line 25. A plurality of semiconductor pillars 23 share one source line 25. Furthermore, the other end of the semiconductor pillar 23 is electrically connected to the wiring 27.

[0011] The memory cell array 30 has a plurality of electrode layers 31 stacked in the Z direction, a plurality of semiconductor pillars 33, and a source line 35. The semiconductor pillars 33 respectively penetrate the electrode layers 31 and extend in the Z direction. One end of the semiconductor pillar 33 is electrically connected to the source line 35. A plurality of semiconductor pillars 33 share one source line 35. Furthermore, the other end of the semiconductor pillar 33 is electrically connected to the wiring 37.

[0012] The memory cell array 40 has a plurality of electrode layers 41 stacked in the Z direction, a plurality of semiconductor pillars 43, and a source line 45. The semiconductor pillars 43 respectively penetrate the electrode layers 41 and extend in the Z direction. One end of the semiconductor pillar 43 is electrically connected to the source line 45. A plurality of semiconductor pillars 43 share one source line 45. Furthermore, the other end of the semiconductor pillar 43 is electrically connected to the wiring 47.

[0013] The electrode layers 21, 31, and 41 are electrically connected to the contact plug 51 at their stepped ends. Further, the electrode layers 21, 31, and 41 are electrically connected to the drive circuit 10 via the contact plug 51 and the contact plug 53. The contact plug 53 is arranged to penetrate each of the memory cell arrays 20, 30, and 40. The contact plug 53 electrically connects the electrode layers 21, 31, and 41 in each of the memory cell arrays stacked above the drive circuit 10 to the wiring 15 in the wiring layer 13.

[0014] Furthermore, other contact plugs 55 that penetrate each of the memory cell arrays are arranged in each of the memory cell arrays. The contact plug 55 electrically connects, for example, the drive circuit 10 to an interface circuit (not shown).

[0015] The memory device 1 further includes contact plugs 60 extending in the Z direction in each of the memory cell arrays. The contact plugs 60 are arranged to penetrate, for example, a plurality of electrode layers 21 in each of the memory cell arrays. The contact plugs 60 extend, for example, longer than the total width Ws in the Z direction of the plurality of electrode layers 21, 31, and 41 stacked in the Z direction. The contact plugs 60 include, for example, a metal such as tungsten.

[0016] As shown in FIG. 1, a contact plug 60a is arranged in the memory cell array 20, and contact plugs 60b and 60c are arranged in the memory cell arrays 30 and 40, respectively. In this specification, there are cases where the contact plugs 60a, 60b, and 60c are collectively referred to as the contact plug 60. The same applies to other components.

[0017] Furthermore, connection pads 61 and 63 are respectively arranged in each of the memory cell arrays. The connection pad 61 is arranged on the lower surface of each of the memory cell arrays, and the connection pad 63 is arranged on the upper surface of each of the memory cell arrays.

[0018] As shown in FIG. 1, at the boundary between the memory cell array 20 and the memory cell array 30, the connection pad 63a and the connection pad 61b are arranged to be connected to each other. The contact plug 60a is electrically connected to the connection pad 63a. On the other hand, the contact plug 60b is electrically connected to the connection pad 61b via the wiring 65b. That is, the contact plug 60a and the contact plug 60b are electrically connected via the connection pads 63a and 61b.

[0019] Similarly, at the boundary between the memory cell array 20 and the memory cell array 30, the connection pad 63b and the connection pad 61c are arranged to be connected to each other. Further, the contact plug 60b and the contact plug 60c are electrically connected via the connection pads 63b and 61c.

[0020] Furthermore, in the memory cell array 20, the wiring 27 connected to the semiconductor column 23 is connected to the wiring 65a, and the wiring 65a is electrically connected to the contact plug 60a. Similarly, in the memory cell array 30, the wiring 37 connected to the semiconductor column 33 is electrically connected to the contact plug 60b and the connection pad 61b via the wiring 65b. Furthermore, in the memory cell array 40, the wiring 47 connected to the semiconductor column 43 is electrically connected to the contact plug 60c and the connection pad 61c via the wiring 65c.

[0021] In this way, it is possible to interconnect the semiconductor columns included in each of the memory cell arrays stacked on the driving circuit 10 via the contact plugs 60. Also, the semiconductor columns interconnected via the contact plugs 60 are connected to, for example, a sense amplifier (not shown) of the driving circuit 10 via the connection pad 61a located between the driving circuit 10 and the memory cell array 20, or the connection pad 63c provided on the upper surface of the memory cell array 40, an upper layer wiring (not shown), and the contact plug 53.

[0022] In this embodiment, it is possible to interconnect the semiconductor columns 23, 33, and 43 included in the memory cell arrays 20, 30, and 40, respectively, to operate as one memory string including, for example, memory cells MC (see FIG. 4) arranged along each semiconductor column.

[0023] For example, if the memory cell arrays 20, 30, and 40 each include 64 electrode layers, the memory device 1 can achieve a memory capacity equivalent to that of a memory cell array having 192 stacked electrode layers. For example, in order to form memory holes in a stack having 192 continuously stacked electrode layers and form semiconductor columns inside the memory holes, extremely high wafer manufacturing technology is required. In contrast, in the memory device 1, by stacking the individually formed memory cell arrays 20, 30, and 40 and electrically connecting them to each other using the contact plugs 60 and the connection pads 61 and 63, it is possible to easily achieve a memory capacity equivalent to the case of continuously stacking 192 electrode layers.

[0024] Furthermore, when forming semiconductor columns that penetrate 192 electrode layers, there is a concern that the cell current may become small due to the resistance of the semiconductor columns, making it difficult to read data from the memory cells MC. In this embodiment, for example, the semiconductor columns 23, 33, and 43 that penetrate 64 electrode layers are connected in parallel, so the resistance of each semiconductor column is lower than that of a semiconductor column that penetrates 192 electrode layers. Therefore, the memory device 1 can suppress a decrease in the cell current.

[0025] Furthermore, the present embodiment is not limited to the above example. For example, two memory cell arrays may be stacked on the drive circuit 10, and furthermore, four or more memory cell arrays may be stacked. Next, with reference to FIGS. 2 to 4, the configuration of each memory cell array will be described in detail.

[0026] FIGS. 2A and 2B are schematic plan views showing the configuration of the memory cell array 20 of the memory device 1 according to the first embodiment. FIG. 2B is a plan view showing the region MP shown in FIG. 2A. The memory cell arrays 30 and 40 have the same structure as the memory cell array 20.

[0027] As shown in FIG. 2A, the electrode layer 21 extends in the X direction, is stacked in the Z direction, and is arranged along the Y direction. Slits ST are provided between the electrode layers 21 adjacent in the Y direction to electrically isolate the electrode layers 21 from each other. Furthermore, a stepped lead-out portion HUP is provided at the end of the electrode layer 21 in the X direction. Further, a contact area CA is provided in a part of the electrode layer 21.

[0028] As shown in FIG. 2B, a plurality of memory holes MH are provided in the electrode layer 21. The memory holes MH penetrate through the plurality of electrode layers 21 and extend in the Z direction, and semiconductor columns 23 (see FIG. 1) are respectively arranged inside the memory holes MH. Further, a plurality of wirings 27 extending in the Y direction are provided. One of the plurality of semiconductor columns 23 that penetrate through two adjacent electrode layers 21 in the Y direction is connected to one of the plurality of wirings 27. That is, one wiring 27 is shared by one semiconductor column 23 that penetrates through the plurality of electrode layers 21 arranged along the Y direction.

[0029] Furthermore, contact holes PH are provided in the contact area CA. The contact holes PH penetrate through the plurality of electrode layers 21 and extend in the Z direction. As shown in FIG. 2B, a contact plug 60a is provided inside the contact hole PH. The contact plug 60a includes a metal such as tungsten and is electrically insulated from the electrode layer 21 by an insulating film 67 provided in the contact hole PH. The insulating film 67 is, for example, a silicon oxide film.

[0030] FIG. 3 is a schematic plan view showing the lower surface of the memory cell array 20. As shown in FIG. 3, between the contact areas CA, a plurality of wirings 27 are arranged and configured along the X direction. The wirings 27 respectively extend in the Y direction. In the contact area CA, a plurality of contact plugs 60a are arranged and configured along the Y direction. Further, a plurality of connection pads 61a are arranged between the contact areas CA.

[0031] The connection pad 61a is disposed above the wiring 27 and is connected to any one of the contact plugs 60a via the wiring 65a respectively. For example, the number of the connection pads 61a disposed between the contact areas CA is the same as the number of the wirings 27 disposed therebetween. The wiring 65a is connected to the contact plug 60a via the contact plug 71. Further, the wiring 65a is connected to one of the wirings 27 via the contact plug 73.

[0032] FIG. 4 is a schematic cross-sectional view showing the memory cell array 20. Further, FIG. 4 is a cross-sectional view in which FIG. 1 is upside down. Further, in FIG. 4, in order to clearly show the configuration of the memory cell array 20, the insulating films that electrically insulate between the respective components are appropriately omitted.

[0033] As shown in FIG. 4, a plurality of electrode layers 21 are stacked above the source line 25. The source line 25 is, for example, a plate-shaped conductive layer extending in the X direction and the Y direction. The source line 25 has a structure in which, for example, a metal layer 25a and a semiconductor layer 25b are stacked. The metal layer 25a is, for example, a tungsten layer, and the semiconductor layer 25b is, for example, polysilicon. The electrode layer 21 is, for example, a metal layer containing tungsten or the like.

[0034] The semiconductor column 23 penetrates the electrode layer 21 in the stacking direction (Z direction), and is connected to the source line 25 at the lower end of the semiconductor column 23. Further, the upper end of the semiconductor column 23 is electrically connected to the wiring 27 via the contact plug 26.

[0035] A memory film 29 is disposed between the electrode layer 21 and the semiconductor column 23. The memory film 29 has a structure in which, for example, a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are sequentially stacked in the direction from the electrode layer 21 toward the semiconductor column 23, and can hold charges inside the memory film 29 and release charges from inside the memory film 29. Memory cells MC are respectively disposed at portions where the semiconductor column 23 penetrates the electrode layer 21, and a part of the memory film 29 is included as a charge holding portion.

[0036] As shown in FIG. 4, the contact plug 60a penetrates a plurality of electrode layers 21 and the source line 25 and extends in the Z direction. The contact plug 60a is electrically insulated from the electrode layer 21 and the source line 25 by the insulating film 67.

[0037] The lower end of the contact plug 60a is electrically connected to the connection pad 63a. Furthermore, the upper end of the contact plug 60a is electrically connected to the wiring 65a via the intermediate wiring 69 and the contact plugs 71, 77. The intermediate wiring 69 is provided at the same level as the wiring 27, for example. The contact plug 77 connects the contact plug 60a and the intermediate wiring 69. The contact plug 71 connects the wiring 65a and the intermediate wiring 69. Furthermore, the wiring 65a is connected to one wiring 27 via the contact plug 73 and is electrically connected to the connection pad 61a via the contact plug 75.

[0038] Furthermore, the memory cell array 20 further includes a contact plug 80 electrically connected to the source line 25. The contact plug 80 penetrates through a plurality of electrode layers 21 and extends in the Z direction. The contact plug 80 is provided in the contact area CA together with the contact plug 60a, for example.

[0039] The lower end of the contact plug 80 is electrically connected to the source line 25. Furthermore, the upper end of the contact plug 80 is electrically connected to the connection pad 81 via the intermediate wirings 85, 87, and the contact plugs 91, 93, and 95. The intermediate wirings 85 and 87 are respectively provided at the same level as the wiring 65a and the wiring 27. The contact plug 91 connects the contact plug 80 and the intermediate wiring 87. The contact plug 93 connects the intermediate wiring 85 and the intermediate wiring 87. Furthermore, the intermediate wiring 85 is electrically connected to the connection pad 81 via the contact plug 91. Furthermore, the source line 25 is electrically connected to the connection pad 83 via the contact plug 97, for example.

[0040] The memory cell arrays 30 and 40 also similarly include the contact plug 80, and the connection pads 81 and 83. When the memory cell arrays 20, 30, and 40 are stacked as shown in FIG. 1, the respective source lines 25, 35, and 45 are electrically connected via the contact plug 80, the connection pads 81, and 83. That is, at the boundary between the memory cell array 20 and the memory cell array 30, the connection pad 83 of the memory cell array 20 is connected to the connection pad 81 of the memory cell array 30. Furthermore, at the boundary between the memory cell array 30 and the memory cell array 40, the connection pad 83 of the memory cell array 30 is connected to the connection pad 81 of the memory cell array 40.

[0041] Next, with reference to FIGS. 5 to 10, a method for manufacturing the memory device 1 according to the first embodiment will be described. FIGS. 5 to 10 are schematic cross-sectional views showing the manufacturing process of the memory cell arrays 20, 30, and 40 stacked on the driving circuit 10.

[0042] As shown in FIG. 5A, a substrate 110 having a convex portion 101 on its upper surface is formed. The convex portion 101 is formed, for example, by selectively etching the substrate 110. The substrate 110 is, for example, a silicon substrate.

[0043] As shown in FIG. 5B, an insulating film 103 covering the upper surface of the substrate 110 is formed. The insulating film 103 is, for example, a silicon nitride film formed using LPCVD (Low Pressure Chemical Vapor Deposition).

[0044] As shown in FIG. 5C, an insulating film 105 is formed on the insulating film 103. The insulating film 105 is, for example, a silicon oxide film formed using CVD (Chemical Vapor Deposition) with TEOS (Tetraethyl orthosilicate) as a raw material.

[0045] As shown in FIG. 5D, the insulating film 105 is planarized to expose a part of the insulating film 103 formed on the convex portion 101. The insulating film 105 is planarized, for example, using CMP (Chemical Mechanical Polishing).

[0046] As shown in FIG. 6A, an insulating film 107 is formed on the insulating film 105 and on the convex portion 101. The insulating film 107 is, for example, a silicon oxide film formed using TEOS-CVD. Next, a contact plug 111 is formed from the upper surface of the insulating film 107 to the convex portion 101.

[0047] As shown in FIG. 6B, an insulating film 109 is formed on the insulating film 107. The insulating film 109 is, for example, a silicon oxide film formed using TEOS-CVD. Next, the insulating film 109 is selectively removed to form a wiring 115. The wiring 115 is electrically connected to the substrate 110 via the contact plug 111, for example.

[0048] As shown in FIG. 6C, a memory cell array 20 is formed on the insulating film 109. The memory cell array 20 includes a plurality of electrode layers 21 stacked in the Z direction, a plurality of semiconductor pillars 23 penetrating the electrode layers 21 in the Z direction, and a source line 25. Further, the memory cell array 20 includes contact plugs 51 respectively connected to the electrode layers 21 and a contact plug 53 connected to the wiring 115. Further, contact plugs 60a and 80 are formed in a part not shown.

[0049] As shown in FIG. 7A, an insulating film 121 is formed on the memory cell array 20. The insulating film 121 is, for example, a silicon oxide film formed using TEOS-CVD. Next, connection pads 123 are formed in the insulating film 121. The connection pads 123 are electrically connected to the contact plugs 53 via the contact plugs 125, for example. Furthermore, connection pads 61a and 81 (refer to FIG. 4) are also formed simultaneously in a part not shown. The connection pads 61a, 81, and 123 contain copper or a copper alloy, for example.

[0050] As shown in FIG. 7B, the drive circuit 10 is bonded to the memory cell array 20. For example, the upper surface of the insulating film 121 is brought into contact with the upper surface of the drive circuit 10, and bonding is performed at a temperature of 300 to 400°C and a specified pressure. At this time, the connection pads 123 are connected to the connection pads 127 on the drive circuit 10 side. The connection pads 127 also contain copper or a copper alloy, for example.

[0051] As shown in FIG. 8A, the substrate 110 is removed. For example, after thinning the back side of the substrate 110 by polishing or grinding, it is selectively removed by wet etching. Thereby, the insulating film 103 is exposed, and after removing the convex portions 101, recesses 131 are formed. On the bottom surface of the recesses 131, the upper surfaces of the contact plugs 111 are exposed.

[0052] As shown in FIG. 8B, connection pads 133 are formed by embedding a metal such as copper or a copper alloy, for example, inside the recesses 131. At this time, connection pads 63a and 83 are also formed simultaneously in a part not shown.

[0053] The connection pads 133 are connected to the contact plugs 111, for example. The connection pads 133 have a shape in which the width W T1 of the upper surface is larger than the width W B1 of the lower surface, for example. In contrast, the contact plugs 111 have a shape in which the width W T2 of the upper surface is smaller than the width W B2 of the lower surface.

[0054] As shown in FIG. 9, the memory cell array 30 is bonded on the memory cell array 20. The memory cell array 30 is formed by the same method as the memory cell array 20. Connection pads 133 are formed on the upper surface side of the memory cell array 30 in FIG. 9. At the boundary between the memory cell array 20 and the memory cell array 30, the connection pads 133 are connected to the connection pads 123. Furthermore, in a part not shown, the connection pad 63a of the memory cell array 20 is connected to the connection pad 61b of the memory cell array 30 (refer to FIG. 1). Further, the connection pad 83 of the memory cell array 20 is connected to the connection pad 81 of the memory cell array 30 (refer to FIG. 4), and the source line 25 is electrically connected to the source line 35.

[0055] As shown in FIG. 10, a memory cell array 40 is bonded on top of the memory cell array 30. The memory cell array 40 is formed by the same method as the memory cell arrays 20 and 30. A connection pad 135 is formed on the upper surface side of the memory cell array 40 in FIG. 10. The connection pad 135 includes aluminum, for example. That is, the connection pad 135 is the uppermost layer wiring and is formed, for example, in such a manner that it can be connected to an external circuit by wire bonding.

[0056] As shown in FIG. 10, at the boundary between the memory cell array 30 and the memory cell array 40, the connection pad 133 is also connected to the connection pad 123. Furthermore, in a part not shown, the connection pad 63b of the memory cell array 30 is connected to the connection pad 61c of the memory cell array 40 (refer to FIG. 1). Further, the connection pad 83 of the memory cell array 30 is connected to the connection pad 81 of the memory cell array 40 (refer to FIG. 4), and the source line 35 is electrically connected to the source line 45.

[0057] In the above manufacturing process, by providing the convex portion 101 on the upper surface of the substrate 110, a connection pad can be formed on the upper surface of each memory cell array after bonding. Furthermore, as long as the convex portion 101 is formed in a manner having a wiring pattern, a connection pad and the wiring connected to the connection pad can be formed. Thereby, photolithography and etching of the insulating film after bonding can be omitted, and the manufacturing process of the memory device 1 can be simplified. [Second Embodiment]

[0058] FIG. 11 is a schematic plan view showing the configuration of a memory cell array 50 of a memory device according to the second embodiment. The memory cell array 50 includes electrode layers 21a, 21b, and 21c arranged along the Y direction. The electrode layers 21a, 21b, and 21c extend along the X direction, and are separated by slits ST between the electrode layer 21a and the electrode layer 21b, and between the electrode layer 21b and the electrode layer 21c. Furthermore, the electrode layers 21a, 21b, and 21c are stacked in the Z direction and are penetrated by a plurality of memory holes MH extending in the Z direction. A semiconductor column 23 (not shown) is provided inside each memory hole MH.

[0059] The memory cell array 50 includes a plurality of wirings 27 extending along the Y direction on the electrode layers 21a, 21b, and 21c. The wirings 27 are arranged along the X direction, for example. Each wiring 27 is electrically connected to one semiconductor column penetrating the electrode layer 21a, one semiconductor column penetrating the electrode layer 21b, and one semiconductor column penetrating the electrode layer 21c.

[0060] In this example, the contact plug 160 is disposed inside the slit ST. The contact plug 160 extends in the Z direction, and its length is longer than the respective total heights of the electrode layers 21a, 21b, and 21c laminated in the Z direction. Furthermore, the contact plug 160 is electrically connected to one wiring 27 via the contact plug 141 respectively. That is, the contact plugs 160 having the same number as the wirings 27 are provided inside the slit ST.

[0061] Figs. 12A and 12B are schematic diagrams showing the memory cell array 50 of the memory device according to the second embodiment. Fig. 12A is a schematic plan view showing the upper surface of the memory cell array 50. Fig. 12B is a schematic diagram of a cross section along the line 12B-12B shown in Fig. 12A.

[0062] As shown in Fig. 12A, a plurality of connection pads 140 are provided on the wiring 27. The connection pads 140 are electrically connected to one wiring 27 respectively. That is, the connection pads 140 having the same number as the wirings 27 are arranged above the plurality of wirings 27 arranged in the X direction.

[0063] As shown in Fig. 12B, the contact plug 160 extends in the Z direction inside the slit ST. The contact plug 160 extends longer than the lamination width WS of the electrode layer 21. Furthermore, the contact plug 160 is electrically insulated from the electrode layer 21 and the source line 120 by the insulating film 167.

[0064] The contact plug 160 is connected to the connection pad 150 at its lower end. Furthermore, the contact plug 160 is electrically connected to one of the wirings 27 via the contact plug 141 at its upper end. Further, the wiring 27 is electrically connected to the connection pad 140 via the contact plug 143. As a result, the contact plug 160 is electrically connected to one of the wirings 27 and one of the connection pads 140.

[0065] In this embodiment, a plurality of memory cell arrays 50 are laminated on the driving circuit 10 (see Fig. 1) for example. The memory cell array 50 is laminated with the structure shown in Fig. 12B upside down. At this time, the connection pad 150 of one memory cell array 50 is connected to the connection pad 140 of the other memory cell array 50 laminated thereon. Thereby, the semiconductor columns 23 of the memory cell arrays 50 laminated vertically are electrically connected.

[0066] Furthermore, in this embodiment, the source lines 120 of the memory cell arrays 50 laminated vertically are also electrically connected via a contact plug (for example, the contact plug 80 in Fig. 4) not shown.

[0067] FIG. 13 is a schematic diagram showing the manufacturing process of the memory cell array 50 of the second embodiment. FIGS. 13A to 13C are schematic top views showing the formation process of the contact plug 160.

[0068] As shown in FIG. 13A, an insulating film 167 is embedded in the slit ST between the electrode layers 21. The insulating film 167 is, for example, a silicon oxide film formed by CVD. At this time, semiconductor columns 23 (not shown) and memory films 29 are respectively formed inside the memory holes MH.

[0069] As shown in FIG. 13B, an etching mask 181, for example, a resist film, is formed so as to cover the memory hole MH and the insulating film 167. The etching mask 181 has an opening 181a located on the slit ST. Then, using the etching mask 181, the insulating film 167 is selectively removed to form a contact hole 185 that extends in the Z direction within the slit ST and communicates with a portion (refer to FIGS. 6A and 12B) that becomes the connection pad 150.

[0070] As shown in FIG. 13C, a contact plug 160 is formed inside the contact hole 185. The contact plug 160 is a metal layer embedded inside the contact hole 185 and contains, for example, tungsten.

[0071] FIG. 14 is a schematic diagram showing the manufacturing process of the memory cell array 50 of a modification of the second embodiment. FIGS. 14A to 14C are schematic top views showing the formation process of the contact plug 170. The contact plug 170 extends longer than the stacking width WS of the electrode layer 21 within the slit ST.

[0072] As shown in FIG. 14A, the slit ST formed between the electrode layers 21 includes a first portion WP and a second portion NP. The width W1 in the Y direction of the first portion WP is greater than the width W2 in the Y direction of the second portion NP.

[0073] As shown in FIG. 14B, an insulating film 167 is formed inside the slit ST. The insulating film 167 is, for example, a silicon oxide film formed by CVD. The insulating film 167 is formed, for example, so as to have a thickness that closes the second portion NP and leaves a contact hole 187 in the first portion WP. In other words, it is formed such that the difference between the width W1 of the first portion WP and the width W2 of the second portion NP is greater than the width in the Y direction of the contact plug 170.

[0074] As shown in FIG. 14C, a contact plug 170 is formed inside the contact hole 187. The contact plug 170 is a metal layer embedded inside the contact hole 187 and contains, for example, tungsten.

[0075] FIG. 15 is a schematic cross-sectional view showing the manufacturing process of the memory cell array 50 of another variation of the second embodiment. FIGS. 15A to 15C are schematic top views showing the formation process of the contact plug 180. The contact plug 180 extends longer than the stacking width WS of the electrode layer 21 within the slit ST.

[0076] As shown in FIG. 15A, the slit ST formed between the electrode layers 21 has, for example, a circular opening and is formed in a shape in which a plurality of contact holes CH are connected in the X direction. The contact holes CH are formed, for example, so as to extend in the Z direction and communicate with a portion that becomes the connection pad 150 (see FIGS. 6A and 12B). The contact holes CH are formed, for example, so that their diameter RS is larger than the diameter of the contact plug 180.

[0077] As shown in FIG. 15B, an insulating film 167 is formed inside the slit ST. The insulating film 167 is, for example, a silicon oxide film formed by CVD. The insulating film 167 is formed, for example, to have a thickness that leaves a contact space 189 inside the contact hole CH.

[0078] As shown in FIG. 15C, a contact plug 180 is formed inside the contact space 189. The contact plug 180 is a metal layer embedded inside the contact space 189 and contains, for example, tungsten. [Third Embodiment]

[0079] FIG. 16 is a schematic cross-sectional view showing the manufacturing process of the memory device 1 of the third embodiment. FIG. 16A is a schematic top view of a wafer 5 formed by bonding, for example, the memory cell array 20 and the memory cell array 30 (see FIG. 1). FIG. 16B is a schematic cross-sectional view taken along line 16B-16B shown in FIG. 16A.

[0080] As shown in FIG. 16A, the wafer 5 includes, for example, an air gap AG extending in the X direction. The air gap AG extends to the outer edge of the wafer 5 and is provided so as to communicate with the outside at both ends.

[0081] As shown in FIG. 16B, the air gap AG is provided at the boundary between the memory cell array 20 and the memory cell array 30. That is, the air gap AG is formed at the boundary where the memory cell array 20 and the memory cell array 30 are bonded and serves as a discharge path for the air remaining between the two. Thereby, a so-called void is formed at the boundary between the memory cell array 20 and the memory cell array 30, and poor bonding can be prevented.

[0082] The air gap AG is formed by forming a groove EG in either one of the memory cell arrays 20 and 30, or both, and bonding them together.

[0083] The air gap AG is provided, for example, in a so-called dicing region KR between wafers cut out from the wafer 5. The dicing region KR is provided so as to surround a device region DR including memory cells MC and respective wirings. Thereby, the adhesion of the joint surface between the memory cell arrays in the device region DR can be improved.

[0084] FIG. 17 is a schematic cross-sectional view showing a manufacturing process of the memory device 1 according to a modification of the third embodiment. FIGS. 17A to C are schematic views showing a part corresponding to a cross section along the line 16B-16B shown in FIG. 16A.

[0085] As shown in FIG. 17A, after bonding the memory cell array 20 and the drive circuit 10, recesses 131 and 201 are formed on the upper surface of the memory cell array 20. The recesses 131 and 201 are formed, for example, by removing the substrate 110 from the memory cell array 20 (see FIG. 8A).

[0086] As shown in FIG. 17B, a metal is embedded in the recesses 131 and 201 to form connection pads 133 and metal patterns 205. The connection pads 133 and the metal patterns 205 are formed using, for example, copper or a copper alloy.

[0087] In this process, for example, a metal layer thicker than the depth of the recesses 131 and 201 is formed on the upper surface of the memory cell array 20. Then, for example, CMP is used to remove the metal layer so as to leave the portions embedded in the recesses 131 and 201.

[0088] At this time, if the ratio of the area of the metal pattern 205 to the surface area of the dicing region KR is large, a groove EG is formed in the dicing region KR by so-called dishing. That is, the ratio of the area of the metal pattern 205 to the surface area of the dicing region KR is made larger than, for example, the ratio of the area of the connection pad 133 to the area of the device region DR of the memory cell array 20, so as to form the groove EG in the dicing region KR.

[0089] As shown in FIG. 17C, the memory cell array 20 and the memory cell array 30 are bonded. In the device region DR, for example, the connection pad 133 of the memory cell array 20 is connected to the connection pad 123 of the memory cell array 30. On the other hand, in the cutting region KR, an air gap AG is formed at the position of the groove EG. Thereby, it is possible to avoid forming a gap between the memory cell arrays, and the close contact between the two can be improved.

[0090] Furthermore, by linearly arranging a plurality of grooves EG on the wafer respectively and extending them unidirectionally, the warping of the wafer can be reduced. Moreover, as described above, by utilizing the concave deformation during CMP, the groove EG can be formed without using, for example, photolithography and selective etching. Thereby, the manufacturing steps of each memory cell array can be simplified.

[0091] FIG. 18 is a schematic cross-sectional view showing the manufacturing process of the memory device 1 according to another variation of the third embodiment. FIGS. 18A and B are schematic views showing a part corresponding to the cross-section along the line 16B-16B shown in FIG. 16A.

[0092] As shown in FIG. 18A, in the air gap AG, it can also be formed in such a manner that the metal pattern 215 is exposed on the entire inner surface of the groove EG. That is, the metal pattern 215 can also be formed in such a manner that the width in the X direction becomes substantially the same as the width in the X direction of the groove EG. Thereby, the concave deformation during CMP becomes larger, and the groove EG can be formed deeper. As a result, the width of the air gap AG in the Z direction can be expanded. The metal pattern 215 is formed using, for example, copper or a copper alloy.

[0093] In the example shown in FIG. 18B, the memory cell array 220 and the memory cell array 230 are bonded. The memory cell arrays 220 and 230 include contact plugs 223 and 233, and the end faces of the contact plugs 223 and 233 function as connection pads. That is, as shown in FIG. 18, when the memory cell array 220 and the memory cell array 230 are bonded, the contact plug 233 of the memory cell array 220 and the contact plug 223 of the memory cell array 230 can be directly connected. Moreover, the metal pattern 215 is exposed on the inner surface of the air gap AG formed at the boundary between the two.

[0094] In the above embodiment, when the memory device 1 is cut out from the wafer 5 and diced, a part of the air gap AG remains at the outer edge of the wafer. That is, in the memory device 1 of the third embodiment, the area ratio of the metal pattern 205 exposed at a part of the air gap AG to the insulating film 105 is larger than the area ratio of the connection pad 133 at the boundary between the memory cell arrays to the insulating film 105. [Fourth Embodiment]

[0095] Figures 19A and 19B are schematic top views showing the memory device 2 of the fourth embodiment. Figure 19A is a top view showing the arrangement of the memory cells MC of the memory device 2. Figure 19B is a top view showing the memory cells MC of the memory device 2.

[0096] As shown in Figure 19A, the memory device 2 includes a plurality of electrode layers 321 extending in the X direction. The electrode layers 321 are arranged in the Y direction. Further, the electrode layers 321 are stacked in the Z direction with an interlayer insulating film (not shown) therebetween. An insulator 311 is embedded in the space MT between adjacent electrode layers 321 in the Y direction. The insulator 311 is, for example, silicon oxide.

[0097] The memory holes MH of the memory device 2 are provided so as to penetrate the insulator 311 in the Z direction. Further, the memory holes MH are formed so as to divide the insulator 311 into a plurality of parts. The memory device 2 further includes contact holes STH penetrating the insulator 311 in the Z direction. A contact plug 330 and 340 are disposed inside the contact holes STH. Further, an insulating film 331 is provided inside the contact holes STH for electrically insulating the contact plugs 330 and 340 from the electrode layer 321.

[0098] As shown in Figure 19B, a semiconductor column 310 extending in the Z direction is provided inside the memory hole MH. The semiconductor column 310 includes an insulating core 313 and a semiconductor layer 315. The insulating core 313 is, for example, silicon oxide extending in the Z direction. The semiconductor layer 315 covers the side surface of the insulating core 313 and extends in the Z direction. The semiconductor layer 315 is, for example, polysilicon.

[0099] An insulating film 317 is further provided inside the memory hole MH. The insulating film 317 is provided between the inner wall of the memory hole MH and the semiconductor column 310. The insulating film 317 is, for example, a silicon oxide film.

[0100] As shown in Figure 19B, the memory cell of the memory device 2 includes, for example, a floating gate FG. The floating gate FG is provided so as to extend from the insulating film 317 covering the inner wall of the memory hole MH to the inside of the electrode layer 321. An insulating film 323 is provided between the floating gate FG and the electrode layer 321.

[0101] The floating gate FG is disposed so as to extend into each of the electrode layers 321 stacked in the Z direction, and is arranged separately from the memory holes extending in the Z direction. One memory hole MH is provided between two adjacent electrode layers 321 in the Y direction, and floating gates FG are provided in the two electrode layers 321 respectively. The two floating gates FG function independently of each other. That is, in the memory device 2, two memory cells MC can be arranged for each memory hole MH between the electrode layers 321 located at the same height in the Z direction.

[0102] In each memory cell MC, a portion of the insulating film 317 between the semiconductor column 310 and the floating gate FG functions as a tunneling insulating film. Further, a portion of the insulating film 323 between the electrode layer 321 and the floating gate FG functions as a blocking insulating film.

[0103] FIG. 20 is a top view showing another mode of the memory device 2. As shown in FIG. 20, a plurality of bit lines 350 are provided in the Y direction intersecting the electrode layer 321. The bit lines 350 are arranged above the memory holes MH and are electrically connected to the semiconductor columns 310 via contact plugs 351.

[0104] As shown in FIG. 20, the contact holes STH are arranged in a row in the Y direction. The bit lines 350 are not arranged above the contact holes STH. Each bit line 350 is electrically connected to a contact plug 330 provided inside the contact hole STH via a wiring 333. The bit line 350 is electrically connected to any one of the plurality of contact plugs 330.

[0105] FIG. 21 is a cross-sectional view showing a mode of the memory device 2. FIG. 21 is a cross-sectional view taken along the line 20A-20A shown in FIG. 20 and includes the contact plug 330. Also, for convenience, the illustration of the insulating films and insulators that electrically insulate between the respective elements is omitted in FIG. 21.

[0106] As shown in FIG. 21, the memory device 2 includes a plurality of memory cell arrays 20 stacked on the driving circuit 10, such as memory cell arrays 20A, 20B, 20C, and 20D. The number of stacked layers of the memory cell arrays 20 is arbitrary and is not limited to this example.

[0107] Each memory cell array 20 includes a plurality of semiconductor columns 310, contact plugs 330, bit lines 350, and source lines 370. One end of each semiconductor column 310 is electrically connected to the bit line 350, and the other end is electrically connected to the source line 370. For convenience, the illustration of the contact plug 351 is omitted in FIG. 21.

[0108] The source line 370 is, for example, a plate-shaped conductor extending in the X direction and the Y direction. The electrode layer 321 is laminated on the source line 370 (refer to FIG. 19A). Further, the contact plug 330 is disposed so as to extend in the Z direction through a through hole SH provided in the source line 370. The contact plug 330 is electrically insulated from the source line 370 by the insulating film 331.

[0109] In each memory cell array 20, the contact plug 330 is electrically connected to one of the bit lines 350 via the wiring 333. As shown in FIG. 21, the wiring 333 is connected to the bit line 350 via the contact plug 339 and is connected to the contact plug 330 via the contact plug 337.

[0110] Furthermore, the contact plugs 330 of each memory cell array 20 are connected in series in the Z direction. The contact plugs 330 of the memory cell arrays 20B and 20C are connected to the upper and lower contact plugs 330 via the solder pads 343 and 345, respectively. As shown in FIG. 21, the solder pad 343 is electrically connected to the wiring 333 via the contact plug 335. The solder pad 345 is connected to one end of the contact plug 330.

[0111] The arrangement of the solder pads 343 and 345 is not limited to this example, and for example, they may be arranged between the bit line 350 and the source line 370 as shown in FIGS. 1 and 3.

[0112] The contact plug 330 of the memory cell array 20D is electrically connected to the wiring 410 via the solder pad 345 and the contact plug 347. The wiring 410 is electrically connected to the sense amplifier SA of the drive circuit 10 via, for example, the contact plug 53 provided around the memory cell array 20 (refer to FIG. 1). As a result, the bit lines 350 of each memory cell array 20 are connected in parallel to the sense amplifier SA via the contact plugs 330. Thereby, without reducing the cell current flowing through each semiconductor pillar 310, the memory cell arrays 20 can be stacked in multiple stages, and thus the memory capacity of the memory device 2 can be increased.

[0113] FIG. 22 is a cross-sectional view showing another mode of the memory device 2. FIG. 21 is a cross-sectional view taken along the line 20B-20B shown in FIG. 20 and includes the contact plug 340. For convenience, the illustration of the insulating film and insulator for electrically insulating between the respective elements is also omitted in FIG. 21.

[0114] As shown in FIG. 22, in each memory cell array 20, the contact plug 340 is connected to the source line 370. Furthermore, the contact plug 340 is electrically connected to the pad 343 via the wiring 333, the contact plugs 335 and 337. On the other hand, the source line 370 is electrically connected to the pad 345 via the contact plug 349.

[0115] For example, the source lines 370 of the memory cell arrays 20B and 20C are electrically connected to the source lines 370 of the upper and lower memory cell arrays 20 via the pads 343 and 345.

[0116] The contact plug 340 of the memory cell array 20D is electrically connected to the wiring 420 via the pad 345 and the contact plug 349. The wiring 420 is electrically connected to the driving transistor of the driving circuit 10 via the contact plug 53 (refer to FIG. 1) provided around the memory cell array 20, for example. As a result, the source lines 370 of the respective memory cell arrays 20 are connected in series via the contact plugs 340 and are electrically connected to the driving circuit 10.

[0117] FIGS. 23A and 23B are schematic cross-sectional views of the memory device 3 showing a modification of the fourth embodiment. FIGS. 23A and 23B are schematic diagrams showing a cross-section including the contact plug 330, respectively, and FIG. 23B is a schematic diagram showing a cross-section different from that of FIG. 23A.

[0118] In the example shown in FIG. 23A, the contact plug 330 of the memory cell array 20B is electrically connected to the bit line 350 via the wiring 333. On the other hand, the respective contact plugs 330 of the memory cell arrays 20A, 20C, and 20D are not electrically connected to the bit line 350. That is, one bit line 350 is electrically connected to the wiring 410B via the serially connected contact plugs 330 and is further connected to the sense amplifier SA.

[0119] In the example shown in FIG. 23B, the contact plug 330 of the memory cell array 20C is electrically connected to the bit line 350 via the wiring 333. On the other hand, the respective contact plugs 330 of the memory cell arrays 20A, 20B, and 20D are not electrically connected to the bit line 350. Therefore, one bit line 350 is electrically connected to the wiring 410C via the serially connected contact plugs 330.

[0120] Thus, in the memory device 3, one bit line 350 in the multi-level stacked memory cell array 20 is connected to one sense amplifier SA via the contact plug 330 connected in series. Thereby, the memory cell array 20 can be multi-level stacked without reducing the cell current flowing through each semiconductor column 310, and the data readout speed from each memory cell MC can be increased.

[0121] As described above, in the present embodiment, an example in which each bit line 350 of the multi-level stacked memory cell array 20 is connected in parallel to the sense amplifier SA via the contact plug 330 connected in series, and an example in which one bit line 350 in the multi-level stacked memory cell 20 is connected to one sense amplifier SA are illustrated. However, the embodiment is not limited to these. For example, depending on the number of bit lines in each memory cell array 20 and the number of contact holes STH, any number of bit lines 350 in the multi-level stacked memory cell 20 can be connected in parallel to the sense amplifier SA via the contact plug 330 connected in series.

[0122] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or their variations are included in the scope or gist of the invention and are included in the invention described in the claims and its equivalents. [Related Application]

[0123] This application claims priority based on Japanese Patent Application No. 2017-42675 (filing date: March 7, 2017). This application incorporates the entire contents of the base application by reference thereto.

[0124] 1: Memory device 10: Drive circuit 11: Substrate 13: Wiring layer 15: Wiring 20: Memory cell array 21: Electrode layer 21a: Electrode layer 21b: Electrode layer 21c: Electrode layer 23: Semiconductor column 25: Source line 25a: Metal layer 25b: Semiconductor layer 27: Wiring 29: Memory film 30: Memory cell array 31: Electrode layer 33: Semiconductor column 35: Source line 37: Wiring 40: Memory cell array 41: Electrode layer 43: Semiconductor column 45: Source line 47: Wiring 50: Memory cell array 51: Contact plug 53: Contact plug 55: Contact plug 60a: Contact plug 60b: Contact plug 60c: Contact plug 61a: Connection pad 61b: Connection pad 61c: Connection pad 63a: Connection pad 63b: Connection pad 63c: Connection pad 65a: Wiring 65b: Wiring 65c: Wiring 69: Intermediate wiring 71: Contact plug 73: Contact plug 75: Contact plug 77: Contact plug 80: Contact plug 81: Connection pad 83: Connection pad 85: Intermediate wiring 87: Intermediate wiring 91: Contact plug 93: Contact plug 95: Contact plug 97: Contact plug 101: Protrusion 103: Insulating film 105: Insulating film 107: Insulating film 109: Insulating film 110: Substrate 111: Contact plug 115: Wiring 120: Source line 121: Insulating film 123: Connection pad 125: Contact plug 127: Connection pad 131: Recess 133: Connection pad 135: Connection pad 140: Connection pad 150: Connection pad 160: Contact plug 167: Insulating film 170: Contact plug 181: Etching mask 181a: Opening 185: Contact hole 187: Contact hole 189: Contact space 201: Recess 205: Metal pattern 215: Metal pattern 220: Memory cell array 223: Contact plug 230: Memory cell array 233: Contact plug 310: Semiconductor column 311: Insulator 313: Insulating core 315: Semiconductor layer 317: Insulating film 321: Electrode layer 323: Insulating film 330: Contact plug 331: Insulating film 333: Wiring 335: Contact plug 337: Contact plug 339: Contact plug 340: Contact plug 343: Bonding pad 345: Bonding pad 347: Contact plug 349: Contact plug 350: Bit line 351: Contact plug 370: Source line 410: Wiring 410B: Wiring 410C: Wiring 420: Wiring AG: Air gap CA: Contact area DR: Device area EG: Groove HUP: Lead-out part KR: Cutting area MC: Memory cell MH: Memory hole MP: Area NP: Second part PH: Contact hole R S: Diameter SH: Through hole ST: Slit STH: Contact hole WP: First part Ws: Full width

Claims

1. A method for manufacturing a semiconductor device, wherein a first device layer including a first semiconductor circuit is formed on a first substrate; a first surface of a second device layer including a second semiconductor circuit formed on a second substrate is bonded to the first surface of the first device layer; a first surface of a third device layer including a third semiconductor circuit formed on a third substrate is bonded to a second surface opposite to the first surface of the first device layer; a first connecting pad and a second connecting pad are directly bonded, wherein the first connecting pad is electrically connected to the first semiconductor circuit and formed on the first surface side of the first device layer; the second connecting pad is electrically connected to the second semiconductor circuit and formed on the first surface side of the second device layer; a third connecting pad and a fourth connecting pad are directly bonded, wherein the third connecting pad is electrically connected to the first semiconductor circuit and formed on the second surface side of the first device layer; and the fourth connecting pad is electrically connected to the third semiconductor circuit and formed on the first surface side of the third device layer. The first semiconductor circuit includes a first memory cell array, the second semiconductor circuit includes a control circuit for controlling the first memory cell array, the third semiconductor circuit includes a second memory cell array controlled by the control circuit, the first memory cell array includes a plurality of first conductive layers and a first memory pillar penetrating the plurality of first conductive layers, the second memory cell array includes a plurality of second conductive layers and a second memory pillar penetrating the plurality of second conductive layers, and the first connecting pad is electrically connected to one end of the first memory pillar.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein a fifth connecting pad electrically connected to the second semiconductor circuit is formed on the second surface of the third device layer, opposite to the first surface.

3. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the first connection pad, the second connection pad and the third connection pad comprise copper.

4. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the third connection pad is formed after removing at least a portion of the first substrate.

5. A method for manufacturing a semiconductor device as claimed in claim 4, wherein at least a portion of the first substrate is removed by wet etching.

6. The method of manufacturing a semiconductor device as claimed in claim 2, wherein the fifth connection pad is formed after removing at least a portion of the third substrate.

7. A method for manufacturing a semiconductor device as claimed in claim 1, wherein the first surface of the first device layer comprises: a silicon oxide film and the surface of the first connection pad.

8. A method for manufacturing a semiconductor device as claimed in claim 1, wherein the first surface of the first device layer and the first surface of the second device layer are bonded at a temperature of 300°C or higher and 400°C or lower.

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