Memory system

Abstract

A highly reliable memory system is provided. The memory system comprises non-volatile memory and a controller. The non-volatile memory includes: a plurality of first memory cells; a first word line connected to the first memory cells; a plurality of second memory cells; and a second word line connected to the second memory cells. The controller is configured to hold: first write data for writing to the plurality of first memory cells; and second write data for writing to the plurality of second memory cells. Furthermore, the controller is configured to calculate rewrite data based on the first write data and the second write data. Moreover, the non-volatile memory is configured to perform: a first write operation for writing to the plurality of first memory cells based on the first write data input from the controller; and a rewrite operation for writing a portion of the plurality of first memory cells based on the rewrite data input from the controller.

Description

Technical Field

[0001] This implementation relates to a memory system. Prior Technology

[0002] Memory systems are known to have non-volatile memory and a controller connected to the non-volatile memory and connectable to a host device. Various methods for writing to non-volatile memory are also known. Summary of the Invention

[0003] A highly reliable memory system is provided. One embodiment of the memory system is a non-volatile memory and a controller connected to the non-volatile memory. Non-volatile memory consists of multiple first memory cells, multiple first word lines connected to multiple first memory cells, multiple second memory cells, and multiple second word lines connected to multiple second memory cells. The controller is configured to be retainable: The first data to be written is used for writing the first memory cell of a complex number; and The second write operation is used to write data to the second memory cell of the complex number, which is performed after the first memory cell of the complex number has been written. Furthermore, the controller is configured to calculate the rewrite data based on the first and second write data. Furthermore, non-volatile memory is configured to be executable: The first write operation involves writing data to a plurality of first memory cells based on the first write data input from the controller; and The write operation writes a portion of the first memory cell of a complex array based on the write data input from the controller. Simple Explanation of the Diagram

[0004] [Figure 1] is a block diagram showing a non-volatile semiconductor device of a first embodiment. [Figure 2] is a block diagram of memory system 10. [Figure 3] is a circuit diagram showing an example of a three-dimensional NAND flash memory lattice array MCA. [Figure 4A] is a cross-sectional view of a portion of the three-dimensional NAND flash memory array MCA. [Figure 4B] is a cross-sectional view of region R1 shown in Figure 4A after enlarging it. [Figure 5] is a diagram showing an example of the region of critical voltage. [Figure 6] is a diagram showing the data encoding of 3-bit / cell. [Figure 7] is a flowchart showing the page readout process. [Figure 8] is a diagram showing the shift of the read voltage of the character line read from the page. [Figure 9] is a graph showing the distribution of critical values ​​when programming all bits simultaneously. [Figure 10] is a flowchart illustrating an example of the write order within a block BLK when all bits are programmed simultaneously. [Figure 11] is a diagram illustrating an example of the order of the selection character lines WL during programming when all bits are programmed simultaneously. [Figure 12] is a graph showing the distribution of critical values ​​after Foggy-Fine programming. [Figure 13] is a diagram showing the programming sequence of Foggy-Fine programming. [Figure 14] is a flowchart illustrating an example of the programming sequence of the entire BLK block in the first implementation. [Figure 15] is a diagram showing an example of the order of selection character lines WL during programming in the first embodiment. [Figure 16] is a graph showing the distribution of critical values ​​after programming in the first implementation. [Figure 17] is an example of the combination of the object cell and the critical value region of the write object in the third stage of programming in the first embodiment. [Figure 18] is a control flow diagram for writing data in the first embodiment. [Figure 19] is a graph showing the distribution of critical values ​​after programming in the second implementation. [Figure 20] is an example of the combination of the object cell and the critical value region of the write object in the third stage of programming in the second embodiment. [Figure 21] is a control flow diagram for writing data in the second embodiment. [Figure 22] is a graph showing the distribution of critical values ​​after programming in the third implementation. [Figure 23] is an example of the combination of the object cell and the critical value region of the write object in the third implementation as the third stage of programming. [Figure 24] is a control flow diagram for writing data in the third embodiment. [Figure 25] is a diagram illustrating an example of the order of the character lines WL during programming in the third embodiment. Implementation

[0005] Secondly, the memory system of each embodiment will be described in detail with reference to the drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the invention. Also, the following drawings are illustrative, and for the sake of explanation, some components may be omitted. Furthermore, common parts in the plurality of embodiments are marked with the same symbols, and explanations may be omitted.

[0006] Furthermore, in this specification, a predetermined direction parallel to the top surface of the substrate is referred to as the X direction, a direction parallel to the top surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the top surface of the substrate is referred to as the Z direction.

[0007] Furthermore, in this specification, the terms "upper" or "lower" are used with reference to the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction approaching the substrate along the Z direction is called "lower." Also, when referring to a certain configuration as "lower side" or "lower end," it means the surface or end of that configuration on the substrate side; when referring to it as "upper side" or "upper end," it means the surface or end of that configuration on the opposite side from the substrate. Also, the surface intersecting the X or Y direction is called "side surface," etc. [First Implementation Form] [constitute]

[0008] Figure 1 is a block diagram showing a non-volatile semiconductor device (non-volatile memory) according to a first embodiment. Figure 2 is a block diagram of the memory system 10. Figure 3 is a circuit diagram showing an example of a three-dimensional NAND flash memory array (MCA).

[0009] Non-volatile semiconductor memory devices (non-volatile memory) are memory devices that store data non-volatilely, such as NAND flash memory 40. In this embodiment, the non-volatile semiconductor memory device is described as a NAND flash memory 40 having a memory cell MC that can store 3 bits per memory cell MC, that is, a 3-bit / Cell (TLC: Triple Level Cell) NAND flash memory 40.

[0010] Non-volatile semiconductor memory devices are constructed and arrayed in three dimensions using memory cells (MCs). In this specification, a group of memory cells (MCs) that are commonly connected to a single word line (WL) and simultaneously selected via a single select gate line (SGD) is defined as a physical memory cell group (MG) (Figure 3). In this embodiment, the non-volatile semiconductor memory device is, for example, a 3-bit / cell NAND flash memory 40, and one physical memory cell group (MG) corresponds to three pages. The 3 bits of each memory cell (MC) correspond to these three pages respectively. In this specification, these three pages are referred to as the Lower page, Middle page, and Upper page.

[0011] The non-volatile semiconductor memory device shown in Figure 1, such as NAND flash memory 40, includes a NAND I / O interface (NIF), a control unit (CTU), a NAND flash memory array (MCA) (memory cell MC section), and a data latch unit (DL). The non-volatile semiconductor memory device is, for example, formed on a semiconductor substrate (e.g., a silicon substrate) and thus chip-shaped.

[0012] The control unit (CTU) controls the operation of the NAND flash memory 40 via the NAND I / O interface (NIF) based on instructions from the memory controller 30. Specifically, when a write request is received, the control unit (CTU) writes the requested data to a designated address on the NAND flash memory array (MCA). Furthermore, when a read request is received, the control unit (CTU) reads the requested data from the NAND flash memory array (MCA) and outputs it to the memory controller 30 via the NAND I / O interface (NIF).

[0013] The data latch DL acts as a buffer, temporarily storing data input from the memory controller 30 or data read from the NAND flash memory array MCA during write operations. Generally, the data latch DL is a data latch that requires adding 1 to the number of rows of bits that can be held in one cell. In this embodiment, since it is 3 bits / cell, it has 4 rows of data latches. The data latches are, for example, circuits composed of latch circuits connected to two inverter circuits. These 4 rows of data latches are referred to as data latches XDL, ADL, BDL, and CDL, respectively. Data latches XDL, ADL, BDL, and CDL can transfer data to each other. Furthermore, only data latch XDL is directly connected to the serial access controller SAC, allowing direct input and output of data. Data latch XDL constitutes a page buffer.

[0014] The control unit (CTU) includes an oscillator (OC), a sequence generator (SQC), an instruction user interface (CUIF), a voltage supply unit (VG), a column counter (CCT), and a serial access controller (SAC).

[0015] Furthermore, the NAND flash memory array MCA has a line decoder RD and a sense amplifier SA.

[0016] The NAND I / O interface (NIF) is a circuit used to send and receive I / O signals and control signals between the memory controller 30 and the memory controller 30.

[0017] The Instruction User Interface (CUIF) retrieves instructions and addresses from the instructions, addresses, and data received from the memory controller 30 via I / O signal lines based on control signals. The CUIF then passes the retrieved instructions and addresses to the sequence generator (SQC).

[0018] The oscillator OC is the circuit that generates the clock signal. The clock signal generated by the oscillator OC is supplied to the components including the sequence generator SQC.

[0019] The Sequence Controller (SQC) is a state machine driven by a clock signal supplied from the oscillator (OC). The SQC performs control over access to the NAND flash memory array (MCA). For example, the SQC issues instructions to control various internal voltages or operating timings based on instructions received from the instruction user interface (CUIF). Furthermore, the SQC supplies the block address and page address contained in the address received from the CUIF to the row decoder (RD). Additionally, the SQC supplies the column address contained in the address received from the CUIF to the column counter (CCT).

[0020] The voltage supply unit VG is a circuit that generates various internal voltages supplied to the word lines or the bit lines BL and supplies them to the row decoder RD or the sense amplifier SA. During programming or reading operations, the column counter CCT advances the column address sequentially according to the control signals supplied from the serial access controller SAC, with the column address provided by the sequence generator SQC as the leading column address.

[0021] During programming, a page buffer is a circuit that sequentially stores data received from the serial access controller (SAC) into the column address area specified by the column counter (CCT). During read operations, the page buffer sequentially transfers the stored data at the column addresses specified by the column address to the serial access controller (SAC).

[0022] The Serial Access Controller (SAC) is a circuit that, during programming, stores data received serially from the NAND I / O interface (NIF) in a page buffer according to the bit width of each I / O signal line. Furthermore, during read operations, the SAC transmits data received serially from the page buffer to the NAND I / O interface (NIF) according to the bit width of each I / O signal line.

[0023] The row decoder RD is a circuit that decodes the block address and page address during programming and reading operations to select the word line WL corresponding to the page containing the access target in the block BLK. Then, each row decoder RD applies appropriate voltages to the selected word line WL and the non-selected word line WL.

[0024] The sensing amplifier SA is a circuit that, during programming, transfers the corresponding data stored in the page buffer to the memory cell transistor MT, and during readout, senses the data read from the select word line to the bit line BL and stores the data in the page buffer. The data stored in the page buffer is transferred to the memory controller 30 via the serial access controller SAC and the NAND I / O interface NIF.

[0025] Figure 2 shows a memory system 10 utilizing NAND flash memory 40. The memory controller 30 controls the writing of data to the NAND flash memory 40 according to write commands from the host 20. The memory controller 30 also controls the reading of data from the NAND flash memory 40 according to read commands from the host 20. The memory controller 30 includes RAM 31 (Random Access Memory), ROM 32 (Read Only Memory), a processor 33, a host interface 34, an ECC circuit 35 (Error Check and Correct), and a memory interface 36. RAM 31, ROM 32, processor 33, host interface 34, ECC circuit 35, and memory interface 36 are interconnected via internal buses.

[0026] The host interface 34 outputs instructions and user data (written data) received from the host 20 to the internal bus. Furthermore, the host interface 34 is a circuit that transmits user data read from the NAND flash memory 40 and responses from the processor 33 to the host 20.

[0027] The memory interface 36 is a circuit that controls the processing of writing user data to NAND flash memory 40 and reading data from NAND flash memory 40 according to the instructions of processor 33.

[0028] Processor 33 provides overall control over memory controller 30. Processor 33 may be, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). Processor 33 receives instructions from host 20 via host interface 34 and performs control according to those instructions. For example, processor 33 instructs memory interface 36 to write user data and parity data to NAND flash memory 40 according to instructions from host 20. Also, processor 33 instructs memory interface 36 to read user data and parity data from NAND flash memory 40 according to instructions from host 20. Processor 33 determines the storage area (memory area) on NAND flash memory 40 for user data stored in RAM 31. User data is stored in RAM 31 via internal buses.

[0029] Processor 33 determines the memory region for data in page units (page data) to be written. In this specification, user data in one page to be stored in NAND flash memory 40 is defined as cell data.

[0030] Cell data is typically encoded and stored as codewords in NAND flash memory 40. In this embodiment, encoding is not mandatory. The memory controller 30 may also store cell data in NAND flash memory 40 without encoding, but in this embodiment, encoding is shown as an example. When the memory controller 30 does not encode, the page data is identical to the cell data. Furthermore, a codeword can be generated based on one cell data, or a codeword can be generated based on the segmentation data of the divided cell data. Also, a codeword can be generated using multiple cell data.

[0031] Processor 33 determines the memory region of NAND flash memory 40 for each cell of data to be written to. Physical addresses are allocated within the memory regions of NAND flash memory 40. Processor 33 uses physical addresses to manage the memory regions where cell data is written to. Processor 33 instructs memory interface 36 to specify the determined memory region (physical address) to write user data to NAND flash memory 40. Processor 33 manages the mapping between logical addresses (logical addresses managed by host 20) and physical addresses for user data. When processor 33 receives a read instruction containing a logical address from host 20, it specifies the physical address corresponding to the logical address, instructs memory interface 36 to specify the physical address, and reads the user data.

[0032] ECC circuit 35 is a circuit that encodes user data stored in RAM 31 to generate codewords. ECC circuit 35 also decodes codewords read from NAND flash memory 40. Figure 2 shows an example configuration where the memory controller 30 includes both ECC circuit 35 and memory interface 36; however, ECC circuit 35 may also be embedded within memory interface 36 or within NAND flash memory 40.

[0033] RAM31 is temporarily stored before user data received from host 20 is written to NAND flash memory 40, or before data read from NAND flash memory 40 is transferred to host 20. RAM31 is a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0034] When a write request is received from host 20, memory system 10 operates as follows. Processor 33 temporarily stores the write data in RAM 31. Processor 33 reads the data stored in RAM 31 and inputs it to ECC circuit 35. ECC circuit 35 encodes the input data and inputs the codeword to memory interface 36. Memory interface 36 writes the input codeword to NAND flash memory 40.

[0035] When a read request is received from host 20, memory system 10 operates as follows. Memory interface 36 inputs the codeword read from NAND flash memory 40 to ECC circuit 35. ECC circuit 35 decodes the input codeword and stores the decoded data in RAM 31. Processor 33 transmits the data stored in RAM 31 to host 20 via host interface 34. Alternatively, NAND flash memory 40 may be connected to multiple chips, and NAND flash memory 40 and memory interface 36 may also be connected via an interface chip that carries relay data and control signals.

[0036] In addition, the memory controller 30 shown in Figure 2 is one example. Its internal bus can be segmented or hierarchical, or connected to additional functional blocks, etc. Other derivative forms are also possible.

[0037] Figure 3 shows the circuit configuration of one of the multiple blocks BLK within a three-dimensional NAND flash memory array MCA. The other blocks BLK in the NAND flash memory array MCA have the same circuit configuration as shown in Figure 3.

[0038] As shown in Figure 3, the block BLK has, for example, four fingers FNG (FNG0~FNG3). Each finger FNG contains a plurality of NAND string words NS. Each NAND string word NS has, for example, eight memory transistors MT (MT0~MT7) connected in series, and select transistors ST1, ST2. In this specification, each finger FNG is sometimes referred to as a string St. Furthermore, the number of memory transistors MT within a NAND string word NS is not limited to eight.

[0039] The memory cell transistor MT is configured such that its current path is connected in series between select transistors ST1 and ST2. The current path of memory cell transistor MT7 on one end of this series connection is connected to one end of the current path of select transistor ST1, and the current path of memory cell transistor MT0 on the other end is connected to one end of the current path of select transistor ST2.

[0040] The gates of the select transistors ST1 for each of the fingers FNG0 to FNG3 are respectively connected to the select gate lines SGD0 to SGD3. On the other hand, the gates of the select transistors ST2 are connected to the same select gate line SGS across the multiple fingers FNG. Furthermore, the control gates of the memory cell transistors MT0 to MT7 located within the same block BLK are respectively connected to the word lines WL0 to WL7. That is, the word lines WL0 to WL7 and the select gate line SGS are connected across the multiple fingers FNG0 to FNG3 within the same block BLK; conversely, even within the same block BLK, the select gate line SGD is independent for each finger FNG0 to FNG3.

[0041] The control gate electrodes of the memory transistors MT0~MT7 constituting the NAND string word NS are respectively connected to word lines WL0~WL7. Furthermore, within each NAND string word NS in the same finger FNG, the i-th memory transistor MTi (where i is an integer from 0 to 7) is also connected via the i-th word line WLi. That is, the control gate electrodes of the memory transistors MTi in the same row within block BLK are connected to the same word line WLi. Each NAND string word NS is connected to both word lines WLi and bit lines BL. Each memory cell MC within each NAND string word NS can be identified using the addresses of the identification word lines WLi, the selection gate lines SGD0~SGD3, and the identification bit line BL.

[0042] As described above, the data in memory cells MC (memory cell transistors MT) located within the same block BLK is erased together. On the other hand, data reading and writing are performed in physical memory cell groups MG. One physical memory cell group MG is connected to one word line WLi and contains multiple memory cells MC belonging to one finger FNG. The memory controller 30 writes (programs) data in units of all memory cells MC connected to one word line WL within one finger FNG. Therefore, the unit of data volume programmed by the memory controller 30 is 3 bits × (number of bit lines BL). This 3-bit unit is called a page.

[0043] During read and program operations, one word line WLi and one select gate line SGD are selected according to the physical address, and the physical memory cell group MG is selected. Additionally, in this manual, writing data into the memory cell MC as needed is referred to as programming.

[0044] Figure 4A is a cross-sectional view of a portion of the three-dimensional NAND flash memory array MCA. Figure 4B is a cross-sectional view of an enlarged region R1 shown in Figure 4A. As shown in Figure 4A, a plurality of NAND serial words NS are formed on the p-well region P-well. That is, a plurality of wiring layers 333 for the Select Gate Line (SGS), a plurality of wiring layers 332 for the Word Line (WL), and a plurality of wiring layers 331 for the Select Gate Line (SGD) are formed on the p-well region P-well. Furthermore, memory vias are formed that penetrate these wiring layers 331, 332, and 333 to reach the p-well region P-well.

[0045] As shown in Figure 4B, a block insulating film 335, a charge storage layer 336, and a gate insulating film 337 are sequentially formed on the side of the memory hole, and a conductive film 338 is further embedded in the memory hole. The conductive film 338 functions as a current path for the NAND serial number NS, forming a channel area when the memory cell transistor MT and the select transistors ST1 and ST2 are operated. In addition, as shown in Figure 4B, an insulating layer 101, such as silicon oxide (SiO2), may also be provided between the wiring layers 331, 332, and 333.

[0046] In each NAND serial word NS, a select transistor ST2, a complex number of memory lattice transistors MT, and a select transistor ST1 are sequentially stacked on the p-well region. A wiring layer is formed at the upper end of the conductive film 338 to function as a bit line BL.

[0047] Furthermore, an n+ type impurity diffusion layer 350 and a p+ type impurity diffusion layer 351 are formed within the surface of the p-well region. A contact plug 340 is formed on the n+ type impurity diffusion layer, and a wiring layer that functions as the source line SL is formed on the contact plug 340. Additionally, a contact plug 339 is formed on the p+ type impurity diffusion layer 351, and a wiring layer that functions as the well wiring CPWELL is formed on the contact plug 339.

[0048] The configuration shown in Figure 4A above involves multiple finger FNGs arranged in the depth direction of the paper in Figure 4A. One finger FNG is formed by a set of multiple NAND string words NS arranged in a row in the depth direction. Other finger FNGs are formed, for example, in the left and right directions of Figure 4A. Figure 3 illustrates four finger FNGs (FNG0 to FNG3), but Figure 4A shows an example of three finger FNGs arranged between contact plugs 339 and 340.

[0049] Furthermore, this embodiment is not only applicable to three-dimensional structures, but also to two-dimensional memory lattice structures (MC). [Critical value distribution of non-volatile memory]

[0050] Figure 5 is a diagram illustrating an example of a region with a critical voltage. The horizontal axis of Figure 5 represents the critical voltage, and the vertical axis represents the number of memory cells. Figure 5 shows an example of the critical voltage distribution for a 3-bit / cell non-volatile memory. In non-volatile memory, information is stored based on the amount of charge stored in the charge accumulation layer 336 of the memory cell MC. Each memory cell MC has a critical voltage based on the amount of charge. Furthermore, a region (critical voltage region) is formed where the multiple data values ​​stored in the memory cell MC correspond to multiple critical voltages.

[0051] The mountain-shaped distribution DS0, DS1, DS2, DS3, DS4, DS5, DS6, and DS7 in Figure 5 represent the critical value distributions of each of the eight critical voltage regions S0 to S7. Thus, each memory cell MC has a critical value distribution divided by seven boundaries. In this embodiment, the region where the critical voltage is below voltage Vr1 is called region S0, the region where the critical voltage is above voltage Vr1 and below voltage Vr2 is called region S1, the region where the critical voltage is above voltage Vr2 and below voltage Vr3 is called region S2, and the region where the critical voltage is above voltage Vr3 and below voltage Vr4 is called region S3. Furthermore, in this embodiment, the region with a critical voltage greater than voltage Vr4 and below voltage Vr5 is designated as region S4; the region with a critical voltage greater than voltage Vr5 and below voltage Vr6 is designated as region S5; the region with a critical voltage greater than voltage Vr6 and below voltage Vr7 is designated as region S6; and the region with a critical voltage greater than voltage Vr7 is designated as region S7. The critical value distributions corresponding to regions S0, S1, S2, S3, S4, S5, S6, and S7 are respectively designated as distributions DS0, DS1, DS2, DS3, DS4, DS5, DS6, and DS7. Voltages Vr1 to Vr7 are the critical voltages that form the boundaries of each region.

[0052] In non-volatile memory, complex data values ​​are assigned to complex critical value regions (i.e., critical value distributions) within memory cells MC. This correspondence is called data encoding. This data encoding is pre-set. During data writing (programming), charge is injected into the memory cells MC according to the data encoding, making them fall within the critical value regions corresponding to the remembered data values. Furthermore, during reading, a readout voltage is applied to the memory cells MC, and the data is determined based on whether the critical value of the memory cells MC is lower or higher than the readout voltage. When the critical value voltage is lower than the readout voltage, it is in an "erased" state, and the data value is defined as "1". When the critical value voltage is higher than the readout voltage, it is in a "programmed" state, and the data is defined as "0".

[0053] Figure 6 is a diagram illustrating the 3-bit / cell data encoding. In this embodiment, the eight threshold distributions (threshold regions) shown in Figure 5 correspond to the eight data values ​​of the 3-bit array. The relationship between the threshold voltages and the data values ​​corresponding to the bits in the Upper, Middle, and Lower pages is as follows. • The memory cell MC, located within region S0, is in the state of remembering "111" when the critical voltage is located. • The memory cell MC, located within region S1, stores the state "110". • The memory cell MC, located within region S2, stores the state "100". • The memory cell MC, located within region S3, stores the state "000". • The memory cell MC, located within region S4, stores the state "010". • The memory cell MC, located within region S5, stores the state "011". • The memory cell MC, located within region S6, stores the state "001". • The memory cell MC, located within region S7, is in the state of remembering "101" when the critical voltage is located.

[0054] Thus, for each critical voltage region, the state of 3 bits of data in each memory cell MC can be represented. Furthermore, in the unwritten state of the memory cell MC (the "erased" state), the critical voltage of the memory cell MC is located within region S0. And, in the data encoding shown here, only 1 bit of data changes between any two adjacent states, so that the data "111" is stored in region S0 and the data "101" is stored in region S1. Thus, the encoding shown in Figure 6 is Gray code, where only 1 bit of data changes between any two adjacent regions.

[0055] In the encoding of this embodiment shown in Figure 6, the critical voltage that serves as the boundary for determining the bit values ​​of each page is as follows. • The critical voltages that serve as the boundaries for determining the bit values ​​of the Upper page are voltages Vr3 and Vr7. • The critical voltages that serve as the boundaries for determining the bit values ​​of the Middle page are voltages Vr2, Vr4, and Vr6. • The critical voltages that serve as the boundaries for determining the bit values ​​of the Lower page are voltages Vr1 and Vr5.

[0056] Thus, the critical voltage value used to determine the boundary of the bit value (hereinafter referred to as the boundary number) is 2, 3, and 2 in the Lower page, Middle page, and Upper page, respectively. This encoding, using the boundary number of each Lower page, Middle page, and Upper page, is called 2-3-2 encoding.

[0057] In this embodiment, the 2-3-2 encoding is used as an example for explanation. The correspondence between the complex critical value regions of the memory cell (MC) and the data values ​​can be represented using other data encodings, but for simplicity, all cases are omitted. In this embodiment, regardless of the data encoding used, a data encoding with a small deviation in the number of boundaries allocated to each page is generally chosen. In this case, since the deviation in the number of boundaries between pages is small, the result is a smaller deviation in the bit error rate between pages. This is because most bit errors are caused by changes in the critical value in adjacent critical value regions; the more boundaries a page has, the more bit errors it will have. This means that even if the error rate of the memory cell (MC) is the same, the ECC correction capability necessary to correct page data errors must be strengthened. This helps improve the response performance of the memory system 10 to write or read requests from the host 20, and reduces cost and power consumption degradation. Furthermore, the deviation in read speed caused by the deviation in the number of boundaries will also be smaller. [Read the action]

[0058] Next, the page readout processing will be explained. If the data is encoded according to the 2-3-2 data encoding shown in Figure 6, since there are two boundaries between the critical value states of the Lower page data change, the control unit CTU (Figure 1) determines the data based on which of the three ranges the critical value falls within that boundary. For example, when the critical value voltage is lower than voltage Vr1, the control unit CTU controls the output to "1" as the data for memory cell MC. Similarly, when the critical value voltage is higher than voltage Vr5, the control unit CTU controls the output to "1" as the data for memory cell MC. Furthermore, when the critical value voltage is lower than voltage Vr5 and higher than voltage Vr1, the control unit CTU controls the output to "0" as the data for memory cell MC. Since there are three boundaries between the critical value states of the physical Middle page data change, the control unit CTU determines the value of the readout data as "0" or "1" based on which of the four ranges the critical value falls within. Since there are two boundaries between the critical value states of the data change on the Upper page, the control unit (CTU) determines whether the value of the read data is "0" or "1" based on which of the three ranges the critical value falls within.

[0059] The following describes the specific processing procedure for page reading. Figure 7 is a flowchart showing the page reading processing procedure.

[0060] As shown in Figure 7, the control unit CTU selects the read page (step S101).

[0061] When the read page is a Lower page, the Control Unit (CTU) first reads it using voltage Vr1 (step S102). Next, the Control Unit (CTU) reads it using voltage Vr5 (step S103). Then, based on the read results at voltage Vr1 and voltage Vr5, the Control Unit (CTU) determines the value of the read data to be either "0" or "1" (step S104). The Control Unit (CTU) then transfers this page of data from the S / A to the data latch XDL (step S105).

[0062] Furthermore, as mentioned above, the reading of the Lower page is performed in the order of the lowest read voltage, i.e., voltage Vr1, voltage Vr5, but it can also be performed in the reverse order, i.e., voltage Vr5, voltage Vr1. This situation is shown in Figures 8(a) and 8(b) respectively.

[0063] When the read page is a Middle page, the control unit (CTU) reads it using three read voltages: Vr2, Vr4, and Vr6. The control unit (CTU) determines the value of the read data to be either "0" or "1" (step S115) based on the results of reading the critical voltage at Vr2 (step S112), the critical voltage at Vr4 (step S113), and the critical voltage at Vr6 (step S114). The control unit (CTU) then transfers this page of data from the S / A to the data latch XDL (step S116).

[0064] Furthermore, as mentioned above, the reading of the Middle page is performed in the order of low read voltage, i.e., voltage Vr2, voltage Vr4, voltage Vr6. However, it can also be performed in the reverse order of high read voltage, i.e., voltage Vr6, voltage Vr4, voltage Vr2. This situation is shown in Figures 8(c) and 8(d) respectively.

[0065] When the read page is an Upper page, the control unit CTU reads it using two read voltages. These voltages are the Upper page read voltages Vr3 and Vr7. Furthermore, the control unit CTU determines the value of the read data to be either "0" or "1" (step S124) based on the results of reading the critical voltage at voltage Vr3 (step S122) and the results of reading the critical voltage at voltage Vr7 (step S123). The control unit CTU then transfers this page of data from the S / A to the data latch XDL (step S125).

[0066] Furthermore, as mentioned above, the reading of the Upper page is performed in the order of lower read voltages, i.e., voltage Vr3, voltage Vr7. However, it can also be performed in the reverse order of higher read voltages, i.e., voltage Vr7, voltage Vr3. This situation is shown in Figures 8(e) and 8(f) respectively.

[0067] Furthermore, as another example, the read sequence can also be as shown in Figure 8(g) or Figure 8(h). This read method is based on the premise of continuously outputting Lower, Middle, and Upper pages to the outside, while the internal read performs all read voltages. In this case, the internal read is controlled in the order of gradually increasing from the lowest read voltage (Figure 8(g)) or gradually decreasing from the highest read voltage (Figure 8(h)), thereby reducing the voltage variation amplitude of the character line WL and shortening the voltage transition time, resulting in the advantage of high-speed read. External output can be performed after the physical Lower page is read (i.e., the voltage Vr5 is read). In addition, since it is necessary to maintain 3 pages of page data simultaneously, 3 data latches ADL, BDL, and XDL are needed to temporarily store the page read data. [Write action]

[0068] Secondly, the programming is explained. The control unit (CTU) of the non-volatile memory controls the programming of the NAND flash memory array (MCA) according to the data encoding shown in Figure 6.

[0069] In the case of a 3D memory cell (MC), if miniaturization has not yet progressed and the spacing between adjacent MCs is wide in a previous generation, interference between adjacent MCs is minimal. In this situation, a common approach is to program all bits simultaneously (or all pages simultaneously if the bits are allocated to different pages). Based on the data from all bits, the position of the eight critical values ​​is determined, and programming proceeds from the region S0 where the state has been eliminated to the determined region. Interference between adjacent MCs will be discussed in detail later. [A technique for programming all bits simultaneously]

[0070] Figure 9 shows the critical value distribution when all bits are programmed simultaneously. Figure 9(T1) represents the critical value distribution of the initial state before programming and the elimination state, while Figure 9(T2) represents the critical value distribution after programming.

[0071] As shown in Figure 9(T1), the entire memory cell MC of the NAND flash memory array MCA is in an unwritten state ("erased" state) and is distributed in region S0. The control unit CTU of the non-volatile memory, as shown in Figure 9(T2), during programming, according to the bit values ​​written (memorized) to the Lower page, Middle page, and Upper page, for each memory cell MC, either maintains the distribution in region S0, or injects charge to move the distribution to regions S1 to S7, which are higher than region S0.

[0072] Specifically, when the bit values ​​written to the Lower, Middle, and Upper pages are all "1", the control unit CTU does not inject charge. When any of the bit values ​​written to the Lower, Middle, and Upper pages is "0", the control unit CTU is programmed to inject charge and move the threshold voltage to a high value.

[0073] That is, when the bit value written to the Lower, Middle, and Upper pages is "110", the distribution of the critical voltage is shifted to region S1; when the bit value written to the Lower, Middle, and Upper pages is "100", the distribution of the critical voltage is shifted to region S2; when the bit value written to the Lower, Middle, and Upper pages is "000", the distribution of the critical voltage is shifted to region S3; and when the bit value written to the Lower, Middle, and Upper pages is "000", the distribution of the critical voltage is shifted to region S3. When the bit value is “010”, the distribution of the critical voltage is moved to region S4. When the bit value written to the Lower, Middle, and Upper pages is “011”, the distribution of the critical voltage is moved to region S5. When the bit value written to the Lower, Middle, and Upper pages is “001”, the distribution of the critical voltage is moved to region S6. When the bit value written to the Lower, Middle, and Upper pages is “101”, the distribution of the critical voltage is moved to region S7.

[0074] Alternatively, programming is typically performed by applying one or more programming voltage pulses to the character line WL. During the application of multiple programming voltage pulses, the voltage value increases in stages. After each programming voltage pulse, a readout, known as a verification readout, is performed to confirm whether the memory cell MC has moved beyond a critical threshold level. By repeating this application and readout, the critical value of the memory cell MC can be moved to within a predetermined range of critical value distributions.

[0075] Figure 10(a) is a flowchart illustrating an example of the programming order of a single block BLK when all bits are programmed simultaneously. This flowchart illustrates an example of the programming order when there are four strings St within the block BLK. Hereinafter, there are cases where the four strings St are referred to as strings Stj using string numbers j (j is an integer from 0 to 3). Furthermore, hereafter, a single block BLK has n+1 character lines WLi, represented by character line numbers i (i is an integer from 0 to n) as character lines WL0 to WLn (n is a natural number). The memory controller 30 programs the character lines WLi in a continuous sequence; therefore, programming is performed as a whole, with the entirety of a certain character line WLi (here, the block BLK) as the overall programming order.

[0076] Once writing begins, the control unit CTU (Fig. 1), according to the instructions of the processor 33 (Fig. 2), sequentially selects character lines WLi and strings St in a predetermined order, as shown in Fig. 10(a), and continuously performs programming. Character lines WL are selected sequentially from the smallest character line number i, as shown in Fig. 11. Furthermore, the multiple physical memory cell groups MG corresponding to the same character line number i are selected sequentially from the smallest string number j. Once all strings St0 to St3 (all physical memory cell groups MG) corresponding to one character line WLi have been programmed, the character line WLi+1 corresponding to the next character line number i+1 is selected. In the following description, the programming operation of the control unit CTU is based on instructions from the processor 33, but for the sake of simplicity, the description of instructions from the processor 33 is omitted.

[0077] In the example shown in Figure 10(a), the control unit CTU first programs the string St0 of character line WL0 (step S201). Next, the control unit CTU programs the string St1 of character line WL0 (step S202). Next, the control unit CTU programs the string St2 of character line WL0 (step S203). Next, the control unit CTU programs the string St3 of character line WL0 (step S204). Next, the control unit CTU programs the string St0 of character line WL1 (step S205). Next, the control unit CTU programs the string St1 of character line WL1 (step S206). Similarly, the control unit CTU processes the last character line in block BLK according to the order of the arrows in Figure 10(a) (steps S207-S212).

[0078] In addition, Figures 10(a) and 11 illustrate the case where the string St in block BLK is 4 characters long, but the string St in block BLK can also be 3 or less, or it can be 5 or more characters long.

[0079] Figure 10(b) is a sub-flowchart illustrating the writing procedure for a single word line WL in the case of simultaneous programming of all bits. In this programming, firstly, a Lower page data input start instruction is input from the memory controller 30 (Figure 2) to the NAND flash memory 40. Then, Lower page data is input from the memory controller 30 to the data latch XDL of the NAND flash memory 40 (step S301). Once the control unit CTU (Figure 1) detects the end of data input from the external source, it transfers the data in the data latch XDL to the data latch ADL (step S302).

[0080] Next, an input start command for Middle page data is input from the memory controller 30 to the NAND flash memory 40. Then, Middle page data is input from the memory controller 30 to the data latch XDL of the NAND flash memory 40 (step S303). Once the control unit CTU detects the end of data input from the external source, it transfers the data in the data latch XDL to the data latch BDL (step S304).

[0081] Next, an input start command for Upper page data is input from the memory controller 30 to the NAND flash memory 40. Then, Upper page data is input from the memory controller 30 to the XDL of the NAND flash memory 40 (step S305). Once the control unit CTU detects the end of data input from the external source, it transfers the data in the XDL to the CDL (step S306).

[0082] Up to this point, the data for the Lower, Middle, and Upper pages necessary for programming the character line WL has been transferred to the data latches ADL, BDL, and CDL, respectively, completing the data preparation. Next, a programming execution instruction is input from the memory controller 30 to the NAND flash memory 40, thereby putting the chip into a busy state. Then, based on the combination of the previously input Lower, Middle, and Upper page data, the programming target Vth (critical voltage) for each memory cell MC is determined (step S307). Afterwards, the determined Vth is used to write three pages of data.

[0083] During data writing, one or more programming voltage pulses are applied (step S308). The first programming voltage is the voltage of the initial value. Subsequent programming voltages can also be the voltage of the initial value, but only increased by a predetermined voltage range. Then, data is read out (verified) to confirm whether the memory cell MC has moved beyond the critical value boundary level (step S309). The readout level at this time is a predetermined level.

[0084] Furthermore, it is confirmed whether the number of failure bits in the data of each memory critical value region is less than the standard (judgment benchmark) (step S310). When the number of failure bits is greater than the standard, the process from applying the programming pulse to judging the standard is repeated (steps S308 to S310). Then, if the number of failure bits is less than the standard, the chip is ready. By repeatedly applying, reading, and confirming in this way, the critical value of the memory cell MC can be moved within the range of the predetermined critical value distribution.

[0085] Furthermore, the predetermined read level after the programming voltage pulse is applied during writing can also differ slightly from the read level after writing, ideally being higher than the read level after writing. This is to establish a margin for threshold determination during the read operation after writing. Then, if the number of failure bits in all threshold regions is less than the standard, the chip is considered ready. [Interference between adjacent memory cells]

[0086] Here, we explain the interference between adjacent memory cells. The first type of interference occurs when the charge in the charge accumulation layer 336 (Fig. 4B) of a single memory cell MC disturbs the electric field of adjacent memory cell MCs. As a result, noise that causes the threshold voltage to fluctuate is generated when reading adjacent memory cell MCs. When programming and verification are performed under a certain electric field condition, if adjacent memory cell MCs are programmed with different charges after programming, the threshold voltage will fluctuate towards a higher direction under the influence of the electric field, thus degrading readout accuracy. Typically, if, after programming, a memory cell MC adjacent to a memory cell MC with a low threshold voltage distribution is programmed towards a higher threshold voltage distribution, the threshold voltage will rise after programming the adjacent memory cell MCs. This interference between adjacent memory cells becomes more significant as memory device manufacturing technology becomes miniaturized and the cell spacing shrinks. Moreover, this interference between adjacent memory cells mainly occurs between adjacent memory cell MCs on different word lines connected to the same bit line BL.

[0087] In addition, there is a second type of interference between adjacent memory cells caused by a different physical phenomenon: charge coupling between adjacent cells. If the amount of charge stored in the charge accumulation layer 336 of a memory cell MC differs from that stored in the charge accumulation layer 336 of an adjacent memory cell MC, i.e., there is a difference in the critical voltage, then in the boundary region between adjacent cells, the charges will gradually couple and neutralize over time after programming. This becomes noise that causes the critical voltage to fluctuate, thus leading to a deterioration in read accuracy. Typically, when a memory cell MC with a high critical voltage distribution is adjacent to a memory cell MC with a low critical voltage distribution, the critical voltage of the memory cell MC with the high critical voltage distribution will decrease, while the critical voltage of the memory cell MC with the low critical voltage distribution will increase. In particular, the decrease in critical voltage is especially large for the memory cell MC with the high critical voltage distribution, because other factors such as leakage of the charge injected during programming over time can also cause the critical voltage to decrease. This interference between adjacent memory cells has become more pronounced as memory device manufacturing technology has become more refined and the spacing between memory cells has decreased. Moreover, this interference between adjacent memory cells also mainly occurs between adjacent memory cells MC of different word lines connected to the same bit line BL. [Foggy-Fine Programming]

[0088] Interference between adjacent memory cells can be mitigated by reducing the difference in electric field conditions of memory cells MC during programming and verification, and during readout after adjacent memory cells MC have been programmed. As a method to reduce inter-cell interference between adjacent memory cells MC of different word lines WL connected to the same bit line BL, a programming method (Foggy-Fine programming) can be employed, which uses multiple programming stages, such as two programming stages (hereinafter also referred to as stages), to gradually inject charge into the charge accumulation layer 336 of the memory cell MC. In this Foggy-Fine programming, after writing to the memory cell MC in the first stage (Foggy stage), writing to adjacent cells is performed, and then writing is performed in the second stage (Fine stage) back to the original memory cell MC. Each stage in this case is a unit of programming execution; programming of a memory cell MC corresponding to one word line WLi is completed by executing two programming stages.

[0089] Both the first and second programming stages use eight critical value regions for programming. The critical value distribution at the end of the first programming stage has a wider width than the critical value distribution of the final data encoding critical value region. That is, in the Foggy stage, Foggy writing is performed. This Foggy stage programming requires all three pages of input data. Because the critical value distribution after the Foggy stage programming is an intermediate state where adjacent distributions overlap, the data cannot be read. In the second stage, the Fine stage programming, the critical value region after the Foggy stage programming is moved to the critical value region of the final data encoding. That is, in the Fine stage, Fine writing is performed. This Fine stage programming also requires all three pages of input data. Because the critical value distribution after the Fine stage programming is a final state where adjacent distributions are separated, the data can be read after the Fine stage programming.

[0090] Assuming significant interference between adjacent memory cells, the programming sequence is implemented using Foggy-Fine programming. Figure 12 shows the critical value distribution after Foggy-Fine programming. Figure 12(T1) represents the critical value distribution of the initial state before programming, i.e., the eliminated state. Figure 12(T2) represents the critical value distribution after the first stage of programming (Foggy programming). Figure 12(T3) represents the critical value distribution after the second stage of programming (Fine programming).

[0091] As shown in (T1) of Figure 12, the critical voltage of the full memory cell MC of the NAND flash memory array MCA is located in region S0 in the unwritten state ("erased" state).

[0092] As shown in Figure 12 (T2), the control unit (CTU) of the NAND flash memory 40, during the first-stage programming, according to the bit values ​​written (memorized) to the Lower, Middle, and Upper pages, maintains the critical value distribution in region S0 for each memory cell MC, or injects charge to move the distribution to regions S1 to S7, which are higher than region S0. The correspondence between the written bit values ​​and the critical value regions is as described above. Here, in regions S1 to S7, the width of the critical value distribution is roughly expanded during programming, making the critical value voltage slightly lower.

[0093] Therefore, the memory cell MC is programmed into 8 levels based on the data from the Lower, Middle, and Upper pages. However, due to the wide width of the threshold distribution, it overlaps with other adjacent threshold distributions, making it impossible to read the data. Nevertheless, since the threshold distribution after this first-stage programming does not require fine-tuning, it allows for high-speed programming.

[0094] Furthermore, as shown in Figure 12 (T3), during the 2nd stage programming, data writing requires data from all pages of the Lower, Middle, and Upper layers. Moreover, the control unit (CTU) of the NAND flash memory 40 is ultimately programmed into eight critical value regions after the 2nd stage programming, with the critical value distribution separated. This makes it possible to read all page data. During the 2nd stage programming, the greater the change in the critical voltage of the memory cell MC from the end of the 1st stage programming, the greater the interference between the first adjacent cells. Therefore, it is ideal for the change in the critical voltage from the 1st stage to the 2nd stage to be small.

[0095] Furthermore, typical writing (programming) of memory cells MC is performed by applying one or more programming voltage pulses to the corresponding character line WL. After each programming voltage pulse is applied, a readout is performed to confirm whether the memory cell MC has moved beyond the critical threshold level. By repeating this application and readout, the critical voltage of the memory cell MC can be moved within a predetermined region S1 to S7. The critical voltage of the corresponding memory cell MC is determined from the data of the entire page of the write target, and the voltage value of multiple programming pulses is gradually increased during writing, thereby forming the determined critical voltage. Memory cells MC that have reached the target critical voltage are excluded from the write target.

[0096] Furthermore, the control unit (CTU) does not perform the first and second stages of programming consecutively for the multiple physical memory cell groups (MG) corresponding to one character line (WLi). In order to reduce the impact of interference between adjacent memory cells, programming is performed in a non-continuous order across the multiple character lines (WLi).

[0097] Figure 13 is a diagram illustrating the programming sequence of Foggy-Fine programming. The example shown in Figure 13 illustrates the programming sequence where four strings, St0~St3, are connected to the word lines WLi within each block BLK of the NAND flash memory 40. In the example shown in Figure 13, programming is performed in two stages to minimize interference between the first adjacent memory cells.

[0098] If writing begins, the control unit (CTU) (Figure 1) performs each programming stage across character lines WLi in a predetermined, non-continuous order. That is, the 1st and 2nd stages for the same character line WL are not executed consecutively. Instead, after programming the 1st stage for all physical memory cell groups MG corresponding to a certain character line WLi, the 2nd stage is performed for all physical memory cell groups MG corresponding to the previous character line WLi-1. If programming to the 2nd stage is completed for a certain character line WLi, and then programming the 1st and 2nd stages consecutively for the adjacent character line WLi+1, the fluctuation of the threshold voltage in the multiple memory cells MC corresponding to the character line WLi becomes larger. Furthermore, if the fluctuation of the threshold voltage of the adjacent character line WLi+1 is large, the inter-cell interference between adjacent memory cells between character lines WLi and WLi+1 increases.

[0099] To reduce interference between adjacent memory cells of word lines WL, after word line WLi completes programming to the 2nd stage, it is effective to suppress the critical voltage fluctuations of the complex number of memory cells MC corresponding to word line WLi caused by the programming of the adjacent word line WLi+1. If the sequence is as shown in Figure 13, since the programming stage of the adjacent word line WLi+1 after a certain word line WLi completes programming to the 2nd stage is only the 2nd stage, the fluctuations of the critical voltage of the complex number of memory cells MC corresponding to word line WLi can be appropriately suppressed.

[0100] Additionally, Figure 13 illustrates the case where the string St within block BLK has 4 characters, but the string St within block BLK can have 3 or fewer characters, or it can have 5 or more characters.

[0101] Additionally, for example, in the example shown in Figure 4A, among the complex character lines WL arranged in the Z direction, the adjacent character line WL corresponding to the kth character line WL (k is a natural number) counted from one side is either the (k-1)th character line WL or the (k+1)th character line WL counted from one side. [Rewrite action]

[0102] Next, the write operation will be explained. In the first implementation, Foggy-Fine programming is used to counteract interference between the first adjacent memory cells, and further, the write operation is used to counteract interference between the second adjacent memory cells.

[0103] Figure 14 is a flowchart illustrating an example of the programming sequence of the entire BLK block in the first embodiment. Figures 15(a) and 15(b) are diagrams illustrating an example of the order of the selection character lines WL during programming in the first embodiment.

[0104] If writing begins, the control unit CTU (Figure 1) selects character lines WL0~WLn and strings St0~St3 sequentially in a predetermined order according to the instructions of the processor 33 (Figure 2), as shown in Figure 14, and performs programming continuously. Character lines WL are selected sequentially from the smallest character line number i, as shown in Figures 15(a) and 15(b). Furthermore, the multiple physical memory cell groups MG corresponding to the same character line number i are selected sequentially from the smallest string number j.

[0105] In the example of Figure 15(a), after the first stage of programming is performed on all strings St0~St3 (all physical memory groups MG) corresponding to character line WLi, the second stage of programming is performed on all physical memory groups MG corresponding to the previous character line WLi-1, and further, the third stage of programming is performed on all physical memory groups MG corresponding to character line WLi-1.

[0106] In the example of Figure 15(b), after the first stage of programming is performed on all the strings St0~St3 (all physical memory groups MG) corresponding to the character line WLi of line 1, the second and third stages of programming are performed sequentially on all the physical memory groups MG corresponding to the character line WLi-1 of the previous line.

[0107] The programming process consists of three stages. The first and second stages are the same as the previous Foggy-Fine programming. Here, a third stage is added (writing again). The third stage programming is the same as the second stage programming. After processing all the substrings St0~St3 in the character line number i, it returns to the original substring number 0 in the same character line number i, and performs the programming in ascending order of substring number j.

[0108] Additionally, Figures 14 and 15(a) illustrate the case where the string St within block BLK has 4 characters, but the string St within block BLK can have 3 or fewer characters, or even 5 or more characters. The procedure for writing a single character line WLi is basically the same as that shown in Figure 10(b), and therefore is omitted.

[0109] Figure 15(b) shows a variation of Figure 15(a) where the third stage of programming for word line WLi is performed immediately after the second stage programming. The example shown in Figure 15(b) is a point where the third stage programming is performed without changing the word line address, offering the advantage of a simpler programming sequence than the example shown in Figure 15(a). However, since it follows immediately after the second stage programming, it occurs when initial charge leakage is insufficient, and the rewrite is performed before the second stage programming of the adjacent word line WLi+1. Therefore, the word line WLi must be in its final state unaffected by interference between adjacent cells. In other words, performing a rewrite before the critical value distribution is finalized has the disadvantage of potentially not achieving the desired critical value increase. Specifically, for example, if a memory cell MC with insufficient initial charge leakage is rewritten, the critical value voltage after rewriting may be higher than expected, posing a risk of reaching the distribution area adjacent to the high-voltage side. This is called overwrite (overprogramming) and is one of the causes of data errors in NAND flash memory 40.

[0110] Figure 16 is a diagram showing the critical value distribution after programming in the first embodiment. Figure 16(T1) shows the critical value distribution of the initial state before programming, i.e., the eliminated state. Figure 16(T2) shows the critical value distribution after the first stage of programming (Foggy programming). Figure 16(T3) shows the critical value distribution after the second stage of programming (Fine programming). Figure 16(T4) shows the critical value distribution after the third stage of programming (reprogramming).

[0111] As shown in (T1) of Figure 16, the critical voltage of the full memory cell MC of the NAND memory cell array is located in region S0 in the unwritten state ("erased" state).

[0112] As shown in Figure 16 (T2), the control unit (CTU) of the NAND flash memory 40, during the first-stage programming, according to the bit values ​​written (memorized) to the Lower, Middle, and Upper pages, maintains the critical value distribution in region S0 for each memory cell MC, or injects charge to move the distribution to regions S1 to S7, which are higher than region S0. The correspondence between the written bit values ​​and the critical value regions is as described above. Here, in regions S1 to S7, the width of the critical value distribution is roughly expanded during programming, making the critical value voltage slightly lower.

[0113] Therefore, the memory cell MC is programmed into 8 levels based on the data from the Lower, Middle, and Upper pages. However, due to the wide width of the threshold distribution, it overlaps with other adjacent threshold distributions, making it impossible to read the data. Nevertheless, since the threshold distribution after this first-stage programming does not require fine-tuning, it allows for high-speed programming.

[0114] Furthermore, as shown in Figure 16 (T3), during the 2nd stage programming, data writing requires data from all pages of the Lower, Middle, and Upper layers. Moreover, the control unit (CTU) of the NAND flash memory 40 is ultimately programmed into eight critical value regions after the 2nd stage programming. This makes it possible to read all page data. During the 2nd stage programming, the greater the change in the critical voltage of the memory cell MC from the end of the 1st stage programming, the greater the interference between the first adjacent cells. Therefore, it is ideal for the change in the critical voltage from the 1st stage to the 2nd stage to be small.

[0115] Furthermore, for example, writing (programming) to a memory cell MC is performed by applying one or more programming voltage pulses to the corresponding character line WL. After each programming voltage pulse is applied, a readout is performed to confirm whether the memory cell MC has moved beyond the critical value boundary level. By repeating this application and readout, the critical value distribution of the memory cell MC can be moved within a predetermined region S1 to S7. The critical value voltage of the corresponding memory cell MC is determined from the data of the entire page of the write target, and the voltage value of multiple programming pulses is gradually increased during writing, thereby forming the determined critical value voltage. Memory cells MCs that reach the target critical value voltage are excluded from the write target.

[0116] The control unit (CTU) of the NAND flash memory 40, as shown in Figure 16 (T4), adjusts the programming voltage (set to be lower than the threshold rise amplitude of the programming in the 2nd stage) based on the bit values ​​to be written (memorized) to the Lower, Middle, and Upper pages, targeting only the memory cells MC in regions S5 to S7. This reduces the threshold rise amplitude caused by the application of a single programming voltage pulse, thus writing "weakly". In this way, the threshold voltage of the memory cells MC located on the high-distribution side is not increased, while the threshold voltage of the cells located on the low-distribution side is increased.

[0117] Verification can be performed in the 3rd stage of programming, or it can be omitted. The verification voltage during verification is the same as the verification voltage (voltages Vr5, Vr6, Vr7) in the 2nd stage of programming, or a higher voltage Vr5', Vr6', Vr7' can be set.

[0118] In the rewriting of regions S5 to S7 (programming in the 3rd stage), the memory cell MC to be written is determined according to the write data of adjacent cells.

[0119] Figure 17 shows an example of the combination of the object cell and the critical value region of the adjacent cell in the 3rd stage of programming as the first embodiment. In Figure 17, the part marked with "0" is the memory cell MC of the write object. The memory cell MC of the write object is the memory cell MC of the 3rd stage programming of the character line WLi that writes to regions S5~S7, and is the memory cell MC of the character line WLi+1 that writes to regions S0~S2.

[0120] In Figure 17, the memory cells MCs in other combinations are not the write targets during the 3rd stage programming. Furthermore, the combination shown in Figure 17 is an example; the combinations of write targets can be expanded or reduced according to the intensity of interference between adjacent cells. Also, for each memory cell MC corresponding to regions S5-S7, at least one of the magnitude of the 3rd stage programming voltage and the pulse width (application time) can be individually set. For example, the 3rd stage programming voltage (the voltage at the initial value during verification) can be greater than the 1st stage programming voltage (the voltage at the initial value during verification). For example, the 3rd stage programming voltage (the voltage at the initial value during verification) can be lower than the 2nd stage programming voltage (the voltage at the initial value during verification). For example, the application time of the 3rd stage programming voltage can be longer than the application time of the 1st stage programming voltage. For example, the application time of the 3rd stage programming voltage can be shorter than the application time of the 2nd stage programming voltage.

[0121] The advantages of limiting the memory cells (MCs) to be rewritten to those with the greatest interference between adjacent cells are as follows. Writing to NAND flash memory involves applying a programming voltage to the word line WLi and injecting charge into the charge accumulation layer 336 (Figure 4B). The amount of charge injected is typically determined by the programming voltage. However, due to individual differences in the shape and characteristics of each memory cell (MC), the amount of charge injected varies between memory cells (MCs) that are simultaneously written to the same word line WLi. As a result, there will be a deviation in the critical voltage range of a single programming pulse rise. Therefore, if a large number of memory cells (MCs) are written simultaneously, there is a certain probability that a few memory cells will unexpectedly experience a large critical voltage rise, and some of these will reach areas adjacent to the high-voltage side. This is called overwriting (overprogramming), and is one of the causes of data errors in the NAND flash memory 40. Limiting the memory cells (MCs) to be rewritten to those that are necessary reduces the number of memory cells and has the effect of suppressing overwriting.

[0122] The determination of the combination of the distribution of adjacent cells as the write target in the 3rd stage of programming shown in Figure 17 is, for example, using the write data held in the data buffer (RAM 31) of the memory controller 30. For example, when the write distribution of word line WLi is region S5 and the write distribution of word line WLi+1 is region S0, it is determined that the bit value of each page written to word line WLi is "011" and the bit value of each page written to the adjacent word line WLi+1 is "111".

[0123] When the memory controller 30 is programmed in the sequence shown in Figure 15(a) or Figure 15(b), including skipping a word line number i, since the word line number i is repeatedly changed, it is necessary to constantly maintain three consecutive word lines WL pages of page data in the data buffer (RAM 31). That is, the execution of the 3rd stage programming of word line WLi is immediately following the execution of the 2nd stage programming of word line WLi, which is between the 1st stage programming and the 2nd stage programming of word line WLi+1. Therefore, the page data of both word line WLi and word line WLi+1 are stored in the data buffer (RAM 31) of the memory controller 30, making operations using such data convenient.

[0124] Figure 18 shows the control flow for writing data in the first embodiment. Here, the write target memory cell MC is defined as the decision executor that performs the third-stage programming in the memory interface 36 within the memory controller 30. The third-stage programming involves writing control to each critical value region.

[0125] First, the write data for character line WL0 is transferred from the host interface 34 to the data buffer (RAM 31) (process F10), and then from the data buffer (RAM 31) to the memory interface 36 (process F11). The memory interface 36 then transfers the write data for character line WL0 to the NAND flash memory 40 (process F12), where the first stage of programming for character line WL0 is performed.

[0126] Next, the write data for character line WL1 is transferred from the host interface 34 to the data buffer (RAM 31) (process F13), and from the data buffer (RAM 31) to the memory interface 36 (process F14). The memory interface 36 transfers the write data for character line WL1 to the NAND flash memory 40 (process F15), where the first stage of programming for character line WL1 is performed in the NAND flash memory 40.

[0127] Next, the write data for word line WL0 is transferred from the data buffer (RAM31) to the memory interface 36 (process F16). The memory interface 36 then transfers the write data for word line WL0 to the NAND flash memory 40 (process F17), where the second stage of programming for word line WL0 is performed in the NAND flash memory 40.

[0128] Secondly, the write data of character lines WL0 and WL1 is transferred from the data buffer (RAM31) to the memory interface 36 (process F18).

[0129] Secondly, for example, in the programming of character line WL0, 3rd stage, and region S5, one page of data is generated (then data is written) according to the discrimination conditions shown in Figure 17. The data written by character line WL0 is region S5, and the data written by character line WL1 is the bits of regions S0~S2, which are the write bits. Other bits are non-write bits (step S501).

[0130] Secondly, memory interface 36 transfers this page of data to NAND flash memory 40 (process F19), and NAND flash memory 40 performs a page rewrite on character line WL0.

[0131] Secondly, the write data of character lines WL0 and WL1 is transferred from the data buffer (RAM31) to the memory interface 36 (process F20).

[0132] Secondly, in the character line WL0, 3rd stage, and region S6 programming, one page of data is generated (the data is then written) according to the discrimination conditions shown in Figure 17. The data written for character line WL0 is region S6, and the data written for character line WL1 is the bits in regions S0~S2, which are the write bits. All other bits are non-write bits (step S502).

[0133] Secondly, memory interface 36 transfers this page of data to NAND flash memory 40 (process F21), and NAND flash memory 40 performs a page rewrite on character line WL0.

[0134] Secondly, the write data of character lines WL0 and WL1 is transferred from the data buffer (RAM31) to the memory interface 36 (process F22).

[0135] Secondly, in the character line WL0, 3rd stage, and region S7 programming, one page of data is generated (the data is then written) according to the discrimination conditions shown in Figure 17. The data written for character line WL0 is region S7, and the data written for character line WL1 is the bits in regions S0~S2, which are the write bits. All other bits are non-write bits (step S503).

[0136] Secondly, memory interface 36 transfers this page of data to NAND flash memory 40 (process F23), and NAND flash memory 40 performs a page rewrite on character line WL0.

[0137] Subsequently, after character line WL2 (after process F24~F28), the same process is performed to write data to the data buffer (RAM31) and generate one page of data for programming in the 3rd stage of memory interface 36.

[0138] In the example shown in Figure 18, the procedure is illustrated by rewriting the distribution of rewrite objects one page at a time, but all rewrite object units can also be grouped together. For example, in the rewrite object conditions shown in Figure 17, the unit corresponding to the critical value region S5 has a bit value of "011" for the written page, the unit corresponding to the critical value region S6 has a bit value of "001" for the written page, the unit corresponding to the critical value region S7 has a bit value of "101" for the written page, and all other units have a bit value of "111" for the written page. That is, data that can be eliminated can also be specified for processing as non-write units. Such page data can also be transferred from the memory interface 36 to the NAND flash memory 40 as rewrite data for writing. [Effect]

[0139] According to this embodiment, the margin for shifting the data retention threshold of the memory cell MC, which suffers from data retention degradation based on adjacent cell patterns, can be increased, thus providing a highly reliable memory system 10.

[0140] Furthermore, in this embodiment, since the selection of the memory cell MC for rewriting (the generation of rewrite data) is performed by operations based on the write data, there is no need to perform a read operation from the memory cell MC corresponding to the character line WLi+1. Therefore, the time required for read operations, data transfer between the memory chip and the memory controller 30, ECC decoding, etc., is eliminated, and the selection of the memory cell MC for rewriting can be performed at high speed.

[0141] Furthermore, in this embodiment, when Foggy-Fine programming is used as the programming sequence, the append write operation can be implemented without an additional data buffer (RAM31). This is because the write data in the data buffer (RAM31) can be used to perform the write target unit discrimination operation in the 3rd stage of programming. [Variations of the first embodiment]

[0142] Furthermore, this embodiment uses the 3-bit / Cell case as an example for explanation, but it is also applicable to other multi-value cases (2-bit / Cell, 4-bit / Cell, 5-bit / Cell, etc.).

[0143] Furthermore, the Foggy-Fine programming case illustrates the programming order, but the same applies to other complex-stage programming cases. Moreover, even the programming order that programs all bits simultaneously can be applied by maintaining the write data of the complex adjacent word lines WL in the controller's buffer.

[0144] Furthermore, in this embodiment, an example is shown where write data corresponding to three consecutive word lines WL in the data buffer (RAM31) of the memory controller 30 is held. However, such write data can also be held, for example, in the data buffer contained in the NAND flash memory 40.

[0145] Furthermore, in this embodiment, the target unit for the rewrite operation is determined based on the data of a plurality of memory cells MC corresponding to the selected character line WLi and the data of a plurality of memory cells MC corresponding to the adjacent character line WLi+1. However, for example, in addition to such data, the target unit for the rewrite operation may also be determined based on the data of a plurality of memory cells MC corresponding to the adjacent character line WLi-1. [Second Implementation]

[0146] The second embodiment adds countermeasures against interference between the first adjacent memory cells using Foggy-Fine programming. However, since its methods share many similarities with the first embodiment, the explanation is appropriately omitted.

[0147] Figure 19 is a diagram showing the critical value distribution after programming in the second embodiment. Figure 19(T1) shows the critical value distribution of the initial state before programming, i.e., the eliminated state. Figure 19(T2) shows the critical value distribution after the first stage of programming (Foggy programming). Figure 19(T3) shows the critical value distribution after the second stage of programming (Fine programming). Figures (T1) to (T3) in Figure 19 are the same as those in Figure 16 and are therefore omitted.

[0148] Figure 19 (T3') shows the critical value distribution after the first stage of programming (Foggy programming) of the next adjacent word line WL. The memory cells MC located in the low critical value regions S0~S3 correspond to the memory cells MC (adjacent cells) of the adjacent word line WL. The higher the voltage of the critical value region after writing, the more the critical value voltage will fluctuate to the high voltage side due to interference between the first adjacent cells. As a result, the distribution of the low critical value regions S0~S3 increases in width towards the top. Therefore, after the first stage of programming of the next adjacent word line WL, especially the narrowing interval between the distribution of low critical value regions and the distribution of adjacent critical value regions, data errors during readout become more likely to occur.

[0149] Figure 19(T4) shows the critical value region after the 3rd stage programming (reprogramming). As shown in Figure 19(T4), the control unit (CTU) of the NAND flash memory 40, during the 3rd stage programming, adjusts the programming voltage (set to be lower than the critical value rise amplitude of the 2nd stage programming) only for memory cells MC in the critical value regions S1 to S3, according to the bit values ​​written (memorized) to the Lower, Middle, and Upper pages. This reduces the rise amplitude of the critical value caused by the application of a single programming voltage pulse, thereby writing "weak" data. In this way, the critical value voltage of memory cells MC located on the high-distribution side does not rise, only the critical value voltage of memory cells located on the low-distribution side rises.

[0150] Additionally, verification can be performed in this 3rd stage of programming, or it can be omitted. The verification voltage during verification is the same as the verification voltage in the 2nd stage of programming, or a higher voltage can be set.

[0151] In the rewriting of regions S1 to S3 of the critical value, the memory cell MC that is to be written is determined according to the written data of the adjacent cells.

[0152] Figure 20 shows an example of the combination of the target cell and the critical value region of the adjacent cell in the third stage of programming as the second embodiment. In Figure 20, in the third stage programming of the word line WLi marked with "〇", the critical value voltage is region S1 to region S3, and the critical value voltage of the memory cell MC adjacent to the word line WLi+1 is region S0 to region S2. The memory cell MC of the target cell becomes the memory cell MC of the write object.

[0153] In Figure 20, the memory cells MC in other combinations are not the write targets. Furthermore, the combination shown in Figure 20 is an example; the combinations of write targets can be expanded or reduced according to the intensity of interference between adjacent cells. Also, for each memory cell MC corresponding to regions S5-S7, at least one of the magnitude of the programming voltage in the 3rd stage and the pulse width (application time) can be individually set. For example, the programming voltage in the 3rd stage (the voltage at the initial value during verification) can be greater than the programming voltage in the 1st stage (the voltage at the initial value during verification). For example, the programming voltage in the 3rd stage (the voltage at the initial value during verification) can be lower than the programming voltage in the 2nd stage (the voltage at the initial value during verification). For example, the application time of the programming voltage in the 3rd stage can be longer than the application time of the programming voltage in the 1st stage. For example, the application time of the programming voltage in the 3rd stage can be shorter than the application time of the programming voltage in the 2nd stage.

[0154] Figure 21 shows the control flow for writing data in the second embodiment. The third stage of programming involves writing control to each critical value region.

[0155] The control flow shown in Figure 21 is basically the same as the control flow shown in Figure 18. However, in the control flow shown in Figure 21, steps S501, S502, and S503 are replaced by steps S601, S602, and S603, and processes F19, F21, and F23 are replaced by processes F61, F62, and F63.

[0156] For example, in the character line WL0, 3rd stage, and region S1 programming, according to the discrimination conditions shown in Figure 20, one page of data is generated (then the data is written). The data written to character line WL0 is region S1, and the data written to character line WL1 is the bits of regions S0~S2, which are the write bits. All other bits are non-write bits (step S601).

[0157] Secondly, memory interface 36 transfers this page of data to NAND flash memory 40 (process F61), and NAND flash memory 40 performs a page rewrite on character line WL0.

[0158] Secondly, in the character line WL0, 3rd stage, and region S2 programming, according to the discrimination conditions shown in Figure 20, one page of data is generated (then the data is written). The data written to character line WL0 is region S2, and the data written to character line WL1 is the bits in regions S0~S2 that are written bits. All other bits are non-written bits (step S602).

[0159] Secondly, memory interface 36 transfers this page of data to NAND flash memory 40 (process F62), and NAND flash memory 40 performs a page rewrite on character line WL0.

[0160] Secondly, in the character line WL0, 3rd stage, and region S3 programming, according to the discrimination conditions shown in Figure 20, one page of data is generated (the data is then written). The data written for character line WL0 is region S3, and the data written for character line WL1 is the bits in regions S0~S2, which are the write bits. All other bits are non-write bits (step S603).

[0161] Secondly, memory interface 36 transfers this page of data to NAND flash memory 40 (process F63), and NAND flash memory 40 performs a page rewrite on character line WL0.

[0162] In the example shown in Figure 21, the procedure is illustrated by rewriting the distribution of rewrite objects one page at a time, but all rewrite object units can also be grouped together. For example, in the rewrite object conditions shown in Figure 20, the unit corresponding to the critical value region S1 has a bit value of "110" for the written page, the unit corresponding to the critical value region S2 has a bit value of "100" for the written page, the unit corresponding to the critical value region S3 has a bit value of "000" for the written page, and all other units have a bit value of "111" for the written page. That is, data that can be eliminated can also be specified for processing as non-write units. Such page data can also be transferred from the memory interface 36 to the NAND flash memory 40 as rewrite data for writing. [Third Implementation Form]

[0163] The third embodiment adds countermeasures against interference between the first adjacent memory cells using Foggy-Fine programming, a method different from the first embodiment. The common parts with the first embodiment are appropriately omitted descriptions.

[0164] Figure 22 is a diagram showing the critical value distribution after programming in the third embodiment. Figure 22(T1) shows the critical value distribution of the initial state before programming, i.e., the eliminated state. Figure 22(T2) shows the critical value distribution after the first stage of programming (Foggy programming). Figure 22(T3) shows the critical value distribution after the second stage of programming (Fine programming). Figures (T1) to (T3) of Figure 22 are the same as those in Figure 16 and are therefore omitted.

[0165] Figure 22(T4) shows the critical value distribution after the 3rd stage programming (reprogramming). As shown in Figure 22(T4), the control unit (CTU) of the NAND flash memory 40, during the 3rd stage programming, adjusts the programming voltage based on the bit values ​​written (memorized) to the Lower, Middle, and Upper pages, targeting only the memory cells MC in region S0. This reduces the rise in critical values ​​caused by a single programming voltage pulse, thus writing "weakly". Therefore, the critical value voltage of memory cells MC located on the high-distribution side is not increased, only the critical value voltage of those located on the low-distribution side increases. Verification can be performed during the 3rd stage programming, but it can also be omitted. The verification voltage Vr0' during verification is set between the lower and upper limits of the original region S0.

[0166] In the rewriting of region S0, the memory cell MC that is to be written is determined according to the written data of the adjacent cells.

[0167] Figure 23 illustrates an example of a combination of the target cell and the critical value region of adjacent cells in the 3rd stage programming of the third embodiment. In Figure 23, in the 3rd stage programming of the word line WLi marked with "0", the critical value voltage is region S0, and the critical value voltage of the memory cells MC adjacent to word line WLi+1 is region S5~S7, which are the memory cells MCs that are the target cells for writing. In Figure 23, memory cells MCs in other combinations are not marked and are not the target cells for writing. Furthermore, the combination shown in Figure 23 is an example, and the combination of target cells for writing can be expanded or reduced according to the intensity of interference between adjacent cells, etc.

[0168] Furthermore, when determining the memory cell MC of the object to be rewritten, a verification operation can be performed. The object of the verification operation may be, for example, only the example shown in Figure 23, or may include other memory cells MC. In addition, during the verification operation, the verification voltage Vr0' described above can be supplied to the select character line WL. Moreover, those with a threshold voltage of Vr0' or higher can be excluded from the rewrite object, and only those with a threshold voltage lower than Vr0' are included in the rewrite object. The result of the verification operation may be transmitted to the memory controller 30, or it may not be transmitted. When the result of the verification operation is transmitted to the memory controller 30, the result of the verification operation is reflected in the rewrite data, thereby excluding those with a threshold voltage of Vr0' or higher from the rewrite object. When the result of the verification operation is not transmitted to the memory controller 30, the calculation can be performed inside the NAND flash memory 40, thereby excluding those with a threshold voltage of Vr0' or higher from the rewrite object.

[0169] Figure 24 shows the control flow for writing data in the third embodiment.

[0170] The control flow shown in Figure 24 is basically the same as the control flow shown in Figure 18. However, in the control flow shown in Figure 24, step S701 is performed instead of steps S501, S502, and S503, and process F71 is performed instead of process F19. Steps S502, S503 and processes F20, F21, F22, and F23 are not performed.

[0171] In the character line WL0, 3rd stage, and region S0 programming, one page of data is generated (then data is written) according to the discrimination conditions shown in Figure 23. The data written by character line WL0 is region S0, and the data written by character line WL1 is the bits of regions S5~S7, which are the write bits. All other bits are non-write bits (step S701).

[0172] Secondly, memory interface 36 transfers this page of data to NAND flash memory 40 (process F71), and NAND flash memory 40 performs a page rewrite on character line WL0.

[0173] The order in which character lines are selected during programming in the third embodiment is the same as in the first embodiment shown in Figure 15, but a variation of the third embodiment is shown in Figure 25. This variation shows the case where programming of the character line WLi is performed in the third stage after the second stage programming of the next adjacent character line WLi+1. In this sequence, since the number of character lines WL crossed during the programming stage progression increases to four, there is a disadvantage of increased control complexity. However, by performing the third stage programming after receiving the final inter-unit interference from the adjacent character lines WL, there is an advantage of reducing the risk of over-programming.

[0174] In the programming sequence shown in Figure 25, during the 3rd stage of programming for word line WLi, there may be cases where data for word line WLi has been discarded in the data buffer (RAM31) of the controller. However, in the determination of the target memory cell MC, only the critical value of the adjacent memory cell MC of word line WLi+1 can be set to the condition of region S5 to region S7, while excluding the critical value of the memory cell MC of word line WLi set to region S0. This is because, as long as the programming voltage is adjusted to the level that allows weak writing at the lower end of region S0, even if all memory cells MC of word line WLi are set as writing targets, only the memory cell MC located at the lower end of region S0 will actually be written. [Other implementation forms]

[0175] Figure 17 illustrates an example of a combination of memory cells MC to be rewritten in the first embodiment. Figure 20 illustrates an example of a combination of memory cells MC to be rewritten in the second embodiment. Figure 23 illustrates an example of a combination of memory cells MC to be rewritten in the third embodiment. However, these are just examples, and the specific combinations can be adjusted appropriately. For example, all of the 21 combinations of memory cells MC shown in Figures 17, 20, and 23 can be used as the objects to be rewritten, or only a portion of them can be used as the objects to be rewritten. [other]

[0176] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit and scope of the invention. These embodiments or variations thereof are included within the scope and spirit of the invention, as well as within the scope of the patent application and its equivalents.

[0177] MC: Memory Cube WL: Character Line 10: Memory System 30: Memory controller 31: RAM (Data Buffer) 40: NAND flash memory

Claims

1. A memory system characterized by comprising: a non-volatile memory including a plurality of first memory cells, first word lines connected to the plurality of first memory cells, a plurality of second memory cells, and second word lines connected to the plurality of second memory cells; and a controller connected to the non-volatile memory, the controller being configured to hold: first write data for writing to the plurality of first memory cells; and second write data for writing to the plurality of second memory cells, the writing being performed after writing to the plurality of first memory cells, and being configured to calculate rewrite data based on the first write data and the second write data, the non-volatile memory being configured to perform: a first write operation for writing to the plurality of first memory cells based on the first write data input from the controller; and a rewrite operation for writing a portion of the plurality of first memory cells based on the rewrite data input from the controller. The magnitude of the first write voltage applied to the first character line during the aforementioned rewrite operation and the application time of the first write voltage to the first character line can be set based on the aforementioned first write data and the aforementioned second write data.

2. The memory system as described in request item 1, wherein, After the first write operation is performed at least once, the rewrite operation is performed.

3. The memory system as described in claim 1, wherein, The aforementioned non-volatile memory is configured to further perform a second write operation, which is to write the aforementioned plurality of second memory cells according to the aforementioned second write data input from the aforementioned controller. The aforementioned second write operation is performed after the aforementioned first write operation has performed at least one row, and the aforementioned rewrite operation is performed after the aforementioned second write operation has performed at least one row.

4. The memory system as described in claim 2, wherein, During the aforementioned rewrite operation, a verification operation is performed, and based on the result of the aforementioned verification operation, the aforementioned portion of the first memory cell of the aforementioned plurality of objects that are to be the subject of the aforementioned rewrite operation is selected.

5. The memory system as described in claim 1, wherein, During the aforementioned write operation, a verification operation is performed, and based on the result of the aforementioned verification operation, a portion of the aforementioned plurality of first memory cells is written multiple times.

6. The memory system as described in claim 1, wherein, The aforementioned first write operation is performed in multiple stages.

7. The memory system as described in claim 1, wherein, The aforementioned controller has a first memory area, and the aforementioned first written data and the aforementioned second written data are stored in the aforementioned first memory area.

8. The memory system as described in claim 1, wherein, The aforementioned non-volatile memory has a second memory region, and the aforementioned first written data and the aforementioned second written data are stored in the aforementioned second memory region.

9. The memory system as described in claim 1, wherein, The aforementioned non-volatile memory includes a voltage supply unit. In the aforementioned first write operation, the aforementioned voltage supply unit applies a first programming voltage pulse to the aforementioned first word line. In the aforementioned rewrite operation, the aforementioned voltage supply unit applies a second programming voltage pulse to the aforementioned first word line. The magnitude of the aforementioned second programming voltage pulse is greater than the magnitude of the aforementioned first programming voltage pulse.

10. The memory system as described in claim 1, wherein, The aforementioned non-volatile memory includes a voltage supply unit. In the aforementioned first write operation, the aforementioned voltage supply unit applies a first programming voltage pulse to the aforementioned first word line. In the aforementioned rewrite operation, the aforementioned voltage supply unit applies a second programming voltage pulse to the aforementioned first word line. The application time of the aforementioned second programming voltage pulse is longer than the application time of the aforementioned first programming voltage pulse.

11. A memory system characterized by comprising: a non-volatile memory including a plurality of first memory cells, a first character line connected to the plurality of first memory cells, a plurality of second memory cells, a second character line connected to the plurality of second memory cells, a plurality of third memory cells, and a third character line connected to the plurality of third memory cells; and a controller connected to the non-volatile memory, wherein the first character line, the second character line, and the third character line are arranged in a first direction, the first character line is disposed between the second character line and the third character line, the first character line is adjacent to the second character line and the third character line, and the controller is configured to hold: first write data for writing to the plurality of first memory cells; The second write data is used to write to the aforementioned plurality of second memory cells, which is performed after the writing to the aforementioned plurality of first memory cells; and the third write data is used to write to the aforementioned plurality of third memory cells, which is performed before the writing to the aforementioned plurality of first memory cells; and is configured to calculate rewrite data based on the aforementioned first write data, the aforementioned second write data, and the aforementioned third write data, the aforementioned non-volatile memory is configured to perform: a first write operation, which writes to the aforementioned plurality of first memory cells based on the aforementioned first write data input from the aforementioned controller; and a rewrite operation, which writes to a portion of the aforementioned plurality of first memory cells based on the aforementioned rewrite data input from the aforementioned controller.

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