Cell region having vg-contact-free and vd-contact-free tracks and method of manufacturing same

Abstract

A cell region of a device includes: an active region; gate segments and metal-to-source / drain (MD) contact windows that are interleaved; via-to-gate (VG) contact windows; via-to-MD contact windows (VD); VG contact windows and VD contact windows correspondingly aligned with α tracks extending in a first direction; a first wiring (RTE) segment correspondingly aligned with the α tracks; and a first embedded power grid segment; the first and second α tracks adjacent to the first and second boundaries of the cell region; at least a third α track located between the first and second α tracks; the first α track having no VG contact windows aligned with it; and the second α track having no VD contact windows aligned with it.

Description

Prior Technology

[0001] The integrated circuit (IC) industry produces various analog and digital semiconductor devices to solve problems in different fields. Advances in semiconductor manufacturing technology have gradually reduced component size and spacing, leading to a gradual increase in transistor density. ICs are becoming increasingly smaller. Simple Explanation of the Diagram

[0002] One or more embodiments are illustrated in the accompanying drawings by way of example rather than limitation, wherein elements having the same reference numerals denote the same elements throughout the specification. Unless otherwise stated, the figures are not drawn to scale. Figure 1 is a block diagram according to some embodiments. Figures 2A to 2E are corresponding layout diagrams according to some embodiments. Figures 3A to 3C are corresponding layout diagrams according to some embodiments. Figures 4A and 4B are corresponding cross-sectional views according to some embodiments. Figure 5A is a layout diagram according to some embodiments. Figures 5B to 5C are corresponding block diagrams according to some embodiments. Figures 6 and 7A to 7B are flowcharts of corresponding methods according to some embodiments. Figure 8 is a block diagram of an electronic design automation (EDA) system according to some embodiments. Figure 9 is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Implementation

[0003] The following disclosure provides numerous different embodiments or examples for protecting various features of the subject matter. Examples of elements, materials, values, steps, operations, arrangements, or similar items are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. Other elements, values, operations, materials, arrangements, or similar items are also considered. For example, in the following description, the formation of a first feature over or on a second feature includes embodiments where the first and second features are in direct contact, and further includes embodiments where an additional feature is formed between the first and second features, such that the first and second features are in indirect contact. Furthermore, reference numerals and / or letters are repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0004] Furthermore, for ease of description, this document uses spatially relative terms such as "below," "under," "down," "above," and "up" to describe the relationship between one element or feature shown in the figures and other elements or features (one or more). These spatially relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly. In some embodiments, the term standard cell structure refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from their libraries and used as elements representing circuits in layout diagrams.

[0005] In some embodiments, the unit region of the device includes: active regions extending along a first direction; gate segments and metal-to-source / drain-region (MD) contact windows extending along a second direction perpendicular to the first direction, intersecting each other and having portions above the active regions; via-to-gate (VG) contact windows above the gate segment regions; via-to-MD-contact (VD) contact windows above the MD contact window regions; VG and VD contact windows correspondingly aligned with α tracks extending along the first direction; first routing (RTE) segments extending along the first direction in a first metallization layer, correspondingly aligned with the α tracks, and respectively above the VG or VD contact windows; and first buried power grid segments extending along the first direction in a first buried metallization layer on the second side of the active regions. The cell region consists of segments, and the first α track (e.g., the top α track) and the second α track (e.g., the bottom α track) are adjacent to the first boundary (e.g., the top) and the second boundary (e.g., the bottom) of the cell region, respectively; at least one third α track (e.g., the inner α track) is located between the first and second α tracks; the first α track has no VG contact window aligned with it; and the second α track has no VD contact window aligned with it. Such a cell region is an example of a back-side power delivery (BSPD) architecture.

[0006] According to another method for generating a device with a BSPD architecture, for various spatial relationships (e.g., corresponding VG spacing, corresponding VD spacing, corresponding V0 structural spacing, or similar), two extreme ultraviolet lithography (EUVL) masks are required to generate the spatial relationship for each corresponding spatial relationship. In contrast, at least some embodiments use a larger minimum spacing for each corresponding spatial relationship. In some embodiments, one EUVL mask is sufficient to generate the spatial relationship in a device with a BSPD architecture for each corresponding spatial relationship, at least in part due to one or more design rules disclosed herein. By eliminating one EUVL mask, these embodiments are at least cheaper and / or faster to manufacture compared to other methods.

[0007] Figure 1 is a block diagram of the functional unit region 104 of a device 100 according to some embodiments.

[0008] Device 100 is an example of an integrated circuit (IC). In some embodiments, device 100 is referred to as a semiconductor device. Device 100 includes a macro region 102. In some embodiments, macro region 102 comprises one or more functional regions, such as circuit regions or the like. In some embodiments, macro region 102 includes one or more memories, power grids, cells or multiple cells, inverters, latches, buffers, drivers, analog devices such as digital-to-analog converters (DACs) or analog-to-digital converters (ADCs) or the like, clock trees, phase-locked loops (PLLs), interfaces, and / or any other type of circuit arrangement. Examples of memory include static random access memory (SRAM), dynamic random access memory (DRAM), resistive random access memory, magnetoresistive random access memory (MRAM), read-only memory (ROM), or similar.

[0009] Macro region 102 can be digitally represented in a standard cell library. In some embodiments, macro region 102 is understood in a context similar to an architectural hierarchy in modular programming, where a subroutine / program is called by a main program (or other subroutine) to perform a given computational function. In this context, device 100 uses macro region 102 to perform one or more given functions. Therefore, in this context and in terms of architectural hierarchy, device 100 is similar to a main program, and macro region 102 is similar to a subroutine / program. In some embodiments, macro region 102 is a software macro. In some embodiments, macro region 102 is a hardware macro. In some embodiments, macro region 102 is a software macro described digitally using register-transfer level (RTL) code. In some embodiments, macro region 102 has not been composed, placed, and routed, such that the software macro can be composed, placed, and routed for various process technology nodes. In some embodiments, macro region 102 is a hardware macro described digitally in a binary file format (e.g., Graphic Database System II (GDSII) streaming format), wherein the binary file format represents, in a hierarchical manner, the planar geometry, text labels, other information, and similar information of one or more layouts of macro region 102. In some embodiments, the binary file format is referred to as a non-text file format. In some embodiments, macro region 102 has been composited, positioned, and wired to make the hardware macro specific to a particular process technology node.

[0010] In Figure 1, macro region 102 includes functional cell region 104 representing functional circuitry. Functional cell region 104 includes at least one active device, such as a transistor or the like. In some embodiments, functional cell region 104 includes one or more logic gates. In some embodiments, functional cell region 104 is or includes a buffer, driver, inverter, or the like. Examples of logic gates / circuits include circuits configured to perform logic functions AND, OR, NAND, NOR, XOR, INV, AND-OR-INVERT (AOI) (see, for example, Figure 5A), OR-AND-INVERT (OAI), or the like. Examples of other functional circuitry include multiplexers (MUX), flip-flops, buffers, drivers (DRV), latches, delays, clocks, memory, or the like.

[0011] Functional unit region 104 includes corresponding segments in one or more metallization layers (see, for example, Figures 4A to 4B). The figures in this disclosure assume a Cartesian coordinate system (unless otherwise stated), where the first, second, and third directions are parallel to the X, Y, and Z axes, respectively. In some embodiments, the first to third directions correspond to directions other than the X, Y, and Z axes. In some embodiments, the major and minor axes of the segments extend along the first and second directions, respectively, in even-numbered metallization layers; in these embodiments, the major and minor axes of the segments extend along the second and first directions, respectively, in odd-numbered metallization layers. In these embodiments, the boundaries of functional unit region 104 are described by the first and second directions.

[0012] In some embodiments, functional cell region 104 corresponds to a transistor element layer (see, for example, Figures 4A-4B) having circuit elements, such as transistors formed in front-end-of-line (FEOL) fabrication. In functional cell region 104, various metal layers (see, for example, Figures 4A-4B) and corresponding interconnect layers (see, for example, Figures 4A-4B) are interleaved above and / or below the active region (AR) layer (see, for example, Figures 4A-4B), stacked above and / or below the insulating layer in back-end-of-line (BEOL) fabrication. The back-end process provides power networks and / or wiring for the circuitry of device 100, including macro region 102 and functional cell region 104.

[0013] In some embodiments, the functional unit region 104 includes one or more active devices, passive devices, or the like. Examples of active devices or active elements include, but are not limited to, transistors, diodes, or the like. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, resistors, or the like.

[0014] Figure 2A is a layout diagram of macro region 202A according to some embodiments.

[0015] Macro region 202A is an example of macro region 102 in Figure 1. Macro region 202A is arranged relative to α orbital lines α0-α21 extending parallel to the X-axis. In Figure 2A and other layout diagrams disclosed herein, the first and second directions are assumed to be parallel to the X-axis and Y-axis, respectively. In some embodiments, the first and second directions are assumed to have directions other than being parallel to the X-axis and Y-axis, respectively. In Figure 2A and other layout diagrams disclosed herein, rows are collinear with the α orbital lines.

[0016] Macro region 202A includes functional (FN) cell regions (CR) 206A(1)-206A(2) and 208A(1)-208A(2) stacked relative to the Y-axis. Functional cell region 206A(2) is stacked on functional cell region 208A(2). Functional cell region 208A(1) is stacked on functional cell region 206A(2). Functional cell region 206A(1) is stacked on functional cell region 208A(1). Functional cell regions 206A(1)-206A(2) and 208A(1)-208A(2) are also described as staggered or scattered relative to the Y-axis.

[0017] Each of the functional unit regions 206A(1)-206A(2) and 208A(1)-208A(2) is configured to perform a given function, such as AOI (see, for example, Figure 5A). That is, each of the functional unit regions 206A(1)-206A(2) and 208A(1)-208A(2) is configured to perform the same function.

[0018] The components (see, for example, Figures 2B to 2E) on the front side of the active region layer (e.g., see Figures 4A to 4B) in each functional unit region 206A(1)-206A(2) and 208A(1)-208A(2) include: a gate segment in the gate / MD layer (see, for example, Figures 4A to 4B) (see, for example, Figures 2C to 2E); a metal-to-source / drain region (MD) contact window in the gate / MD layer (see, for example, Figures 2C to 2E); a via-to-gate (VG) contact window in the VG / VD layer (see, for example, Figures 4A to 4B) (see, for example, Figures 2C and 2D to 2E); a via-to-MD contact window (VD) contact window in the VG / VD layer (see, for example, Figures 2B and 2D to 2E); and a first wiring (RTE) segment in the first metallization layer (see, for example, Figures 4A to 4B). In some embodiments, VG is an abbreviation for via to gate. In some embodiments, VD is an abbreviation for via to source / drain.

[0019] In some embodiments, according to the numbering convention of the corresponding process technology node of the manufacturing apparatus, on the front side of the active region (AR) layer (see, for example, Figures 4A to 4B), the first metallization layer is metallization layer zero (MET0) (see, for example, Figures 4A to 4B) or metallization layer one (MET1), and correspondingly, the first interconnect layer on the first metallization layer is interconnect layer zero (VIA0) (see, for example, Figures 4A to 4B) or interconnect layer one (VIA1).

[0020] In these embodiments, again following the numbering convention of corresponding process technology nodes, the components on the back side of the active region (AR) layer (see, for example, Figures 4A-4B) include BVD contact windows (see, for example, Figures 2B and 2D-2E) in the buried via-to-source / drain-region (BVD) layer, and a first buried power grid segment in the first buried metallization layer. The first buried metallization layer is buried metallization layer zero (BMET0) (see, for example, Figures 4A-4B) or buried metallization layer one (BMET1), and correspondingly, the first buried interconnect layer under the first metallization layer is interconnect layer zero (VIA0) (see, for example, Figures 4A-4B) or interconnect layer one (VIA1).

[0021] In Figure 2A and other figures disclosed herein, the following naming convention is adopted: the first metallization layer is assumed to be MET0; the first interconnect layer is assumed to be VIA0; the second metallization layer is assumed to be MET1; the second interconnect layer is assumed to be VIA1; and the third metallization layer is assumed to be MET2. The metallized segment in the MET0 layer is called the M0 segment. The via structure in the VIA0 layer is called the V0 structure. The metallized segment in the MET1 layer is called the M1 segment. The via structure in the VIA1 layer is called the V1 structure. The metallized segment in the MET2 layer is called the M2 segment.

[0022] Looking at Figures 2D to 2E and Figures 4A to 4B or similar figures, the following naming convention is also adopted: the first embedded metallization layer is assumed to be BMET0; the first embedded interconnect layer is assumed to be BVIA0; the second embedded metallization layer is assumed to be BMET1; the second embedded interconnect layer is assumed to be BVIA1; and the third embedded metallization layer is assumed to be BMET2. The metallized segment in the BMET0 layer is called the embedded M0 segment. The via structure in the BVIA0 layer is called the BV0 structure. The metallized segment in the BMET1 layer is called the BM1 segment. The via structure in the BVIA1 layer is called the BV1 structure. The metallized segment in the BMET2 layer is called the BM2 segment.

[0023] The discussion will now return to Figure 2A.

[0024] In Figure 2A and other figures disclosed herein: the Gate segment and MD contact window are aligned with the corresponding β orbital line; and the VG contact window and VD contact window are aligned with the corresponding α orbital line and β orbital line.

[0025] Functional cell regions (FN CR) 206A(1)-206A(2) are examples of a first element arrangement configured to perform a given function. Functional cell regions 208A(1)-206A(2) are examples of a second element arrangement configured to perform a given function. The first and second arrangements contribute to the staggered / scattered stacking of functional cell regions 206A(1)-206A(2) and 208A(1)-208A(2) relative to the Y-axis.

[0026] In some embodiments, the first and second arrangements refer to the corresponding arrangements of the Gate segment, MD contact window, VG contact window, and VD contact window. In some embodiments, the first and second arrangements refer to the corresponding arrangements of the Gate segment, MD contact window, VG contact window, and VD contact window, plus the wiring segment (M0_rte segment) of the M0 segment (see, for example, Figures 2D and 5A) and the V0 structure.

[0027] Examples of differences between the first and second arrangements are discussed below, including the differences shown in functional unit regions 506 and 508 of Figures 2D to 2E, Figure 5A, or similar figures. Despite the differences between the first and second arrangements, they share common characteristics. The first common characteristic of both arrangements is that the Gate segment and VG contact window are aligned to the corresponding odd-numbered β orbital lines (e.g., β3-β9 orbital lines in Figures 2D to 2E). The second common characteristic is that the MD contact window and VD contact window are aligned to the corresponding even-numbered β orbital lines (e.g., β2-β10 orbital lines in Figures 2D to 2E). The third common characteristic of both arrangements is shown in Figures 2B to 2C.

[0028] Figures 2B and 2C are layout diagrams of corresponding functional unit regions 210B-210C according to some embodiments.

[0029] The corresponding layout diagrams of Figures 2B to 2C and other layout diagrams disclosed herein represent transistor-based devices. Structures within the devices are represented by patterns (also called shapes) in the layout diagrams. For the sake of simplicity, elements in the corresponding layout diagrams of Figures 2B to 2C (and other layout diagrams disclosed herein) will be referred to as structures rather than patterns. For example, the shape representing an instance of the M0_rte segment in Figure 2B is referred to as the M0_rte segment itself rather than a pattern.

[0030] A layout diagram is a top view. Shapes in a layout diagram are two-dimensional relative to, for example, the X and Y axes, while the represented device is three-dimensional. Therefore, shapes in such a layout diagram are described as having width / length relative to the X-axis and height relative to the Y-axis. Relative to the Z-axis, for example, the bottom / back side of a first element represented in the layout diagram is stacked on top / front of a second element device represented in the layout diagram, or the top / front side of the first element is stacked below, for example, the bottom / back side of the second element.

[0031] Typically, relative to the Z-axis, the device is organized as a stack of layers, with corresponding structures located within these layers. Each shape in the layout diagram more specifically represents an element in the corresponding layer of the device. Furthermore, the layout diagram typically indicates the relative depth of a shape and its corresponding layer, i.e., its position along the Z-axis, by superimposing a second shape on a first shape such that the second shape at least partially overlaps the first shape. To simplify the illustration, some structures in the device having a first stacking order along the Z-axis are represented in the layout diagram using a second stacking order along the Z-axis, i.e., a different / twisted stacking order; see, for example, Figure 2I.

[0032] Layout diagrams vary in the amount of detail they represent. In some cases, selected layers of a layout diagram are combined / abstracted into a single layer, for example, for simplification. Alternatively and / or additionally, in some cases, not all layers of the corresponding device are represented, i.e., selected layers of the layout diagram are omitted, for example, for illustrative simplicity. Alternatively and / or additionally, in some cases, not all elements of a given depicted layer are represented, i.e., selected elements of a given depicted layer in the layout diagram are omitted, for example, for illustrative simplicity. Figures 2B to 2C and other layout diagrams disclosed herein are examples of layout diagrams in which selected layers and / or selected elements depicting a given layer have been omitted.

[0033] Regarding Figures 2B to 2C, functional unit regions 210B and 210C are examples of functional unit regions 206A(1)-206A(2) and 208A(1)-208A(2) in Figure 2A, respectively.

[0034] Functional unit regions 210B-210C are representations of the first and second design rules (DRs) that result in the first and second arrangements in Figure 2A, as described below.

[0035] Regarding Figures 2A and 2B, the first design rule relates to the first α track in the α track, for example, the α track adjacent to and overlapping the bottom boundary of functional unit region 210B relative to the Y-axis. In the context of functional unit regions 206A(1)-206A(2) and 208A(1)-208A(2) in Figure 2A and 210B in Figure 2B, the first α track is referred to as the bottom α track. In Figures 2A to 2C, the bottom α tracks are assumed to be α tracks α5, α10, α15, and α20. The first design rule specifies that the bottom α track must not have any VD contact windows aligned with it. In some embodiments, the first design rule is referred to as the VD-non-grata-track design rule.

[0036] Regarding Figures 2A and 2C, the second design rule relates to the second α track in the α track, for example, the α track adjacent to and overlapping the top boundary of functional unit region 210C relative to the Y-axis. In the context of functional unit regions 206A(1)-206A(2) and 208A(1)-208A(2) in Figure 2A and 210C in Figure 2C, the second α track is referred to as the top α track. In Figures 2B to 2C, the top α tracks are assumed to be α tracks α1, α6, α11, and α16. The second design rule specifies that the top α track must not have any VG contact windows aligned with it. In some embodiments, the second design rule is referred to as the VG-non-grata-track design rule.

[0037] In the functional unit regions 206A(1)-206A(2) and 208A(1)-208A(2) of Figure 2A and 210B of Figure 2C, the VD contact window is permissible on the top α track and on each inner α track located between the top α track and the bottom α track. For example, in Figures 2B to 2C, the inner α tracks are α tracks α2-α4. In other words, in the functional unit regions 206A(1)-206A(2) and 208A(1)-208A(2) of Figure 2A and 210B of Figure 2B, each of the α tracks α1-α4 is a VD-permissible α track.

[0038] In the functional unit regions 206A(1)-206A(2) and 208A(1)-208A(2) of Figure 2A and 210C of Figure 2C, the VG contact window is permissible on the bottom α track and each inner α track. In other words, in the functional unit regions 206A(1)-206A(2) and 208A(1)-208A(2) of Figure 2A and 210C of Figure 2C, each of the α tracks α2-α5 is a permissible α track for VG.

[0039] The third characteristic shared by the first and second arrangements, as discussed in Figure 2A, is again shown in Figures 2B and 2C. In each of the functional unit regions 210B and 210C, a VG contact window is permitted on each internal α track, i.e., each α track α2-α4 in Figures 2B and 2C. In each of the functional unit regions 210B and 210C, a VD contact window is permitted on each internal α track, i.e., (again) each α track α2-α4 in Figures 2B and 2C. Therefore, the third characteristic shared by the first and second arrangements is that a VG contact window and / or a VG contact window is permitted on each α track α2-α4 in Figures 2B and 2C. In other words, as shown in Figures 2B and 2C, the third characteristic shared by the first and second arrangements is that each α track α2-α4 is an α track that allows VD (VD-permissible alpha track) and an α track that allows VG (VG-permissible alpha track).

[0040] Figure 2D is a layout diagram of macro region 202D according to some embodiments.

[0041] Macro region 202D is an example of macro region 102 in FIG1. ​​Macro region 202D includes functional (FN) cell regions 206D(1)-206D(2) and 208D(1) stacked relative to the Y-axis. In FIG2D, section lines 4A-4A' extend parallel to the X-axis. In some embodiments, section lines 4A-4A' of FIG2D correspond to section 420A of FIG4A.

[0042] Functional unit region 208D(1) is stacked on functional unit region 206D(2). Functional unit region 206D(1) is stacked on functional unit region 208D(1). Functional unit regions 206D(1)-206D(2) and 208D(1) are also described as being staggered relative to the Y-axis.

[0043] Each of the functional unit regions 206D(1)-206D(2) and 208D(1) is configured to perform a given function. That is, each of the functional unit regions 206D(1)-206D(2) and 208D(1) is configured to perform the same function. However, as described below, the arrangement of the elements in functional unit regions 206D(1)-206D(2) differs from the arrangement of the elements in functional unit region 208D(1).

[0044] Each of the functional unit regions 206D(1)-206D(2) and 208D(1) includes the following elements: active region (AR); Gate segment; MD contact window; VG contact window; VD contact window; M0_rte segment; V0 structure; wiring segment in M1 segment (M1_rte segment); isolation dummy gates (IDG) (discussed below); and power grid (PG) segment in BM0 segment (BM0_PG segment).

[0045] Because they contain the BM0_PG segment, each of the functional unit regions 206D(1)-206D(2) and 208D(1) is an example of a back-side power delivery (BSPD) architecture. Figure 2D assumes that none of the functional unit regions 206D(1)-206D(2) and 208D(1) have any M0 segment as a PG segment. Advantages of the BSPD architecture include reduced congestion of the front-side M0_rte segment, etc. In some embodiments, the selected M0 segment is a PG segment (M0_PG segment).

[0046] In some embodiments where the first and second arrangements refer to the corresponding arrangements of Gate segment, MD contact window, VG contact window and VD contact window: functional unit regions 206D(1)-206D(2) are instances of a first element arrangement configured to perform a given function; while functional unit region 208D(1) is an instance of a second element arrangement configured to perform a given function.

[0047] In Figure 2D, functional unit region 206D(2) includes a V0 structure and an M1_rte segment, while functional unit region 206D(1) does not. In some embodiments where the first and second arrangements refer to corresponding arrangements of Gate segment, MD contact window, VG contact window, VD contact window, V0 structure, and M1_rte segment: functional unit region 206D(2) is an instance of a first element arrangement configured to perform a given function; functional unit region 208D(1) is an instance of a second element arrangement configured to perform a given function; and functional unit region 206D(1) is a slight variation of functional unit region 206D(2), and therefore functional unit region 206D(1) is considered a minor variation of the first element arrangement.

[0048] In the macro region 202D of Figure 2D, relative to the X-axis, the left and right boundaries of functional unit regions 206D(1)-206D(2) and 208D(1) each correspond to an isolation dummy gate (IDG), rather than a corresponding gate segment. In some embodiments, the isolation dummy gate is a dielectric structure comprising one or more dielectric materials and serving as an electrical isolation structure. Therefore, the isolation dummy gate is not a conductive structure and thus does not serve as an active gate, for example, a transistor. The isolation dummy gate comprises one or more dielectric materials and serves as an electrical isolation structure. In some embodiments, the isolation dummy gate is based on a gate structure as a precursor. In some embodiments, the dummy gate structure includes a gate conductor, a gate insulating layer, (optionally) one or more spacers, etc. In some embodiments, an isolation dummy gate is formed by first forming a gate structure (e.g., a dummy gate structure), sacrificing / removing (e.g., etching) the gate conductor of the gate structure to form a trench, (optionally) removing a portion of the substrate previously below the gate conductor to deepen the trench, and then filling the trench with one or more dielectric materials such that the resulting electrically isolated structure (i.e., the isolation dummy gate) has a physical size similar to the size of the sacrificed dummy gate conductor, or the combined size of the sacrificed gate conductor and the removed portion of the substrate. In some embodiments, the isolation dummy gate is a dielectric feature comprising one or more dielectric materials (e.g., oxides, nitrides, oxynitrides, or other suitable materials) and used as an isolation feature. In some embodiments, the isolation dummy gate refers to a continuous polysilicon on oxide diffusion (OD) edge structure, and is referred to as a CPODE structure.

[0049] In Figure 2D, each boundary of functional unit regions 206D(1)-206D(2) and 208D(1) can be identified in the corresponding device by including one or more of the following features. In some embodiments, the top boundary of each of functional unit regions 206D(1)-206D(2) and 208D(1) is defined by a first reference line that extends parallel to the X-axis and is close to and parallel to a line intersecting the upper end of a first majority gate segment, for example, all of them in the example of Figure 2D. In some embodiments, the bottom boundary of each of functional unit regions 206D(1)-206D(2) and 208D(1) is defined by a second reference line that extends parallel to the X-axis and is close to and parallel to a line intersecting a second majority gate segment, for example, all of them in the example of Figure 2D. In some embodiments, such as as shown in FIG2D, the left and right boundaries of each of the functional cell regions 206D(1)-206D(2) and 208D(1) are defined by the corresponding IDG portion. In some embodiments, the left boundary of each of the functional cell regions 206D(1)-206D(2) and 208D(1) is defined by a third reference line that extends parallel to the Y-axis and is close to and parallel to the line intersecting the left end of the first majority of MO_rte segments, for example, all of them in the example of FIG2D; the right boundary of each of the functional cell regions 206D(1)-206D(2) and 208D(1) is defined by a fourth reference line that extends parallel to the Y-axis and is close to and parallel to the line intersecting the right end of the second majority of MO_rte segments, for example, all of them in the example of FIG2D. In some embodiments, the boundaries of the cell regions are identified by dummy source / drain regions and / or dummy conductors. In some embodiments, the boundary of a cell region is identified by a power rail (e.g., a VDD rail or a ground rail). In some embodiments, the boundary of a cell region is identified by finding a location that does not include certain types of interconnects. In some embodiments, the boundary is identified by blank space or a dummy region.

[0050] Relative to the Y-axis, the bottom boundary of functional unit region 208D(1) is also the top boundary of functional unit region 206D(2). In Figure 2D: the uppermost α track of functional unit region 208D(1) is assumed to be α track α6; the lowermost α track of functional unit region 208D(1) is assumed to be α track α10; the uppermost α track of functional unit region 206D(2) is assumed to be α track α11; the lowermost α track of functional unit region 206D(2) is assumed to be α track α15.

[0051] In Figure 2D, the Gate segments are spaced apart from each other at a uniform distance / p_gate relative to the X-axis. The p_gate spacing value depends on the corresponding semiconductor process technology node. In some embodiments, the p_gate spacing represents a contacted polysilicon gate pitch (CPP) for the corresponding semiconductor process technology node. Here, the 'poly' in CPP does not necessarily mean that the gate structure in the semiconductor device based on Figure 2D or similar graphics will be formed of polysilicon, but rather represents a historical convention, since the gate structure in ICs manufactured according to previous semiconductor process technology nodes was typically formed of polysilicon.

[0052] In Figure 2D, the M0_rte segments are spaced apart from each other with a uniform distance / spacing p_M0_rte relative to the Y-axis. The p_M0_rte spacing value depends on the corresponding semiconductor process technology node. In Figure 2D, and in other layout diagrams disclosed herein, M0_rte segments aligned to the same α orbital are referred to as alpha-coaligned M0_rte segments.

[0053] In Figure 2D, and in other layout diagrams disclosed herein, VG contact windows aligned to the same β track are referred to as beta-coaligned VG contacts. Adjacent beta-coaligned VG contacts are spaced apart by a minimum distance gap_VG relative to the Y-axis. In some embodiments, gap_VG is approximately equal to or greater than the smaller of p_gate or twice p_M0_rte, such that min{≈(p_gate), ≈(2*p_M0_rte)} ≤ gap_VG. According to another method for fabricating a device with a BSPD architecture, the corresponding minimum distance (OA_gap_VG) between adjacent beta-coaligned corresponding VG contact windows is approximately equal to the corresponding M0_rte spacing (OA_p_M0_rte). The corresponding gap OA_gap_VG is so small that this other method requires the use of two extreme ultraviolet lithography (EUVL) masks to fabricate the adjacent beta-coaligned corresponding VG contact windows of the corresponding device. In contrast, at least in part due to one or more design rules disclosed herein, at least some embodiments use a relatively large minimum distance, gap_VG, between adjacent β-collinear VG contact windows, for which an EUVL mask is sufficient to manufacture the adjacent β-collinear VG contact windows of the corresponding device; therefore, by eliminating an EUVL mask, these embodiments are at least cheaper and / or faster to manufacture than the other methods.

[0054] In Figure 2D, and in other layout diagrams disclosed herein, VD contact windows aligned to the same β track are referred to as beta-coaligned VD contacts. Adjacent beta-coaligned VD contacts are spaced apart by a minimum distance (gap_VD) relative to the Y-axis. In some embodiments, gap_VD is approximately equal to or greater than the smaller of p_gate or twice p_M0_rte, such that min{≈(p_gate), ≈(2*p_M0_rte)} ≤ gap_VD. According to another method for manufacturing a device with a BSPD architecture, the corresponding minimum distance (OA_gap_VD) between adjacent beta-coaligned corresponding VD contact windows is approximately equal to the corresponding M0_rte spacing (OA_p_M0_rte). The corresponding gap OA_gap_VD is so small that this other method requires the use of two EUVL masks to manufacture the adjacent beta-coaligned corresponding VD contact windows of the corresponding device. In contrast, at least in part due to one or more design rules disclosed herein, at least some embodiments use a relatively large minimum distance, gap_VD, between adjacent β-collinear VD contact windows, for which an EUVL mask is sufficient to manufacture adjacent β-collinear VD contact windows of the corresponding device; therefore, by eliminating an EUVL mask, these embodiments are at least cheaper and / or faster to manufacture than the other methods.

[0055] In Figure 2D, and in other layout diagrams disclosed herein, V0 structures aligned to the same β orbital are referred to as beta-coaligned V0 structures. Adjacent beta-coaligned V0 structures are spaced apart by a minimum distance gap_V0 relative to the Y-axis. In some embodiments, gap_V0 is approximately equal to or greater than the smaller of p_gate or twice p_M0_rte, such that min{≈(p_gate), ≈(2*p_M0_rte)} ≤ gap_V0. According to another method for fabricating a device with a BSPD architecture, the corresponding minimum distance (OA_gap_V0) between adjacent beta-coaligned corresponding V0 structures is approximately equal to the corresponding M0_rte spacing (OA_p_M0_rte). The corresponding gap OA_gap_V0 is so small that this other method requires the use of two EUVL masks to fabricate the adjacent beta-coaligned corresponding V0 structures of the corresponding device. In contrast, at least in part due to one or more design rules disclosed herein, at least some embodiments use a relatively large minimum distance, gap_V0, between adjacent β-collinear V0 structures, for which an EUVL mask is sufficient to manufacture the adjacent β-collinear V0 structures of the corresponding device; therefore, by eliminating an EUVL mask, these embodiments are at least cheaper and / or faster to manufacture than the other methods.

[0056] In Figure 2D, and in other layout diagrams disclosed herein, M1_rte segments aligned to the same β orbital are referred to as beta-coaligned M1_rte segments. Relative to the Y-axis, adjacent endpoints of beta-coaligned M1_rte segments are spaced apart by a minimum distance gap_M1_E2E. In some embodiments, gap_M1_E2E is substantially larger than p_M0_rte. In some embodiments, gap_M1_E2E is approximately twice p_M0_rte, such that ≈(2*p_M0_rte) ≤ gap_M1_E2E. According to another method for manufacturing a device with a BSPD architecture, the corresponding minimum distance (OA_gap_M1_E2E) between adjacent endpoints of beta-coaligned M1_rte segments is approximately equal to the corresponding minimum distance (OA_gap_M0) between adjacent corresponding M0_rte segments, relative to the Y-axis. Generally, regarding segments in a metallization layer, as the end-to-end (E2E) distance decreases, it becomes increasingly difficult to segment / cut a longer precursor segment into two parts (whose adjacent endpoints are separated by a corresponding minimum E2E distance). At least in part due to one or more design rules disclosed herein, at least some embodiments use the minimum distance between adjacent endpoints of β-collinear M1_rte segments, namely gap_M1_E2E, to fabricate adjacent endpoints of β-collinear M1_rte segments, where gap_M1_E2E is substantially greater than the corresponding minimum distance OA_gap_M1_E2E; therefore, fabricating adjacent endpoints of β-collinear M1_rte segments is at least easier and / or cheaper than other methods.

[0057] In Figure 2D, and in other layout diagrams disclosed herein, each functional unit region (e.g., 206D(1)) is assumed to have a height equal to six α orbitals relative to the Y-axis, such that each functional unit region overlaps five α orbitals (e.g., α1-α5 in Figure 2D), i.e., five columns of M0_rte segments. In some embodiments, the functional unit regions have a height equal to or greater than four α orbitals, such that each functional unit region overlaps at least three α orbitals.

[0058] Assuming the α-orbital spacing is substantially the same, according to another method for manufacturing a device with a BSPD architecture, corresponding functional unit regions having a height equal to six α-orbitals overlap only four columns of corresponding M0_rte segments. At least in part due to one or more design rules disclosed herein, in some embodiments, functional unit regions having a height equal to six α-orbitals overlap five columns of M0_rte segments, achieving an additional column of M0_rte segments compared to the other method. In some embodiments, regarding the transistor gate density formed in a given functional unit region, the gate density G_dens achieved by a functional unit region having a height equal to six α-orbitals and overlapping five columns of M0_rte segments, in the range (≈1.04) ≤ G_dens ≤ (≈1.06), represents an improvement of approximately 4% to approximately 6% compared to a corresponding functional unit region having a height equal to six α-orbitals and overlapping only four columns of M0_rte segments according to the other method.

[0059] The differences between the first and second arrangements in Figure 2D include the following points. Regarding the reference line 214(1) extending parallel to the X-axis, all VD contact windows and half of the VG contact windows in functional unit regions 208D(1) and 206D(2) are mirror-symmetric with respect to the reference line 214(1). Exceptions to the VG / VD mirror symmetry between functional unit regions 208D(1) and 206D(2) include: the position of the VG contact window at the intersection of α track α10 and β track β7 in functional unit region 208D(1), and the position of the VG contact window at the intersection of α track α12 and β track β7 in functional unit region 206D(2); the position of the VG contact window at the intersection of α track α9 and β track β9 in functional unit region 208D(1), and the position of the VG contact window at the intersection of α track α14 and β track β9 in functional unit region 206D(2). Regarding the reference line 214(2) extending parallel to the X-axis, the V0 structure and the M1_rte segment are mirror-symmetric with respect to the reference line 214(2).

[0060] The differences between the first and second arrangements in Figure 2D also include the following points. The relative positions in functional unit regions 208D(1) and 206D(2) are relative to the upper and lower boundary backgrounds of functional unit regions 208D(1) and 206D(2), respectively. Although there are two α orbitals with α collinear M0_rte segments in each of functional unit regions 208D(1) and 206D(2), the relative positions of the two α orbitals (α7 and α9) in functional unit region 208D(1) are different from the relative positions of the two α orbitals (α12 and α13) in functional unit region 206D(2). Although the gaps between the collinear M0_rte segments of α orbit α7 in functional unit region 208D(1) and between the collinear M0_rte segments of α orbit α13 in functional unit region 206D(2) are aligned with β orbit β5, the gaps between the collinear M0_rte segments of α orbit α9 in functional unit region 208D(1) are aligned with β orbit β8, while the gaps between the collinear M0_rte segments of α orbit α12 in functional unit region 206D(2) are aligned with β orbit β6.

[0061] Figure 2E is a layout diagram of macro region 202E conforming to some embodiments.

[0062] Macro region 202E is a version of macro region 202D. Macro region 202E is an example of macro region 102 in Figure 1. In Figure 2E, section lines 4B-4B' extend parallel to the X-axis. In some embodiments, section lines 4B-4B' of Figure 2E correspond to section 420B of Figure 4B.

[0063] Comparing macro region 202E with macro region 202D, for simplicity, macro region 202E does not include the active region (AR), V0 structure, and M1_rte segment. In contrast, comparing macro region 202E with macro region 202D, macro region 202E also includes the cut-gate-segment (CG) shape and the cut-MD-contact (CMD) shape.

[0064] In Figure 2E, and in other layout diagrams disclosed here, gate segments aligned with the same β track are called beta-coaligned gate segments. Adjacent beta-coaligned gate segments are the result of cutting a longer precursor segment into two parts, the adjacent endpoints of which are separated by a corresponding minimum distance; the CG shape is used to indicate where the longer precursor segment (not shown) will be cut.

[0065] Relative to the Y-axis, adjacent endpoints of β-collinear gate segments are separated by a minimum distance h_CG, where h_CG also represents the height of the CG shape. In some embodiments, h_CG is approximately equal to p_M0_rte, such that h_CG ≈ p_M0_rte. According to another method of manufacturing a device with a BSPD architecture, the corresponding minimum distance (OA_h_CG) between adjacent endpoints of β-collinear counterpart gate segments is approximately equal to the corresponding minimum distance (OA_gap_M0) between adjacent corresponding M0_rte segments relative to the Y-axis. Generally, for segments in a metallization layer, as the end-to-end (E2E) distance decreases, it becomes increasingly difficult to cut a longer precursor segment into portions with adjacent endpoints separated by a corresponding minimum E2E distance. At least some embodiments use the minimum distance between adjacent endpoints of the β-collinear gate segment, i.e., h_CG, to manufacture adjacent endpoints of the β-collinear gate segment, where h_CG is significantly larger than the corresponding minimum distance OA_h_CG; therefore, manufacturing adjacent endpoints of the β-collinear gate segment is at least easier and / or less costly than another method.

[0066] In Figure 2E, and in other layout diagrams disclosed here, MD contact windows aligned with the same β track are referred to as β-collinear MD contact windows. Adjacent β-collinear MD contact windows are the result of cutting a longer precursor contact window into two parts, with the adjacent endpoints of these two parts separated by a corresponding minimum distance; the CMD shape is used to indicate where the longer precursor contact window (not shown) will be cut.

[0067] Relative to the Y-axis, adjacent endpoints of β-collinear MD contact windows are separated by a minimum distance h_CMD, where h_CMD also represents the height of the CMD shape. In some embodiments, h_CMD is approximately equal to p_M0_rte, such that h_CMD ≈ p_M0_rte. According to another method of manufacturing a device with a BSPD architecture, the corresponding minimum distance (OA_h_CMD) between adjacent endpoints of β-collinear corresponding MD contact windows is approximately equal to the corresponding minimum distance (OA_gap_M0) between adjacent corresponding M0_rte segments relative to the Y-axis. Generally, for segments in a metallization layer, as the end-to-end (E2E) distance decreases, it becomes increasingly difficult to cut a longer precursor segment into portions with adjacent endpoints separated by a corresponding minimum E2E distance. At least some embodiments use the minimum distance between adjacent endpoints of a β-collinear MD contact window, h_CMD, to manufacture adjacent endpoints of the β-collinear MD contact window, where h_CMD is significantly larger than the corresponding minimum distance OA_h_CMD; therefore, manufacturing adjacent endpoints of a β-collinear MD contact window is at least easier and / or less costly than another method.

[0068] In Figure 2E, the macro region is represented by the third and fourth design rules (DRs) that lead to the macro region 202D in Figure 2D, as described below.

[0069] Regarding Figure 2E, the third design rule relates to each first α track in functional unit regions 206D(1)-206D(2) and 208D(1). Within the context of functional unit regions 206D(1)-206D(2) and 208D(1), the first α tracks are referred to as the bottom α tracks. In functional unit regions 206D(1)-206D(2) and 208D(1), the bottom α tracks are assumed to be α tracks α5, α10, and α15. The third design rule specifies that the bottom α tracks must not have any CMD shapes aligned with them. In some embodiments, the third design rule is referred to as the CMD-non-grata-track design rule.

[0070] Regarding Figure 2E, the fourth design rule relates to each of the second α tracks in functional unit regions 206D(1)-206D(2) and 208D(1)-208(2). Within the context of functional unit regions 206D(1)-206D(2) and 208D(1), the second α track is referred to as the top α track. In functional unit regions 206D(1)-206D(2) and 208D(1)-208(2), the top α tracks are assumed to be α tracks α1, α6, and α11. The fourth design rule specifies that the top α track must not have any CG shape aligned with it. In some embodiments, the fourth design rule is referred to as the CG-non-grata-track design rule.

[0071] Figure 3A is a layout diagram of macro region 302A according to some embodiments.

[0072] Macro region 302A is an example of macro region 102 in Figure 1.

[0073] Macro region 302A includes functional (FN) cell regions (CR) 306A(1)-306A(2) and 308A(1)-308A(2) stacked relative to the Y-axis. Functional cell region (FN CR) 306A(2) is stacked on functional cell region 308A(2). Functional cell region 308A(1) is stacked on functional cell region 306A(2). Functional cell region 306A(1) is stacked on functional cell region 308A(1). Functional cell regions 306A(1)-306A(2) and 308A(1)-308A(2) are also described as being staggered relative to the Y-axis.

[0074] Each of the functional unit regions 306A(1)-306A(2) and 308A(1)-308A(2) is configured to perform a given function, such as AOI (see Figure 5A). That is, each of the functional unit regions 306A(1)-306A(2) and 308A(1)-308A(2) is configured to perform the same function.

[0075] Each of the functional unit regions 306A(1)-306A(2) and 308A(1)-308A(2) contains the following components (see Figures 3B to 3C): Gate segment (see Figures 3B to 3C); MD contact window (see Figures 2B and 2E); VG contact window (see Figures 2C to 2E); VD contact window (see Figures 2B and 2D to 2E); M0_rte segment; those M0_rte segments (M0_pin segments) that serve as input / output (pins) of the M0 segment; and V0 structure. In Figure 3A and other figures disclosed herein, the V0 structure is aligned with the corresponding α and β orbitals.

[0076] Functional unit areas 306A(1)-306A(2) are examples of a third element arrangement configured to perform a given function. Functional unit areas 308A(1)-306A(2) are examples of a fourth element arrangement configured to perform a given function.

[0077] In some embodiments, the third and fourth arrangements refer to the corresponding arrangements of the Gate segment, MD contact window, V0 contact window, and M0_pin segment. In some embodiments, the third and fourth arrangements refer to the corresponding arrangements of the Gate segment, MD contact window, V0 contact window, and M0_pin segment, plus the non-pin M0_rte segment.

[0078] Examples of the differences between the third and fourth permutations will be discussed below. Although the third and fourth permutations differ, they still share common characteristics. The first characteristic shared by the third and fourth permutations is that the VD structure is aligned with the corresponding even-numbered β orbital lines (e.g., β orbital lines β2-β10 in Figures 3D to 3E). The second characteristic shared by the third and fourth permutations is shown in Figures 3B to 3C.

[0079] Figures 3B and 3C are layout diagrams of corresponding functional unit regions 310B-310C according to some embodiments.

[0080] Regarding Figures 3B to 3C, each of the functional unit regions 310B and 310C is an example of functional unit regions 306A(1)-306A(2) and 308A(1)-308A(2) in Figure 3A. Functional unit regions 310B-310C are representations of the corresponding fifth and sixth design rules (DRs), which lead to the third and fourth permutations in Figure 3A, as described below.

[0081] Regarding Figures 3A and 3B, the fifth design rule relates to the first α track in functional unit regions 306D(1)-306D(2) and 308D(1)-308D(2) in Figure 3A and 310B in Figure 3B. In the context of functional unit regions 306D(1)-306D(2) and 308D(1)-308D(2) in Figure 3A and 310B in Figure 3B, the first α track is referred to as the bottom α track. In functional unit regions 306D(1)-306D(2) and 308D(1)-308D(2) in Figure 3A and 310B in Figure 3B, the bottom α track is assumed to be α track α5, α10, α15, α20. The fifth design rule specifies that the bottom α track must not be aligned with any V0 structure. In some embodiments, the fifth design rule is referred to as the V0-structure-non-grata-track design rule.

[0082] Regarding Figures 3A and 3C, the sixth design rule relates to the second α track in functional unit regions 306D(1)-306D(2) and 308D(1)-308D(2) in Figure 3A and 310C in Figure 3C. In the context of functional unit regions 306D(1)-306D(2) and 308D(1)-308D(2) in Figure 3A and 310C in Figure 3C, the second α track is referred to as the top α track. In functional unit regions 306D(1)-306D(2) and 308D(1)-308D(2) in Figure 3A and 310C in Figure 3C, the top α track is assumed to be α tracks α1, α6, α11, and α16. The sixth design rule specifies that the top α track must not have any M0_pin segments aligned with it. In some embodiments, the sixth design rule is referred to as the M0_pin-non-grata-track design rule.

[0083] In functional unit regions 306D(1)-306D(2) and 308D(1)-308D(2) in Figure 3A, and 310C in Figure 3C and 310B in Figure 3B, the V0 structure can be allowed to exist in the top α track and each inner α track located between the top α track and the bottom α track. For example, in each of Figures 3B to 3C, the inner α track is α track α2-α4. In other words, in functional unit regions 306D(1)-306D(2) and 308D(1)-308D(2) in Figure 3A, and 310C in Figure 3C and 310B in Figure 3B, each of the α tracks α1-α4 is a V0-permissible α track.

[0084] In functional unit regions 306D(1)-306D(2) and 308D(1)-308D(2) in Figure 3A, and in 310C and 310C in Figure 3C, the M0_pin segment is allowed to exist in the bottom α track and each inner α track. In other words, in functional unit regions 306D(1)-306D(2) and 308D(1)-308D(2) in Figure 3A, and in 310C and 310C in Figure 3C, each of the α tracks α2-α5 is an α track that allows M0_pin (M0_pin-permissible alpha track).

[0085] The second characteristic shared by the third and fourth permutations mentioned above in the discussion of Figure 3A is shown (again) in Figures 3B to 3C.

[0086] In each of the functional unit regions 310B and 310C, the V0 structure is permitted to exist in each internal α track, i.e., α tracks α2-α4 in each of Figures 3B to 3C. In each of the functional unit regions 310B and 310C, the M0_pin segment is permitted to exist in each internal α track, i.e., (again) α tracks α2-α4 in each of Figures 3B to 3C. Therefore, the third characteristic shared by the third and fourth arrangements is that the V0 structure and / or the M0_pin segment is permitted to exist in each of the α tracks α2-α4 in each of Figures 3B to 3C. In other words, as shown in Figures 3B to 3C, the third characteristic shared by the third and fourth arrangements is that each of the α tracks α2-α4 is an α track that allows V0 (V0-permissible alpha track) and an α track that allows M0_pin (M0_pin-permissible alpha track).

[0087] Figures 4A and 4B are corresponding cross-sections 420A-420B of the device portion according to some embodiments.

[0088] In some embodiments, the device portions of Figures 4A to 4B are examples of device portions based on the layout diagrams of Figures 2D to 2E. The devices of Figures 4A to 4B are examples of device 100 in Figure 1. In some embodiments, section 420A corresponds to section lines 4A-4A' in Figure 2D. In some embodiments, section 420B corresponds to section lines 4B-4B' in Figure 2E.

[0089] Figure 5A is a set of three layout diagrams according to some embodiments. Figures 5B to 5C are corresponding simple block diagrams according to some embodiments.

[0090] Figure 5A includes functional unit regions 506 and 508 and intermediate unit region 516. Figure 5B shows the spatial rearrangement in intermediate unit region 516 compared to functional unit region 506. Figure 5C shows the spatial rearrangement in functional unit region 508 compared to intermediate unit region 516.

[0091] Each of the functional unit regions 506 and 508 is configured to perform a given function. In the example of Figure 5A, each of the functional unit regions 506 and 508 is configured to perform the logical function of AND-OR-INVERT (AOI). That is, each of the functional unit regions 506 and 508 is configured to perform the same function, namely AOI.

[0092] In some embodiments, each of the functional cell regions 506 and 508 is configured as a D1 cell region of AOI 22. In some embodiments, DX of AOI 22 is an alphanumeric literal string intended to indicate that the corresponding cell region is an AOI cell region, where the drive intensity of the cell region is DX, and X is a multiple of the unit drive intensity D. In Figure 5A, it is assumed that X is 1, therefore X = 1.

[0093] Functional unit area 506 is an example of a first element arrangement configured to perform AOI functions. Functional unit area 508 is an example of a second element arrangement configured to perform AOI functions. The first and second arrangements facilitate the staggered / scattered stacking of the same arrangement relative to the Y-axis.

[0094] Regarding Figure 5B, it is necessary to recall that Figure 5B represents a spatial rearrangement in the intermediate unit region 516 compared to the functional unit region 506. The axis of symmetry is represented by a reference line 214(3) extending parallel to the X-axis. The reference line 214(3) is located approximately midway between orbits α3 and α4 relative to the Y-axis. Given that the character ρ represents the Greek letter rho, the rows ρ0-ρ4 of the functional unit region 506 are rotated around the reference line 214(3), resulting in rows ρ0'-ρ4' of the intermediate unit region 516.

[0095] Regarding Figure 5C, it is important to recall that Figure 5C represents a spatial rearrangement in functional unit region 508 compared to intermediate unit region 516. The VG contact window located at the intersection of row ρ4' and β track β7 is moved to the intersection of row ρ2' and β track β7. The gap between the collinear α segments M0_rte in row ρ3' (located between β tracks β7 and β9) is moved to the intersection of row ρ2' and β track β6. Row ρ4' is moved from its collinear position with α track α0 to its original position, i.e., collinear with α track α6, forming row ρ4''. The VG contact window located at the intersection of row ρ3' and β track β9 is moved to the intersection of row ρ4'' and β track β9.

[0096] Figure 6 is a flowchart (flowchart) of a method 600 for manufacturing a system or apparatus according to some embodiments.

[0097] Method 600 may be implemented, for example, using an electronic design automation (EDA) system 800 (Figure 8, discussed below) and an IC manufacturing system 900 (Figure 9, discussed below), according to some embodiments. Examples of systems or devices including functional unit regions that can be manufactured according to method 600 include the systems or devices including functional unit regions disclosed herein.

[0098] In Figure 6, method 600 includes blocks 602-604. In block 602, a layout diagram is generated, including one or more layout diagrams corresponding to one or more functional unit regions, one or more macro regions, or the like disclosed herein. According to some embodiments, block 602 may be implemented, for example, using EDA system 800 (Figure 8, discussed below). From block 602, the process proceeds to block 604.

[0099] In block 604, based on the layout diagram, at least one of the following is performed: (i) performing one or more lithography exposures, or (ii) fabricating one or more lithography masks, or (iii) fabricating one or more components in a layer of an apparatus, such as fabricating an apparatus. See the following discussion of the IC manufacturing system 900 in Figure 9.

[0100] Figures 7A and 7B are corresponding portions of a flowchart of a method 700 for manufacturing an apparatus according to some embodiments.

[0101] Method 700 is an example of block 604 (see Figure 6 discussed above). According to some embodiments, method 700 may be implemented, for example, using IC manufacturing system 900 (see Figure 9 discussed below). Examples of devices that can be manufactured according to method 700 include devices having one or more functional cell regions disclosed herein, one or more macro regions disclosed herein, or the like. Method 700 includes blocks 710-744.

[0102] In block 710, an active region extending in a first direction (e.g., parallel to the X-axis) is formed (e.g., see Figures 2D and 4A to 4B). From block 710, the process proceeds to block 712.

[0103] In block 712, gate segments are formed (e.g., see Figures 2A to 2E and Figures 4A to 4B). These gate segments extend in a second direction perpendicular to the first direction (e.g., parallel to the Y-axis), intersect each other, and have portions covering the active region. From block 712, the process proceeds to block 714.

[0104] In block 714, MD contact windows are formed (e.g., see Figures 2E and 4A-4B). These MD contact windows extend in the second direction, intersect each other, and have portions covering the active area. From block 714, the process proceeds to block 716.

[0105] In block 716, a VG contact window is formed in the region of the gate segment (see, for example, Figures 2C-2E and 4A-4B). Block 716 includes blocks 718-720. Within block 716, the process proceeds to block 718.

[0106] In block 718, the VG contact window is positioned to align with the corresponding α track, except for the first α track (e.g., see α tracks α1, α6, α11, and α16 in Figures 2A to 2C, respectively), which has no VG contact window aligned with it. From block 718, the process proceeds to block 720.

[0107] In block 720, adjacent collinear β-VG contact windows are spaced apart by a distance gap_VG (e.g., see Figure 2D). From block 720, the process leaves block 716 and proceeds to block 722.

[0108] In block 722, a VD contact window is formed in the area of ​​the MD contact window (see, for example, Figures 2C-2E and 4A-4B). Block 722 includes blocks 724-726. Within block 722, the process proceeds to block 724.

[0109] In block 724, the VD contact window is positioned to align with the corresponding α track, except for the last α track (e.g., see α tracks α5, α10, α15, and α20 in Figures 2A to 2E, respectively), which has no VD contact window aligned with it. From block 724, the process proceeds to block 726.

[0110] In block 726, adjacent collinear β-VD contact windows are spaced apart by a distance gap_VD (e.g., see Figure 2D). From block 726, the process leaves block 722 and proceeds to block 728.

[0111] In block 728, within the first metallization layer (e.g., see METO in Figures 4A-4B), MO_rte segments (e.g., see Figures 2B-2E, 3B-3C, and 4A-4B) are formed. These MO_rte segments extend in a first direction (e.g., parallel to the X-axis), correspondingly aligned with α orbitals (e.g., see α0, α1, ...), and correspondingly located above the VG contact window or VD contact window. Block 728 includes blocks 730-732. Within block 728, the process proceeds to block 730.

[0112] In block 730, adjacent M0_rte segments are spaced apart relative to the Y-axis by a distance p_M0_rte (see, for example, Figure 2D). From block 730, the process proceeds to block 732.

[0113] In block 732, the M0_pins, i.e., the pins of the M0_rte segment, are positioned to align with the corresponding α track, except for the first α track (e.g., see α track α1 in FIG. 3C), which has no M0_pin segment contact window aligned with it. From block 732, the process leaves block 728 and proceeds to the page connector block 733. From the page connector block 733 in FIG. 7A, the process proceeds to the page connector block 733 in FIG. 7B.

[0114] In Figure 7B, the process proceeds from the cross-page connector block 733 to the block 734.

[0115] In block 734, within the first embedded metallization layer (e.g., see BMETO in Figures 4A-4B), BMO_PG segments are formed (e.g., see Figures 2D-2E and 4A-4B), extending in a first direction (e.g., parallel to the X-axis). From block 734, the process proceeds to block 736.

[0116] In block 736, the V0 structure (e.g., see Figures 2D, 3B, and 4A) is formed above the region of the M0_rte segment and aligned with the corresponding β orbital (e.g., see β4). Block 736 includes blocks 738-740. Within block 736, the process proceeds to block 738.

[0117] In block 738, the V0 structure is positioned to align with the corresponding α track, except for the last α track (e.g., see the corresponding α tracks α5, α10, α15, and α20 in Figures 2D, 3A, and 3C), which has no V0 structure aligned with it. From block 738, the process proceeds to block 740.

[0118] In block 740, adjacent collinear β-V0 structures are spaced apart by a distance gap_V0 (see, for example, Figure 2D). From block 740, the process leaves block 736 and proceeds to block 742.

[0119] In block 742, within the second metallization layer (e.g., see MET1 in Figures 4A-4B), M1_rte segments (e.g., see Figures 2D and 4A) are formed. These M1_rte segments extend in a second direction (e.g., parallel to the Y-axis), correspondingly aligned with the β orbitals (e.g., see β4), and correspondingly located above the V0 structure. Block 742 includes block 744. Within block 742, the process proceeds to block 744.

[0120] In block 744, relative to the Y-axis, the adjacent endpoints of the M1_rte segment are spaced apart by a distance gap_M1_E2E from each other (see, for example, Figure 2D).

[0121] Figure 8 is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0122] In some embodiments, EDA system 800 includes an automatic placement and routing (APR) system. In some embodiments, EDA system 800 is a general-purpose computing device including processor 802 (e.g., a hardware processor) and non-transitory computer-readable storage medium 804. The computer-readable storage medium 804 is, among other things, encoded, i.e., storing computer program code 806, i.e., a set of executable instructions. Processor 802 executes instructions 806 representing (at least partially) an EDA tool that implements some or all of, for example, one or more methods, or similar methods (hereinafter referred to as the processes and / or methods), according to one or more embodiments, for generating layouts corresponding to the layouts disclosed herein.

[0123] The computer-readable storage medium 804, among others, stores a layout diagram 811, such as the layout diagram disclosed herein, or other similar layout diagrams.

[0124] Processor 802 is electrically coupled to computer-readable storage medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is also electrically connected to processor 802 via bus 808. Network interface 812 is connected to network 814 so that processor 802 and computer-readable storage medium 804 can be connected to external components via network 814. Processor 802 is configured to execute computer program code 806 encoded in computer-readable storage medium 804 to enable EDA system 800 to perform some or all of the aforementioned processes and / or methods. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0125] In one or more embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, portable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disc. In one or more embodiments using optical discs, the computer-readable storage medium 804 includes a compact disk-read-only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disc (DVD).

[0126] In one or more embodiments, the computer-readable storage medium 804 stores instructions, i.e., computer program code 806, configured to make the EDA system 800 (where such execution (at least partially) represents an EDA tool) available to perform some or all of the mentioned processes and / or methods. In one or more embodiments, the computer-readable storage medium 804 also stores information that facilitates the execution of some or all of the mentioned processes and / or methods. In one or more embodiments, the computer-readable storage medium 804 stores a standard cell library 807, including standard cells corresponding to the layout elements disclosed herein. The computer-readable storage medium 804 stores one or more layout diagrams 816, such as one or more layout diagrams corresponding to the layout diagrams disclosed herein, one or more compiled macros 817 based on the layout diagrams including one or more layout diagrams disclosed herein, or the like.

[0127] EDA system 800 includes an I / O interface 810. The I / O interface 810 is coupled to external circuitry. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 802.

[0128] EDA system 800 also includes a network interface 812 coupled to processor 802. Network interface 812 allows EDA system 800 to communicate with network 814, to which one or more other computer systems are connected. Network interface 812 includes a wireless network interface, such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more EDA systems 800.

[0129] EDA system 800 is configured to receive information through I / O interface 810. The information received through I / O interface 810 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 802. The information is transmitted to processor 802 via bus 808. EDA system 800 is also configured to receive information related to the user interface (UI) through I / O interface 810. This information is stored as user interface (UI) 842 on computer-readable medium 804.

[0130] In some embodiments, part or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application used by an EDA system 800. In some embodiments, a layout diagram containing standard cells is generated using tools such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS or other suitable layout generation tools.

[0131] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of the following: optical discs, such as DVDs; magnetic disks, such as hard disks; semiconductor memory, such as ROM, RAM, memory cards; and the like.

[0132] Figure 9 is a block diagram of an integrated circuit (IC) manufacturing system 900 and its associated IC manufacturing process according to some embodiments.

[0133] In some embodiments, based on the layout diagram generated by block 702 of FIG7, IC manufacturing system 900 implements block 704 of FIG7, wherein the manufacturing system 900 manufactures at least one of the following: (A) one or more semiconductor masks or (B) at least one element in a layer of unfinished semiconductor integrated circuitry. In some embodiments, IC manufacturing system 900 implements the flowchart of FIG5, or a similar process.

[0134] In Figure 9, the IC manufacturing system 900 includes entities that interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacturing of IC device 960, such as design end 920, mask manufacturing end 930, and IC manufacturer / fab (“fab”) 950. The entities in the IC manufacturing system 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design end 920, mask manufacturing end 930, and IC fabrication plant 950 are owned by a single larger company. In some embodiments, two or more of the design end 920, mask manufacturing end 930, and IC fabrication plant 950 coexist in a shared facility and use shared resources.

[0135] The design end (or design team) 920 generates an IC design layout 922. The IC design layout 922 includes various geometric patterns designed for an IC device 960. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device 960 to be manufactured. The layers are combined to form various IC features. For example, a portion of the IC design layout 922 includes various IC features to be formed on a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate, such as active regions, gate terminals, sources and drains, metal lines or vias for interlayer interconnects, and openings for bonding pads. Source / drain regions may refer to sources or drains, individually or collectively, depending on the context. The design end 920 performs appropriate design procedures to form the IC design layout 922. These design procedures include one or more of logic design, physical design, or positioning and routing. The IC design layout 922 is presented in one or more files containing geometric pattern information. For example, the IC design layout 922 is represented in GDSII or DFII file format.

[0136] Mask manufacturing end 930 includes mask data preparation 932 and mask manufacturing 934. Mask manufacturing end 930 uses IC design layout 922 to manufacture one or more masks 935 for manufacturing various layers of IC device 960 according to IC design layout 922. Mask manufacturing end 930 performs mask data preparation 932, wherein IC design layout 922 is converted into a representative data file (“RDF”). Mask data preparation 932 provides the RDF to mask manufacturing 934. Mask manufacturing 934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mesh) or semiconductor wafer. The design layout is manipulated by mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of IC manufacturing plant 950. In FIG. 9, mask data preparation 932, mask manufacturing 934, and mask 935 are shown as separate elements. In some embodiments, mask data preparation 932 and mask manufacturing 934 are collectively referred to as mask data preparation.

[0137] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, or other process effects. OPC adjusts the IC design layout 922. In some embodiments, mask data preparation 932 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution adjustment features, phase-shift masking, other fitting techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is further used, which treats OPC as a reverse imaging problem.

[0138] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout that has already undergone the process in OPC. These rules include certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask manufacturing 934, which may offset portions of the modifications performed by OPC to meet the mask creation rules.

[0139] In some embodiments, mask data preparation 932 includes lithography process checking (LPC), which simulates the process performed by IC manufacturer 950 to manufacture IC device 960. LPC simulates this process based on IC design layout 922 to manufacture a simulated device, such as IC device 960. Processing parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other patterns of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, or combinations thereof. In some embodiments, after manufacturing the simulated device using LPC, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 922.

[0140] It should be understood that the above description of mask data preparation 932 has been simplified for clarity. In some embodiments, mask data preparation 932 includes additional features such as logic operations (LOPs) to modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to the IC design layout 922 during data preparation 932 can be performed in various different sequences.

[0141] After mask data preparation 932 and during mask manufacturing 934, a mask 935 or a set of masks 935 is manufactured based on a modified IC design layout. In some embodiments, an electron beam (e-beam) or multiple electron beam mechanisms are used to form a pattern on the mask (photomask or intermediate mask) based on the modified IC design layout. The mask is formed using various techniques. In some embodiments, a binary technique is used to form the mask. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and transmits through the transparent areas. In an example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the mask. In another example, a phase-shifting technique is used to form the mask. In a phase-shift mask (PSM), various features in the pattern formed on the mask are configured to have an appropriate phase difference to improve resolution and image quality. In various examples, the phase-shift mask is a decaying PSM or an alternating PSM. Masks generated by mask fabrication 934 are used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafers, in etching processes to form various etched regions in semiconductor wafers, and / or in other suitable processes.

[0142] IC manufacturing plant 950 is an IC manufacturing enterprise, including one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC manufacturing plant 950 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end-of-line (FEOL) manufacturing of a plurality of IC products, while a second manufacturing facility may provide back-end-of-line (BEOL) manufacturing for the interconnects and packaging of IC products, and a third manufacturing facility may provide other services for foundry operations.

[0143] IC manufacturing plant 950 uses a mask 935 manufactured by mask manufacturing end 930 to manufacture IC device 960 using manufacturing tool 952. Therefore, IC manufacturing plant 950 at least indirectly uses IC design layout 922 to manufacture IC device 960. In some embodiments, semiconductor wafer 953 is manufactured by IC manufacturing plant 950 using mask 935 to form IC device 960. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate having a material layer formed thereon. The semiconductor wafer further includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0144] In some embodiments, the cell region includes: an active region extending along a first direction; gate segments and metal-to-source / drain (MD) contact windows extending along a second direction perpendicular to the first direction, intersecting each other and having portions located above the active region; via-to-gate (VG) contact windows located above the gate segment regions; via-to-MD (VD) contact windows located above the MD contact window regions; VG and VD contact windows respectively aligned with α tracks extending along the first direction; a first wiring (RTE) segment extending along the first direction in a first metallization layer on a first side of the active region, aligned with the α tracks, and located above the VG or VD contact windows respectively; and a first embedded power grid segment extending along the first direction in a first embedded metallization layer on a second side of the active region; and a first α track and a second α track in the α tracks are respectively adjacent to the first and second boundaries of the cell region; at least a third α track is located between the first and second α tracks; the first α track has no VG contact windows aligned with it; and the second α track has no VD contact windows aligned with it.

[0145] In some embodiments, the gate segments are aligned with β tracks extending along a second direction; adjacent gate segments are spaced apart from each other by a first spacing relative to the first direction; adjacent first RTE segments are spaced apart from each other by a second spacing relative to the second direction; and with respect to those VD contact windows aligned to the same β track (β co-aligned VD contact windows), adjacent β co-aligned VD contact windows are spaced apart from each other by a gap having a size that is approximately equal to or greater than the smaller of the first spacing or twice the second spacing.

[0146] In some embodiments, the gate segments are aligned with β tracks extending along a second direction; adjacent gate segments are spaced apart from each other by a first spacing relative to the first direction; adjacent first RTE segments are spaced apart from each other by a second spacing relative to the second direction; with respect to those VG contact windows aligned to the same β track (β co-aligned VG contact windows), adjacent β co-aligned VG contact windows are spaced apart from each other by a gap having a size that is approximately equal to or greater than the smaller of the first spacing or twice the second spacing.

[0147] In some embodiments, the cell region further includes: a first contact window in the first interconnect layer, corresponding to the α track and located above the first RTE segment, wherein: one or more first RTE segments are first input / output (pin) segments; the first α track has no first pin segment aligned with it, and the second α track has no first contact window aligned with it.

[0148] In some embodiments, the gate segments are aligned with β tracks extending along a second direction; adjacent gate segments are spaced apart from each other by a first spacing relative to the first direction; adjacent first RTE segments are spaced apart from each other by a second spacing relative to the second direction; with respect to those first contact windows aligned to the same β track (β co-aligned first contact windows), adjacent β co-aligned first contact windows are spaced apart from each other by a gap having a size that is approximately equal to or greater than the smaller of the first spacing or twice the second spacing.

[0149] In some embodiments, the unit region further includes: in the second metallization layer, a second RTE segment extending along a second direction, correspondingly aligned with the β track and respectively located above the first contact window, wherein: adjacent first RTE segments are spaced apart from each other by a first spacing relative to the second direction; with respect to those second RTE segments aligned to the same β track (β co-aligned second RTE segments), adjacent endpoints of the β co-aligned second RTE segments are spaced apart from each other by a first gap equal to or greater than the first spacing.

[0150] In some embodiments, the gate segment, MD contact window, VG contact window, and VD contact window of the cell region may be arranged in a first arrangement or a second arrangement; and when arranged according to the first arrangement or the second arrangement, the cell region is configured to perform the same function.

[0151] In some embodiments, when arranged according to a first arrangement or a second arrangement, the cell region is configured to perform the same AND-OR-INVERT (AOI) function.

[0152] In some embodiments, the unit region of the device includes: an active region extending along a first direction; gate segments and metal-to-source / drain (MD) contact windows extending along a second direction perpendicular to the first direction, staggered and partially located above the active region; via-to-gate (VG) contact windows located above the gate segments; via-to-MD (VD) contact windows located above the MD contact windows; VG and VD contact windows correspondingly aligned with α tracks extending along the first direction; and in a first metallization layer on a first side of the active region, extending along the first direction, correspondingly aligned with the α tracks, and located above the VG or VD contact windows respectively. The first wiring (RTE) segment, and one or more first RTE segments are first input / output (pin) segments; and in the first interconnect layer, a first contact window corresponding to the α track and located above the first RTE segment; in the first buried metallization layer on the second side of the active region, a first buried power grid segment extending along a first direction; and the first and second α tracks are respectively adjacent to the first and second boundaries of the cell region; at least one third α track is located between the first and second α tracks; the first α track has no VG contact window and no first pin segment aligned with it; and the second α track has no VD contact window and no first contact window aligned with it.

[0153] In some embodiments, the gate segments are aligned with β tracks extending along a second direction; adjacent gate segments are spaced apart from each other by a first spacing relative to the first direction; adjacent first RTE segments are spaced apart from each other by a second spacing relative to the second direction; and with respect to those VD contact windows aligned to the same β track (β co-aligned VD contact windows), adjacent β co-aligned VD contact windows are spaced apart from each other by a gap of approximately equal to or greater than the smaller of the first spacing or twice the second spacing.

[0154] In some embodiments, the gate segments are aligned with β tracks extending along a second direction; adjacent gate segments are spaced apart from each other by a first spacing relative to the first direction; adjacent first RTE segments are spaced apart from each other by a second spacing relative to the second direction; and with respect to those VG contact windows aligned to the same β track (β co-aligned VG contact windows), adjacent β co-aligned VG contact windows are spaced apart from each other by a gap of approximately equal to or greater than the smaller of the first spacing or twice the second spacing.

[0155] In some embodiments, the gate segments are aligned with β tracks extending along a second direction; adjacent gate segments are spaced apart from each other by a first spacing relative to the first direction; adjacent first RTE segments are spaced apart from each other by a second spacing relative to the second direction; with respect to those first contact windows aligned to the same β track (β co-aligned first contact windows), adjacent β co-aligned first contact windows are spaced apart from each other by a gap of approximately equal to or greater than the smaller of the first spacing or twice the second spacing.

[0156] In some embodiments, the cell region further includes: in the second metallization layer, a second RTE segment extending along a second direction, corresponding to an alignment with a β track, and correspondingly located above a first contact window, wherein: adjacent first RTE segments are spaced apart from each other by a first spacing relative to the second direction; with respect to those second RTE segments aligned to the same β track (β co-aligned second RTE segments), adjacent endpoints of the β co-aligned second RTE segments are spaced apart from each other by a first gap equal to or greater than the first spacing.

[0157] In some embodiments, the gate segment, MD contact window, VG contact window, and VD contact window of the cell region may be arranged in a first arrangement or a second arrangement; and when arranged according to the first arrangement or the second arrangement, the cell region is configured to perform the same function.

[0158] In some embodiments, a method (for forming a unit region of the device) includes: forming an active region extending along a first direction; forming a gate segment having a portion located above the first region of the active region in a second direction perpendicular to the first direction, and forming metal-to-source / drain region (MD) contact windows intersecting the gate segment, the MD contact windows having a portion located above the second region of the active region; forming a via-to-gate (VG) contact window located above the gate segment region; forming a via-to-MD (VD) contact window located above the MD contact window region; the VG contact window and the VD contact window being correspondingly aligned with an α track extending along the first direction; and forming a metallization layer on a first side of the active region. A first wiring (RTE) segment extending along a first direction, correspondingly aligned with an α track and located above a VG contact window or a VD contact window; a first embedded power grid segment extending along the first direction is formed in a first embedded metallization layer on the second side of the active region; and the first and second α tracks are respectively adjacent to the first and second boundaries of the cell region; at least one third α track is located between the first and second α tracks; forming a via-to-gate (VG) contact window includes the step of positioning the VG contact window such that no VG contact window aligns with the first α track; and forming a via-to-MD (VD) contact window includes the step of positioning the VD contact window such that no VD contact window aligns with the second α track.

[0159] In some embodiments, forming a gate segment includes the steps of aligning the gate segment with a corresponding β track extending along a second direction and separating adjacent gate segments with a first spacing relative to a first direction; forming a metal-to-source / drain region (MD) contact window includes the steps of separating adjacent first RTE segments with a second spacing relative to the second direction; and forming a via-to-MD contact window (VD) contact window includes the steps of aligning corresponding VD contact windows to the same β track to cause β co-aligned VD contact windows and separating adjacent β co-aligned VD contact windows with a gap of approximately equal to or greater than the smaller of the first spacing or twice the second spacing.

[0160] In some embodiments, forming a gate segment includes the steps of aligning the gate segment with a corresponding β track extending along a second direction and separating adjacent gate segments with a first spacing relative to a first direction; forming a first wiring (RTE) segment includes the steps of separating adjacent first RTE segments with a second spacing relative to a second direction; and forming a via-to-gate (VG) contact window includes the steps of aligning corresponding VG contact windows to the same β track to cause β co-aligned VG contact windows and separating adjacent β co-aligned VG contact windows with a gap of approximately equal to or greater than the smaller of the first spacing or twice the second spacing.

[0161] In some embodiments, the method further includes: forming a first contact window in a first interconnect layer that corresponds to an α track and is located above a first RTE segment, wherein: forming the first wiring (RTE) segment includes forming one or more first input / output (pin) segments; forming one or more first input / output (pin) segments includes positioning one or more first pin segments such that no first pin segment aligns with the first α track; and forming the first contact window includes positioning the first contact window such that no first contact window aligns with the second α track.

[0162] In some embodiments, forming a gate segment includes the steps of aligning the gate segment with a corresponding β track extending along a second direction and separating adjacent gate segments with a first spacing relative to a first direction; forming a first wiring (RTE) segment includes the steps of separating adjacent first RTE segments with a second spacing relative to a second direction; and forming a first contact window includes the steps of aligning a corresponding first contact window to the same β track causing β to co-align the first contact window and separating adjacent β co-aligned first contact windows with a gap of approximately equal to or greater than the smaller of the first spacing or twice the second spacing.

[0163] In some embodiments, the method further includes: forming a second RTE segment extending along a second direction, correspondingly aligned with a β track and correspondingly located above a first contact window in a second metallization layer, wherein: forming a first wiring (RTE) segment includes the step of separating adjacent first RTE segments with a first spacing relative to the second direction; and forming a second RTE segment includes the step of aligning corresponding second RTE segments to the same β track to cause β co-aligned second RTE segments, and separating adjacent endpoints of β co-aligned second RTE segments with a first gap equal to or greater than the first spacing.

[0164] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages described above. Upon reading the foregoing specification, those skilled in the art will be able to implement various variations, equivalent substitutions, and various other embodiments widely disclosed herein. Therefore, the protection granted herein is intended to be limited only to the definitions contained in the appended claims and their equivalents.

[0165] 100: Device 102, 202A, 202D, 202E, 302A: Macro areas 104: Functional Unit Area 206A(1), 206A(2), 206D(1), 206D(2), 208A(1), 208A(2), 208D(1), 214(1), 214(2), 214(3), 306A(1), 306A(2), 308A(1), 308A(2), 210B, 210C, 310B, 310C, 506, 508: Functional unit areas 420A, 420B: Sections 516: Intermediate Unit Area 600, 700: Method 602, 604, 710, 712, 714, 716, 718, 720, 722, 724, 726, 728, 730, 732, 733, 734, 736, 738, 740, 742, 744: squares 800: EDA System 802: Processor 804: Computer-readable storage media 806: Computer program code, instructions 807: Standard Cell Library 808: Busbar 810:I / O interface 812: Network Interface 814: Internet 816: Layout Diagram 817: Compilation Macros 900: IC Manufacturing System 920: Design End 922: IC Design Layout 930: Mask manufacturing end 932: Masking Data Preparation 934: Mask Manufacturing 935: Mask 950: IC manufacturing plant 952: Manufacturing Tools 953 semiconductor wafer 960: IC device FN CR: Functional Unit α0, α2, α3, α4, α5, α6, α7, α8, α9, α10, α11, α12, α13, α14, α15, α16, α17, α18, α19, α20, α21: α orbit β0, β1, β2, β3, β4, β5, β6, β7, β8, β9, β10, β11, β12: β orbitals ρ0, ρ1, ρ2, ρ3, ρ4, ρ0', ρ1', ρ2', ρ3', ρ4', ρ4'': row IDG: Isolate virtual gate Gate: gate MD: Metal to source / drain region M1: Metallization segment in the MET1 layer M0_rte: The wiring segment of segment M0 M1_rte: Wiring segment in segment M1 M0_pin: Input / output pin for segment M0 VD: Through-hole to MD contact window VG: Through-hole to gate section V0: Through-hole structure in the first interconnect layer (VIA0) AR: Active Region The power grid (PG) in segment BM0_PG:0 CMD: Cut MD CG: Cutting the gate gap_VD: The minimum distance between adjacent collinear β-VD contact windows. gap_V0: The minimum distance between adjacent collinear β-structures V0. gap_M1_E2E: The minimum distance between adjacent endpoints of the collinear M1_rte segment. gap_VG: The minimum distance between adjacent collinear β-VG contact windows. p_gate: The uniform distance / spacing between gate segments. p_M0_rte: The uniform distance / spacing between M0_rte segments h_CMD: Minimum distance between adjacent endpoints of β-collinear MD contact windows h_CG: Minimum distance between adjacent endpoints of the β collinear gate segment BMET0: Embedded metallization layer zero BVD: Buried via to source / drain region MET0: Metallization layer zero MET1: Metallization layer 1 VIA0: Internal interconnect layer zero 4A-4A', 4B-4B': Section lines

Claims

1. A unit region of an apparatus, the unit region comprising: The active region extends along the first direction; The gate segment and the metal-to-source / drain-region (MD) contact window extend along a second direction perpendicular to the first direction, intersect each other, and have a portion located above the region of the active region; A via-to-gate (VG) contact window is located above the region of the gate segment; a via-to-MD-contact (VD) contact window is located above the region of the MD contact window; the VG contact window and the VD contact window are respectively aligned with an α track extending in the first direction; a first wiring (RTE) segment extends in the first metallization layer on the first side of the active region along the first direction, is respectively aligned with the α track, and is respectively located above the VG contact window or the VD contact window; And a first embedded power grid segment, in a first embedded metallization layer on the second side of the active region, extending along the first direction, wherein: the first α track and the second α track in the α track are adjacent to the first boundary and the second boundary of the cell region, the third α track, the fourth α track and the fifth α track in the α track are located between the first α track and the second α track, the first α track has no VG contact window aligned with it, but has a VD contact window aligned with it, the second α track has no VD contact window aligned with it, and the third α track, the fourth α track and the fifth α track each have a VG contact window aligned with it, or a VD contact window aligned with it.

2. The cell region as described in claim 1, wherein: The gate segment is correspondingly aligned with the β orbital extending in the second direction; adjacent gate segments are spaced apart from each other by a first spacing relative to the first direction; adjacent first RTE segments are spaced apart from each other by a second spacing relative to the second direction. And for VD contact windows aligned with the same β track in the β track (β collinear VD contact windows), adjacent β collinear VD contact windows are spaced apart from each other by a gap, the size of which is approximately equal to or greater than the smaller of the first gap or twice the second gap.

3. The cell region as described in claim 1, wherein: The gate segment is correspondingly aligned with the β track extending in the second direction; adjacent gate segments are spaced apart from each other by a first spacing relative to the first direction; adjacent first RTE segments are spaced apart from each other by a second spacing relative to the second direction; for VG contact windows aligned with the same β track in the VG contact window (β collinear VG contact windows), adjacent β collinear VG contact windows are spaced apart from each other by a gap, the size of which is approximately equal to or greater than the smaller of the first spacing or twice the second spacing.

4. The unit region as described in claim 1, further comprising: The first contact window, in the first interconnect layer, is correspondingly aligned with the α track and correspondingly located above the first RTE segment; And wherein: one or more of the first RTE segments are first input / output (pin) segments; the first α track has no first pin segment aligned with it, and the second α track has no first contact window aligned with it.

5. The cell region as described in claim 4, wherein: The gate segment is correspondingly aligned with the β track extending in the second direction; adjacent gate segments are spaced apart from each other by a first spacing relative to the first direction; adjacent first RTE segments are spaced apart from each other by a second spacing relative to the second direction; for first contact windows (β collinear first contact windows) aligned with the same β track in the first contact window, adjacent β collinear first contact windows are spaced apart from each other by a gap, the size of which is approximately equal to or greater than the smaller of the first spacing or twice the second spacing.

6. The unit region as described in claim 4, further comprising: The second RTE segment, in the second metallization layer, extends in the second direction, is aligned with the β orbital accordingly, and is located above the first contact window accordingly; And wherein: relative to the second direction, adjacent first RTE segments are spaced apart from each other by a first gap; for second RTE segments aligned with the same β orbit in the second RTE segment (β-collinear second RTE segments), adjacent endpoints of the β-collinear second RTE segments are spaced apart from each other by a first gap, the first gap being equal to or greater than the first spacing.

7. The cell region as described in claim 1, wherein: The gate segment, the MD contact window, the VG contact window, and the VD contact window of the unit region can be arranged in a first arrangement or a second arrangement; and when arranged according to the first arrangement or the second arrangement, the unit region is configured to perform the same function.

8. A unit region of an apparatus, the unit region comprising: The active region extends along the first direction; The gate segment and the metal-to-source / drain-region (MD) contact window extend along a second direction perpendicular to the first direction, intersect each other, and have a portion located above the region of the active region; A via-to-gate (VG) contact window is located above the region of the gate segment; a via-to-MD-contact (VD) contact window is located above the region of the MD contact window; the VG contact window and the VD contact window are respectively aligned with an α track extending along the first direction; a first wiring (RTE) segment is located in a first metallization layer on a first side of the active region, extending along the first direction, respectively aligned with the α track, and respectively located above the VG contact window or the VD contact window, wherein one or more of the first RTE segments are first input / output (pin) segments; a first contact window is located in a first interconnect layer, respectively aligned with the α track, and respectively located above the first RTE segment; a first embedded power grid segment is located in a first embedded metallization layer on a second side of the active region, extending along the first direction, wherein: the first α track and the second α track in the α track are adjacent to the first boundary and the second boundary of the cell region. The third, fourth, and fifth α tracks are located between the first and second α tracks; the first α track has no VG contact window and the first pin segment aligned with it, but has a VD contact window aligned with it; and the second α track has no VD contact window and the first contact window aligned with it, and the third, fourth, and fifth α tracks each have a VG contact window aligned with it, or a VD contact window aligned with it.

9. A method for forming a unit region of an apparatus, the method comprising: Forming an active region extending along the first direction; In a second direction perpendicular to the first direction, a gate segment is formed, the gate having a portion above a first region of the active region, and a metal-to-source / drain-region (MD) contact window is formed, the MD contact window interleaving with the gate segment and having a portion above a second region of the active region; a via-to-gate (VG) contact window is formed above the region of the gate segment; a via-to-MD-contact (VD) contact window is formed above the region of the MD contact window; the VG contact window and the VD contact window are respectively aligned with an α track extending along the first direction; in a first metallization layer on the first side of the active region, a first wiring (RTE) segment is formed, extending along the first direction, respectively aligned with the α track, and respectively located above the VG contact window or the VD contact window; in a first embedded metallization layer on the second side of the active region, A first embedded power grid segment extending along the first direction is formed; and the first and second α tracks in the α tracks are adjacent to the first and second boundaries of the unit region; the third, fourth, and fifth α tracks in the α tracks are located between the first and second α tracks; The process of forming a via to a gate (VG) contact window and forming a via to an MD (VD) contact window includes the following steps: positioning the VG contact window such that the first α track has no VG contact window aligned with it; positioning the VD contact window such that the second α track has no VD contact window aligned with it, and the first α track has a VD contact window aligned with it; and positioning the VG contact window and positioning the VD contact window such that the third α track, the fourth α track, and the fifth α track each have a VG contact window aligned with it, or a VD contact window aligned with it.

10. The method as described in claim 9, wherein: The formation of the gate segment includes the following steps: aligning the gate segment accordingly with a β track extending along the second direction, and spacing adjacent gate segments apart from each other with a first spacing relative to the first direction; The formation of the MD contact window includes the following steps: spacing adjacent first RTE segments apart from each other with a second spacing relative to the second direction. The formation of the VD contact window includes the following steps: aligning corresponding VD contact windows in the VD contact windows with the same β track in the β track to generate β collinear VD contact windows, and spacing adjacent β collinear VD contact windows apart from each other with a gap, the size of which is approximately equal to or greater than the smaller of the first gap or twice the second gap.

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