Semiconductor memory devices

Abstract

According to an embodiment, a semiconductor memory device having a plurality of first memory cells and a first selection mechanism is provided. The plurality of first memory cells are stacked on top of a substrate. The plurality of first memory cells are connected in parallel between a first vertical bit line and a first vertical source line. The first vertical bit line extends along the stacking direction. The first vertical source line extends along the stacking direction. The first selection mechanism is disposed between the substrate and the plurality of first memory cells in the stacking direction. The first selection mechanism selectively connects the first vertical bit line to a first local bit line. The first selection mechanism selectively connects the first vertical source line to the first local source line.

Description

Technical Field

[0001] [References to related applications] This application claims priority to Japanese Patent Application No. 2024-163246, filed on September 20, 2024, the full text of which is incorporated herein by reference.

[0002] This embodiment relates to a semiconductor memory device. Prior Technology

[0003] In a semiconductor memory device having multiple memory cells connected in parallel between bit lines and source lines, a selection mechanism can supply selection potentials to the memory cells from the bit lines and source lines. In a semiconductor memory device, it is desirable to appropriately configure the selection mechanism of the memory cells. Summary of the Invention

[0004] [The problem that the invention aims to solve] One embodiment aims to provide a semiconductor memory device that can be suitably configured as a selection mechanism for memory cells. [Methods for solving problems]

[0005] According to one embodiment, a semiconductor memory device having a plurality of first memory cells and a first selection mechanism is provided. The plurality of first memory cells are stacked on top of a substrate. The plurality of first memory cells are connected in parallel between a first vertical bit line and a first vertical source line. The first vertical bit line extends along the stacking direction. The first vertical source line extends along the stacking direction. The first selection mechanism is disposed between the substrate and the plurality of first memory cells in the stacking direction. The first selection mechanism selectively connects the first vertical bit line to a first local bit line. The first selection mechanism selectively connects the first vertical source line to the first local source line. Simple Explanation of the Diagram

[0006] Figure 1 is a perspective view showing the structure of the semiconductor memory device according to an embodiment.

[0007] Figure 2 is a block diagram showing the structure of the semiconductor memory device according to the embodiment.

[0008] Figure 3 is a circuit diagram showing the structure of the memory cell array in the embodiment.

[0009] Figure 4 is a circuit diagram showing the structure of the memory cell and selection mechanism in the embodiment.

[0010] Figure 5 is a plan view showing the structure of the array layer in the embodiment.

[0011] Figure 6 is a cross-sectional view showing the structure of the array layer and the selected gate layer in the embodiment.

[0012] Figure 7 is a plan view showing the structure of the selected gate layer in the embodiment.

[0013] Figure 8 is a cross-sectional view showing the structure of the array layer and the selected gate layer in the embodiment.

[0014] Figure 9 is a plan view showing the structure of the selected gate layer in the embodiment.

[0015] Figure 10 is a cross-sectional view showing the structure of the array layer and the selected gate layer in the first variation of the implementation.

[0016] Figure 11 is a plan view showing the structure of the selected gate layer in the first variation of the embodiment.

[0017] Figure 12 is a cross-sectional view showing the structure of the array layer and the selected gate layer in the second variation of the embodiment.

[0018] Figure 13 is a plan view showing the structure of the selected gate layer in the second variation of the embodiment.

[0019] Figure 14 is a cross-sectional view showing the structure of the array layer and the selected gate layer in the third variation of the embodiment.

[0020] Figure 15 is a plan view showing the structure of the gate selection layer in the fourth variation of the implementation and the operation of the gate selection layer when writing "1".

[0021] Figure 16 is an enlarged plan view showing the operation of the selection memory cell when writing "1" in the fourth variation of the implementation.

[0022] Figure 17 is an enlarged plan view showing the operation of the non-selective memory cell when writing "1" in the fourth variation of the embodiment.

[0023] Figure 18 is a plan view showing the operation of selecting the gate layer when writing "0" in the fourth variation of the implementation.

[0024] Figure 19 is an enlarged plan view showing the operation of the selection memory cell when writing "0" in the fourth variation of the implementation.

[0025] Figure 20 is an enlarged plan view showing the operation of the non-selective memory cell when writing "0" in the fourth variation of the embodiment.

[0026] Figure 21 is a plan view showing the operation of selecting the gate layer during reading in the fourth variation of the embodiment.

[0027] Figure 22 is an enlarged plan view showing the operation of the selection memory cell during reading in the fourth variation of the embodiment.

[0028] Figure 23 is an enlarged plan view showing the operation of the non-selective memory cell during reading in the fourth variation of the embodiment. Implementation

[0029] According to this embodiment, a semiconductor memory device having a plurality of first memory cells and a first selection mechanism is provided. The plurality of first memory cells are stacked on top of a substrate. The plurality of first memory cells are connected in parallel between a first vertical bit line and a first vertical source line. The first vertical bit line extends along the stacking direction. The first vertical source line extends along the stacking direction. The first selection mechanism is disposed between the substrate and the plurality of first memory cells in the stacking direction. The first selection mechanism selectively connects the first vertical bit line to a first local bit line. The first selection mechanism selectively connects the first vertical source line to the first local source line.

[0030] Hereinafter, the semiconductor memory device according to embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0031] (Implementation Method) The semiconductor memory device of the embodiment has a plurality of memory cells connected in parallel between the bit lines and the source lines. The selection potential of the bit lines and the source lines can be supplied to the memory cells via a selection mechanism, but efforts are made to properly construct the selection mechanism.

[0032] The semiconductor memory device 1 can be configured as shown in Figure 1. Figure 1 is a perspective view showing the structure of the semiconductor memory device 1. Hereinafter, the direction perpendicular to the surface of the substrate SB is defined as the Z direction, and the two directions orthogonal to each other in the plane perpendicular to the Z direction are defined as the X direction and the Y direction.

[0033] Semiconductor memory device 1 is a three-dimensional memory, such as a high-dielectric memory. Semiconductor memory device 1 has a substrate SB, a select gate layer L1, a connection layer CL, a select gate layer L2, and an array layer L3. The select gate layer L1, the connection layer CL, the select gate layer L2, and the array layer L3 are sequentially deposited on the substrate SB.

[0034] The array layer L3 has a memory cell array 2, a character line WL, columnar columns PL3 and PL13.

[0035] The substrate SB extends in a plate-like shape along the XY direction. The substrate SB can be formed of a material primarily composed of semiconductors (e.g., silicon). Multiple character lines WL are deposited spaced apart along the Z direction on top of the substrate SB (on the +Z side). Multiple insulating layers IF2 and character lines WL can also be alternately disposed on the substrate SB. At the same Z position, the multiple character lines WL are arranged spaced apart along the X direction. Each character line WL mainly extends along the Y direction. Each character line WL can also be plate-like with a main surface along the XY direction. Each character line WL can, for example, be formed of a material primarily composed of metals such as tungsten. The insulating layer IF2 can be formed of a material primarily composed of semiconductor oxides (e.g., silicon oxide).

[0036] The memory cell array 2 has multiple channel regions CH and multiple insulating films FE.

[0037] Multiple channel regions CH are stacked on the +Z side of the substrate SB, spaced apart along the Z direction. Multiple layers of insulating layer IF2 and channel regions CH can also be alternately provided. The multiple channel regions CH are arranged along the XYZ directions.

[0038] Multiple channel regions CH adjacent in the XY direction between multiple character lines WL are electrically separated using an insulating film IF1. Multiple channel regions CH adjacent in the X direction, sandwiching multiple character lines WL, are electrically separated using a slit IF3. The slit IF3 can be formed of a material primarily composed of semiconductor oxides (e.g., silicon oxide). Multiple channel regions CH adjacent in the Z direction are electrically separated using an insulating layer IF2.

[0039] Each channel region CH extends in a plate-like shape along the XY direction. Each channel region CH can be formed from a semiconductor film with semiconductor (e.g., silicon) as the main component.

[0040] Multiple insulating films FE are deposited separately along the Z direction on the +Z side of the substrate SB. Multiple insulating layers IF2 and insulating films FE can also be alternately provided. The multiple insulating films FE are arranged along the X direction. In the X direction, each insulating film FE is disposed between the character line WL and the channel region CH. Each insulating film FE extends linearly along the Y direction. Each insulating film FE can be formed of an insulating material. Each insulating film FE can also contain a strong dielectric.

[0041] Each insulating film FE can be formed from a material whose main component is hafnium oxide (HfO). Each insulating film FE can also be formed from a material that further includes at least one element selected from the group consisting of silicon (Si), scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), zirconium (Zr), aluminum (Al), strontium (Sr), lanthanum (La), cerium (Ce), pium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), thorium (Gd), tungsten (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thionium (Tm), ytterbium (Yb), and argonium (Lu).

[0042] Multiple columnar structures PL3 are arranged along the XY direction on the +Z side of the substrate SB. The XY direction arrangement of the multiple columnar structures PL3 corresponds to the XY direction arrangement of multiple channel regions CH. Each columnar structure PL3 corresponds to the multiple channel regions CH arranged along the Z direction. Each columnar structure PL3 penetrates the multiple channel regions CH arranged along the Z direction, extending along their stacking direction, i.e., the Z direction, until it reaches the channel region CH on the -Z side (see Figure 6). Each columnar structure PL3 extends along the Z direction within the channel region CH. Each columnar structure PL3 can be formed, for example, from a material whose main component is metal such as tungsten. The columnar structures PL3 function as part of the vertical bit line vBL (see Figure 4). The vertical bit line vBL can be connected to the global bit line GBL via the local bit line LBL.

[0043] Multiple columnar bodies PL13 are arranged along the XY direction on the +Z side of the substrate SB. The XY direction arrangement of the multiple columnar bodies PL13 corresponds to the XY direction arrangement of the multiple channel regions CH, and also corresponds to the XY direction arrangement of the multiple columnar bodies PL3. Each columnar body PL13 corresponds to the multiple channel regions CH arranged along the Z direction. Each columnar body PL13 extends through the corresponding multiple channel regions CH at a position spaced apart from the columnar body PL3 in the Y direction, along their stacking direction, i.e., the Z direction, until it reaches the channel region CH on the -Z side (see Figure 6). Each columnar body PL13 extends along the Z direction within the channel region CH. Each columnar body PL13 may be formed, for example, from a material whose main component is metal such as tungsten. The columnar bodies PL13 function as part of the vertical source line vSL (see Figure 4). The vertical source line vSL can be connected to the global source line GSL via the local source line LSL.

[0044] In the array layer L3, a stacked body SST is formed by alternating layers of "character lines WL, insulating film FE, channel regions CH" and insulating layer IF2. In the stacked body SST, multiple channel regions CH are arranged along the XYZ direction. In the X direction, the insulating film FE and character lines WL are sequentially adjacent to each other to form a three-dimensional memory cell MT (memory cell array).

[0045] That is, in the semiconductor memory device 1, the portion of the channel region CH facing the word line WL via the insulating film FE is configured to function as a memory cell MT, forming a memory cell array 2 in which multiple memory cells MT are arranged in three dimensions. In the semiconductor memory device 1, by increasing the number of word lines WL in the stacked layer SST, the memory capacity can be increased even without using finer patterning techniques.

[0046] The gate layer L2 is equipped with a selection mechanism SM2 (see Figure 4). The selection mechanism SM2 includes a selection transistor BT2 and a selection transistor ST2. The selection transistors BT2 and ST2 are driven via the selection gate line SG2 connected to their respective gates.

[0047] The interconnect layer CL includes conductive films CN1 and CN2 (see Figures 6 and 8). Conductive films CN1 and CN2 can be formed, for example, from materials primarily composed of metals such as aluminum or copper. Conductive film CN1 functions as part of a local bit line LBL (see Figure 4). Conductive film CN2 functions as part of a local source line LSL (see Figure 4).

[0048] In the gate selection layer L1, a selection mechanism SM1 is provided (see Figure 4). The selection mechanism SM1 includes a selection transistor BT1 and a selection transistor ST1. The selection transistors BT1 and ST1 are driven via the selection gate line SG1 connected to their respective gates.

[0049] Furthermore, an interlayer insulating film 81 may also be disposed between the substrate SB and the selective gate layer L1 in the Z direction. The interlayer insulating film 81 may be formed of a material mainly composed of semiconductor oxides (e.g., silicon oxide).

[0050] The selection potential of the global bit line GBL can be supplied to the memory cell MT via the selection mechanism SM1, the local bit line LBL, the selection mechanism SM2, and the vertical bit line vBL. The selection potential of the global source line GSL can be supplied to the memory cell MT via the selection mechanism SM1, the local source line LSL, the selection mechanism SM2, and the vertical bit line vBL.

[0051] For example, in manufacturing a semiconductor memory device 1, on the +Z side of the substrate SB, a structure of a select gate layer L1, a structure of a connection layer CL, a structure of a select gate layer L2, and a structure of an array layer L3 are formed in approximately sequential order. When forming the structures of the select gate layer L1 (selection mechanism SM1) and the select gate layer L2 (selection mechanism SM2), a relatively high-temperature heat treatment (e.g., above 1000°C) is performed. When each insulating film FE contains a strong dielectric, this heat treatment causes the strong dielectric properties of each insulating film FE to be lost (paraelectricized), making it difficult to maintain "1" or "0" using its polarization direction.

[0052] On the other hand, in the semiconductor memory device 1, as shown in FIG1, a selection mechanism SM1 and a selection mechanism SM2 for memory cells MT are provided between the substrate SB and the memory cell array 2 in the Z direction. Therefore, in the manufacturing process of the semiconductor memory device 1, the structure of the array layer L3 is formed after a relatively high-temperature heat treatment. Thus, the structure of the semiconductor memory device 1 is suitable for avoiding the heat treatment of each insulating film FE when each insulating film FE contains a strong dielectric.

[0053] Figure 2 is a block diagram showing the schematic structure of the semiconductor memory device 1. As shown in Figure 2, the semiconductor memory device 1 has a memory cell array 2, peripheral circuitry 100, and interface 200. The peripheral circuitry 100 includes a WL driving circuit 110, an SG1 driving circuit 120, an SG2 driving circuit 130, an SL driving circuit 140, and a sense amplifier circuit 150.

[0054] The WL drive circuit 110 controls the voltage applied to the character line WL, the SG1 drive circuit 120 controls the voltage applied to the select gate line SG1, the SG2 drive circuit 130 controls the voltage applied to the select gate line SG2, and the SL drive circuit 140 controls the voltage applied to the global source line GSL. The sense amplifier circuit 150 controls the voltage applied to the global bit line GBL and determines the data to be read based on the signal from the selected memory cell.

[0055] The peripheral circuit 100 controls the operation of the semiconductor memory device 1 based on instructions input from an external source (e.g., a memory controller of the memory system applicable to the semiconductor memory device 1) via the interface 200.

[0056] Next, Figure 3 will be used to illustrate the circuit structure of the memory cell array 2. Figure 3 is a diagram showing the circuit structure of the memory cell array 2 in three dimensions.

[0057] In Figure 3, the memory cell array 2 has, for example, 4n word lines (n is an integer greater than 2) WL_1 to WL_4n. Moreover, the memory cell array 2 has m vertical bit lines (m is a multiple of 2 greater than 2) vBL_1 to vBL_m and m vertical source lines vSL_1 to vSL_m.

[0058] In memory cell array 2, multiple memory cells MT contain NOR (Not OR, NOR) type circuits.

[0059] The memory cell array 2 can be divided into m driving cells DU_1 to DU_m. The m driving cells DU_1 to DU_m are arranged along the XY direction. In Figure 3, a 2-row × 2 / m-column arrangement is shown as an example of the arrangement of the driving cells DU. Each driving cell DU contains n memory cells MT that share a vertical bit line vBL and a vertical source line vSL. The n memory cells MT are arranged along the Z direction.

[0060] In the driving unit DU, n memory cells MT are connected in parallel between the vertical bit line vBL and the vertical source line vSL, forming a NOR-type memory cell group MG.

[0061] The word line WL is connected across the drive units DU arranged along the Y direction. The word line WL is connected to the gates of multiple memory cells MT arranged along the Y direction.

[0062] As shown in Figure 4, selection mechanisms SM1 and SM2 are provided on the -Z side of the vertical bit line vBL and the vertical source line vSL. Figure 4 is a circuit diagram showing the structure of the memory cell MT and the selection mechanisms SM1 and SM2. In Figure 4, for simplicity, only one memory cell MT in the memory cell group MG of the driving unit DU_1 and the driving unit DU_2 is shown, and the illustrations of other memory cells MT in the memory cell group MG are omitted.

[0063] As the selection mechanism SM1, it includes selection transistors BT1 and ST1. As the selection mechanism SM2, it includes selection transistors BT2 and ST2.

[0064] Select transistor BT1 is connected between the local bit line LBL and the global bit line GBL. The drain of select transistor BT1 is connected to the local bit line LBL, the source is connected to the global bit line GBL, and the gate is connected to the select gate line SG1. Select transistor BT1 is driven via the select gate line SG1 connected to its gate.

[0065] Select transistor BT2 is connected between the vertical bit line vBL and the local bit line LBL. The drain of select transistor BT2 is connected to the vertical bit line vBL, the source is connected to the local bit line LBL, and the gate is connected to the select gate line SG2. Select transistor BT2 is driven via the select gate line SG2 connected to its gate.

[0066] Select transistor ST1 is connected between the local source line LSL and the global source line GSL. The drain of select transistor ST1 is connected to the local source line LSL, the source is connected to the global source line GSL, and the gate is connected to the select gate line SG1. Select transistor ST1 is driven via the select gate line SG1 connected to its gate.

[0067] Select transistor ST2 is connected between the vertical source line vSL and the local source line LSL. The drain of select transistor ST2 is connected to the vertical source line vSL, the source is connected to the local source line LSL, and the gate is connected to the select gate line SG2. Select transistor ST2 is driven via the select gate line SG2 connected to its gate.

[0068] In the memory cell group MG, the global bit line GBL is selected and connected in two stages by select transistors BT1 and BT2. The global source line GSL is selected and connected in two stages by select transistors ST1 and ST2. The selection of memory cells MT within the memory cell group MG is performed by word lines WL.

[0069] Next, Figures 5 through 9 will be used to illustrate the detailed structures of array layer L3, selective gate layer L2, and selective gate layer L1. Figure 5 is an XY plan view showing the structure of array layer L3, and is an enlarged XY plan view corresponding to part A of Figure 1. Figure 6 is an XZ cross-sectional view showing the structure of array layer L3, selective gate layer L2, and selective gate layer L1, representing the cross-section when Figure 5 is cut along line BB. Figure 7 is an XY plan view showing the structure of selective gate layer L2, corresponding to the cross-section when Figure 6 is cut along line EE. Figure 8 is a YZ cross-sectional view showing the structure of array layer L3, selective gate layer L2, and selective gate layer L1, representing the cross-section when Figure 5 is cut along line CC. Figure 9 is an XY plan view showing the structure of selective gate layer L1, corresponding to the cross-section when Figure 8 is cut along line FF.

[0070] As shown in Figures 5, 6, and 8, in array layer L3, the portion of the channel region CH facing the word line WL via the insulating film FE functions as memory cells MT, forming a memory cell array 2 with multiple memory cells MT arranged in a three-dimensional manner. In memory cell array 2, the multiple memory cells MT are grouped into multiple memory cell groups corresponding to the driving unit DU (see Figure 3). Each memory cell group contains multiple memory cells MT arranged along the Z direction. The multiple memory cell groups are arranged along the XY direction.

[0071] Multiple memory cell groups correspond to multiple columnar bodies PL3 and multiple columnar bodies PL13. In the channel region CH of each memory cell group, the corresponding columnar body PL3 extends along the Z-direction, and the corresponding columnar body PL13 extends along the Z-direction. Each columnar body PL3 can be formed, for example, from a material primarily composed of metals such as tungsten. The columnar body PL3 functions as part of the vertical source line vBL (see Figure 4). Each columnar body PL13 can be formed, for example, from a material primarily composed of metals such as tungsten. The columnar body PL13 functions as part of the vertical source line vSL (see Figure 4).

[0072] As shown in Figures 6 and 7, the gate layer L2 is equipped with multiple columnar bodies PL2, multiple columnar bodies PL12, multiple selector gate lines SG2_1~SG2_3, and multiple insulating films IF4. Selector gate line SG2_1 has multiple conductive films SG2_1a and SG2_1b. Selector gate line SG2_2 has multiple conductive films SG2_2a and SG2_2b. Selector gate line SG2_3 has multiple conductive films SG2_3a and SG2_3b.

[0073] Multiple columnar bodies PL2 correspond to multiple columnar bodies PL3 and multiple conductive films CN1. Each columnar body PL2 extends along the Z direction. The +Z side end of each columnar body PL2 is connected to the corresponding columnar body PL3. The -Z side end of each columnar body PL2 is connected to the corresponding conductive film CN1 (local bit line LBL).

[0074] Multiple columnar bodies PL12 correspond to multiple columnar bodies PL13 and multiple conductive films CN2. Each columnar body PL12 extends along the Z direction. The +Z side end of each columnar body PL12 is connected to the corresponding columnar body PL13. The -Z side end of each columnar body PL12 is connected to the corresponding conductive film CN2 (Local Source Line LSL).

[0075] Multiple conductive films SG2_1a~SG2_3b correspond to multiple columnar bodies PL2, PL12 arranged along the Y direction. Each conductive film SG2 extends along the Y direction. Each conductive film SG2 can be formed, for example, from a material whose main component is a metal such as tungsten.

[0076] As shown in Figure 7, the conductive film SG2_1a alternately approaches the -X side of columnar body PL2 and the -X side of columnar body PL12 multiple times as it advances from the -Y side towards the +Y side. At each approach point, an insulating film IF4 mediates between the conductive film SG2_1a and columnar bodies PL2 and PL12. The insulating film IF4 may be formed of a material primarily composed of semiconductor oxides (e.g., silicon oxide). Similarly, the conductive film SG2_1b alternately approaches the +X side of columnar body PL2 and the +X side of columnar body PL12 multiple times as it advances from the -Y side towards the +Y side. At each approach point, the insulating film IF4 mediates between the conductive film SG2_1b and columnar bodies PL2 and PL12.

[0077] Conductive films SG2_1a and SG2_1b are paired and work together as the selection gate line SG2_1 (see Figure 4). The portion of columnar body PL2 that faces both conductive films SG2_1a and SG2_1b via insulating film IF4 functions as the selection transistor BT2. The selection transistor BT2 has a vertical thin-film transistor (TFT) structure with a channel region extending along the Z direction and gates on both sides in the X direction.

[0078] The portion of columnar body PL12 that faces conductive films SG2_1a and SG2_1b via insulating film IF4 functions as selector transistor ST2. Selector transistor ST2 has a vertical thin-film transistor (TFT) structure with channel region extending along the Z direction and gates on both sides in the X direction.

[0079] Furthermore, the pairings of conductive films SG2_2a and SG2_2b, and conductive films SG2_3a and SG2_3b, are the same as the pairings of conductive films SG2_1a and SG2_1b.

[0080] As shown in Figures 6-9, the connecting layer CL is provided with multiple conductive films CN1 and multiple conductive films CN2. Each conductive film CN1 functions as part of the local bit line LBL shown in Figures 7 and 9, for example, as part from the +X side of the local bit line LBL to the +X side of the selected transistor BT1. The multiple conductive films CN1 are arranged along the Y direction and extend along the X direction. Each conductive film CN2 functions as part of the local source line LSL shown in Figures 7 and 9, for example, as part from the -X side of the local source line LSL to the -X side of the selected transistor ST1. The multiple conductive films CN2 are arranged along the X direction and extend along the Y direction.

[0081] As shown in Figures 8 and 9, the gate layer L1 is equipped with multiple columnar bodies PL1 and PL11, multiple selector gate lines SG1_1 to SG1_8, and multiple insulating films IF5. Selector gate line SG1_1 has multiple conductive films SG1_1a and SG1_1b. Selector gate line SG1_2 has multiple conductive films SG1_2a and SG1_2b. Selector gate line SG1_3 has multiple conductive films SG1_3a and SG1_3b. Selector gate line SG1_4 has multiple conductive films SG1_4a and SG1_4b. Selector gate line SG1_5 has multiple conductive films SG1_5a and SG1_5b. Selector gate line SG1_6 has multiple conductive films SG1_6a and SG1_6b. Selector gate line SG1_7 has multiple conductive films SG1_7a and SG1_7b. Selector gate line SG1_8 has multiple conductive films SG1_8a and SG1_8b.

[0082] Multiple columnar bodies PL1 correspond to multiple conductive films CN1. Each columnar body PL1 extends along the Z direction. The +Z side end of each columnar body PL1 is connected to the corresponding conductive film CN1 (local bit line LBL). The -Z side end of each columnar body PL1 is connected to the global bit line GBL.

[0083] Multiple columnar bodies PL11 correspond to multiple conductive films CN2. Each columnar body PL11 extends along the Z direction. The +Z side end of each columnar body PL11 is connected to the corresponding conductive film CN2. The -Z side end of each columnar body PL12 is connected to the global source line GSL.

[0084] Multiple conductive films SG1_1a to SG1_8b correspond to multiple columnar bodies PL1 and PL11 arranged along the Y direction. Each conductive film SG1 extends along the X direction. Each conductive film SG1 may be formed, for example, from a material whose main component is a metal such as tungsten.

[0085] As shown in Figure 9, the conductive film SG1_1a alternately approaches the -Y side of columnar body PL1 and columnar body PL11 multiple times as it advances from the -X side towards the +X side. At each approach point, an insulating film IF5 mediates between the conductive film SG1_1a and columnar bodies PL1 and PL11. The insulating film IF5 may be formed of a material primarily composed of semiconductor oxides (e.g., silicon oxide). The conductive film SG1_1b alternately approaches the +Y side of columnar body PL1 and columnar body PL11 multiple times as it advances from the -X side towards the +X side. At each approach point, the insulating film IF5 mediates between the conductive film SG1_1b and columnar bodies PL1 and PL11.

[0086] The portion of columnar body PL1 that faces conductive films SG1_1a and SG1_1b via insulating film IF5 functions as select transistor BT1. Select transistor BT1 has a vertical thin-film transistor (TFT) structure with channel region extending along the Z direction and gates on both sides of the Y direction.

[0087] The portion of columnar body PL11 that faces conductive films SG1_1a and SG1_1b via insulating film IF5 functions as select transistor ST1. Select transistor ST1 has a vertical thin-film transistor (TFT) structure with channel region extending along the Z direction and gates on both sides of the Y direction.

[0088] Furthermore, the pairs of conductive films SG2_2a and SG2_2b, SG2_3a and SG2_3b, SG2_4a and SG2_4b, SG2_5a and SG2_5b, SG2_6a and SG2_6b, SG2_7a and SG2_7b, and SG2_8a and SG2_8b are the same as the pairs of conductive films SG2_1a and SG2_1b. For example, the pairs of conductive films SG2_2a and SG2_2b, SG2_3a and SG2_3b, SG2_4a and SG2_4b, SG2_5a and SG2_5b, SG2_6a and SG2_6b, SG2_7a and SG2_7b, and SG2_8a and SG2_8b respectively cooperate to function as selective gate lines SG1_2, SG1_3, SG1_4, SG1_5, SG1_6, SG1_7, and SG1_8.

[0089] Figures 7 and 9 illustrate the arrangement of selection mechanisms SM2 and SM1 when multiple drive units DU_1~DU_12 are arranged in 4 rows × 3 columns.

[0090] In Figure 7, selection transistors BT2_1 to BT2_12 and ST2_1 to ST2_12 are illustrated as selection mechanism SM2. Selection transistors BT2_1 to BT2_12 correspond to drive unit DU and are arranged in 4 rows × 3 columns. Selection transistors ST2_1 to ST2_12 correspond to drive unit DU and are arranged in 4 rows × 3 columns.

[0091] In Figure 9, selection transistors BT1_1 to BT1_4 and ST1_1 to ST1_4 are illustrated as selection mechanism SM1. Selection transistors BT1_1 to BT1_12 correspond to local bit lines LBL and are arranged in 4 rows × 1 column on the -X side of the arrangement of multiple drive units DU_1 to DU_12. Selection transistors ST1_1 to ST1_4 correspond to local source lines LSL and are arranged in 4 rows × 1 column on the +X side of the arrangement of multiple drive units DU_1 to DU_12.

[0092] Furthermore, the local bit line LBL and the local source line LSL are arranged alternately multiple times along the Y direction. The global bit line GBL is positioned on the -X side relative to the arrangement of multiple drive units DU_1~DU_12 and extends along the Y direction. The global source line GSL is positioned on the +X side relative to the arrangement of multiple drive units DU_1~DU_12 and extends along the Y direction.

[0093] For example, suppose that the memory cell MT_n of the driving unit DU_7 shown in Figures 7 and 9 (refer to Figure 3) is selected, and the other memory cells MT_1 to MT_n-1 of the driving unit DU_7 and all memory cells MT of the other driving units DU_1 to DU_6 and DU_8 to DU_12 are set to non-selected.

[0094] When a write operation is performed to the "1" of the selected memory cell MT_n of the drive unit DU_7, a selection potential of "1" (e.g., -2.5 V) is applied to the word line WL_n of the selected memory cell MT_n, and a non-selection potential (e.g., 0 V) ​​is applied to the word lines WL_1 to WL_n-1 of the non-selected memory cells MT_1 to MT_n-1. The global bit line GBL and the global source line GSL are controlled to a selection potential of "1" (e.g., 2.5 V).

[0095] In Figures 7 and 9, the selected gate lines SG1_5a, SG1_5b, SG1_6a, SG1_6b, SG2_2a, and SG2_2b, indicated by diagonal shaded lines, correspond to the selected memory cell MT_n. Selected gate lines SG1_5a, SG1_5b, SG1_6a, SG1_6b, SG2_2a, and SG2_2b are controlled at a selection potential (e.g., 1.5 V). The other selected gate lines SG1_1a to SG1_4b, SG1_7a to SG1_8b, and SG2_1a, SG2_1b, SG2_3a, and SG2_3b are controlled at a non-selection potential (e.g., 0 V).

[0096] Therefore, the select transistors BT1 and BT2 of the driving unit DU_7 are selectively turned on, and the selection potential of the global bit line GBL is supplied to the selection memory cell MT_n of the driving unit DU_7 through the select transistors BT1 and BT2. Similarly, the select transistors ST1 and ST2 of the driving unit DU_7 are selectively turned on, and the selection potential of the global source line GSL is supplied to the selection memory cell MT_n of the driving unit DU_7 through the select transistors ST1 and ST2.

[0097] Correspondingly, the channel region CH of the selected memory cell MT_n in the driving unit DU_7 becomes the selection potential (e.g., 2.5 V). In the selected memory cell MT_n of the driving unit DU_7, relative to the channel region CH, the word line WL_n applies an electric field exceeding the positive threshold value (e.g., 5 V) to the insulating film FE on the positive side, causing a negative shift of Vth in the memory cell MT. A "1" can be written to the memory cell MT_n of the driving unit DU_7. The memory cell MT_n can remain at "1" as long as its polarization state does not change due to external electric fields, etc.

[0098] At this time, in the non-selection memory cells MT_1 to MT_n-1 of the selection drive unit DU_7, the selection potential of the global bit line GBL and the global source line GSL is supplied, but the electric field applied to the insulating film FE at a value lower than the threshold (e.g., 2.5 V) will not cause writing to the memory cell MT.

[0099] Alternatively, when writing a "0" to the selected memory cell MT_n of the drive unit DU_7, a selection potential of "0" (e.g., 2.5 V) is applied to the word line WL_n of the selected memory cell MT_n, and a non-selection potential (e.g., 0 V) ​​is applied to the word lines WL_1 to WL_n-1 of the non-selected memory cells MT_1 to MT_n-1. The global bit line GBL and the global source line GSL are controlled to a selection potential of "0" (e.g., -2.5 V).

[0100] In Figures 7 and 9, the selected gate lines SG1_5a, SG1_5b, SG1_6a, SG1_6b, SG2_2a, and SG2_2b, indicated by diagonal shading, correspond to the selected memory cell MT_n. Selected gate lines SG1_5a, SG1_5b, SG1_6a, SG1_6b, SG2_2a, and SG2_2b are controlled at a selection potential (e.g., 1.5 V). The other selected gate lines SG1_1a to SG1_4b, SG1_7a to SG1_8b, and SG2_1a, SG2_1b, SG2_3a, and SG2_3b are controlled at a non-selection potential (e.g., 0 V).

[0101] Therefore, the select transistors BT1_3 and BT2_7 of the driving unit DU_7 are selectively turned on, and the selection potential of the global bit line GBL is supplied to the selection memory cell MT_n of the driving unit DU_7 via the select transistors BT1_3 and BT2_7. Similarly, the select transistors ST1_3 and ST2_7 of the driving unit DU_7 are selectively turned on, and the selection potential of the global source line GSL is supplied to the selection memory cell MT_n of the driving unit DU_7 via the select transistors ST1_3 and ST2_7.

[0102] Correspondingly, the channel region CH of the selected memory cell MT_n in the driving unit DU_7 becomes the selection potential (e.g., -2.5 V). In the selected memory cell MT_n, relative to the channel region CH, the word line WL_n applies an electric field exceeding the negative threshold value (e.g., -5 V) to the insulating film FE on the negative side, causing a positive shift of Vth in the memory cell MT_n during writing. "0" can be written to the memory cell MT_n of the driving unit DU_7. The memory cell MT_n of the driving unit DU_7 can remain "0" as long as its polarization state does not change due to external electric fields, etc.

[0103] At this time, the non-selected memory cells MT_1 to MT_n-1 in the drive unit DU_7 are supplied with the selection potential of the global bit line GBL and the global source line GSL, but the electric field applied to the insulating film FE on the positive side below the threshold value (e.g., 2.5 V) will not cause writing to the memory cell MT.

[0104] Alternatively, when performing a read operation on the selected memory cell MT_n of the driving unit DU_7, a read selection potential (e.g., 1.5 V) is applied to the word line WL_n of the selected memory cell MT_n, and a non-selection potential (e.g., 0 V) ​​is applied to the word lines WL_1 to WL_n-1 of the non-selected memory cells MT_1 to MT_n-1. The global bit line GBL is controlled to the read selection potential (e.g., 0.5 V), and the global source line GSL is controlled to the read selection potential (e.g., 0 V).

[0105] In Figures 7 and 9, the selected gate lines SG1_5a, SG1_5b, SG1_6a, SG1_6b, SG2_2a, and SG2_2b, indicated by diagonal shading, correspond to the selected memory cell MT_n. Selected gate lines SG1_5a, SG1_5b, SG1_6a, SG1_6b, SG2_2a, and SG2_2b are controlled at a selection potential (e.g., 1.5 V). The other selected gate lines SG1_1a to SG1_4b, SG1_7a to SG1_8b, and SG2_1a, SG2_1b, SG2_3a, and SG2_3b are controlled at a non-selection potential (e.g., 0 V).

[0106] Therefore, the select transistors BT1_3 and BT2_7 of the driving unit DU_7 are selectively turned on, and the selection potential of the global bit line GBL is supplied to the selection memory cell MT_n of the driving unit DU_7 via the select transistors BT1_3 and BT2_7. Similarly, the select transistors ST1_3 and ST2_7 of the driving unit DU_7 are selectively turned on, and the selection potential of the global source line GSL is supplied to the selection memory cell MT_n of the driving unit DU_7 via the select transistors ST1_3 and ST2_7.

[0107] If a "1" is written into the selection memory cell MT_n of the driving unit DU_7, the cell current in the channel region CH of the selection memory cell MT_n flows from the conductive film BL to the conductive film SL, and the potential of the conductive film BL decreases. The sensing amplifier circuit 150 detects the "1" in response to the decrease in the potential of the conductive film BL. Thus, a "1" is read from the selection memory cell MT_n of the driving unit DU_7. Alternatively, if a "0" is written into the selection memory cell MT_n of the driving unit DU_7, the cell current in the channel region CH of the selection memory cell MT_1 hardly flows from the conductive film BL to the conductive film SL, and the potential of the conductive film BL is maintained. The sensing amplifier circuit 150 detects the "0" in response to the maintenance of the potential of the conductive film BL. Thus, a "0" is read from the selection memory cell MT_n of the driving unit DU_7.

[0108] At this time, in the non-selection memory cells MT_1 to MT_n-1 of the selection drive unit DU_7, the selection potentials of the global bit line GBL and the global source line GSL are supplied, but the non-selection potentials are supplied to the word lines WL_1 to WL_n-1. Therefore, the reading of the self-memory cell MT will not be triggered in the non-selection memory cells MT_1 to MT_n-1 of the selection drive unit DU_7.

[0109] As described above, in the embodiment, in the semiconductor memory device 1, the selection mechanisms SM1 and SM2 of the memory cells MT are disposed between the substrate SB and the memory cell array 2 in the Z direction. Therefore, in the manufacturing process of the semiconductor memory device 1, the structure of the array layer L3 is formed after a relatively high-temperature heat treatment. Thus, a structure for the semiconductor memory device 1 suitable for avoiding the heat treatment of each insulating film FE when each insulating film FE contains a strong dielectric material can be provided.

[0110] Furthermore, as a first variation of the embodiment, in the selection mechanism SM101, the conductive film that functions as the selection gate line SG1 can also be arranged on one side of the columnar bodies PL1 and PL11 in the Y direction, as shown in Figures 10 and 11. Figure 10 is a YZ cross-sectional view showing the structure of the array layer L3, the selection gate layer L2, and the selection gate layer L1 in the first variation of the embodiment, corresponding to the cross-section when Figure 5 is cut along the CC line. Figure 11 is an XY plan view showing the structure of the selection gate layer L1, corresponding to the cross-section when Figure 10 is cut along the GG line.

[0111] In the selected gate layer L1, each selected gate line SG1 omits one of the two conductive films disposed on both sides of the columnar bodies PL1 and PL11 in the Y direction. Figures 10 and 11 illustrate the structure in which the conductive film disposed on the -Y side of the two conductive films disposed on both sides of the columnar bodies PL1 and PL11 in the Y direction is omitted.

[0112] The selective gate line SG1_1 shown in Figures 10 and 11 has a conductive film SG1_1b. Selective gate line SG1_2 has a conductive film SG1_2b. Selective gate line SG1_3 has a conductive film SG1_3b. Selective gate line SG1_4 has a conductive film SG1_4b. Selective gate line SG1_5 has a conductive film SG1_5b. Selective gate line SG1_6 has a conductive film SG1_6b. Selective gate line SG1_7 has a conductive film SG1_7b. Selective gate line SG1_8 has a conductive film SG1_8b.

[0113] As shown in Figure 11, the conductive film SG1_1b alternately approaches the +Y side of columnar body PL1 and columnar body PL11 multiple times as it advances from the -X side towards the +X side. At each approach point, the insulating film IF5 mediates between the conductive film SG1_1b and columnar bodies PL1 and PL11.

[0114] The portion of columnar body PL1 that faces conductive film SG1_1b via insulating film IF5 functions as selection transistor BT1 in selection mechanism SM101. Selection transistor BT1 has a vertical thin-film transistor (TFT) structure with channel region extending along the Z direction and gate on one side in the Y direction.

[0115] The portion of columnar body PL11 facing the conductive film SG1_1b via insulating film IF5 functions as the selection transistor ST1 in selection mechanism SM101. Selection transistor ST1 has a vertical thin-film transistor (TFT) structure with channel region extending along the Z direction and a gate on one side in the Y direction.

[0116] Furthermore, the conductive films SG2_2b, SG2_3b, SG2_4b, SG2_5b, SG2_6b, SG2_7b, and SG2_8b are the same as those for the conductive film SG2_1b.

[0117] Thus, in the selection mechanism SM101, the conductive film that functions as the selection gate line SG1 is disposed on one side of the columnar bodies PL1 and PL11 in the Y direction. This allows the columnar bodies PL1 and PL11 in the Y direction to be brought closer together, and consequently, the local bit line LBL and local source line LSL in the Y direction are also brought closer together. As a result, the density of the selection transistor BT1 and the selection transistor ST1 in the Y direction can be increased, respectively.

[0118] Alternatively, as a second variation of the embodiment, in the selection mechanism SM202, the conductive film that functions as the selection gate line SG2 can also be arranged on one side of the columnar bodies PL2 and PL12 in the X direction, as shown in Figures 12 and 13. Figure 12 is a YZ cross-sectional view showing the structure of the array layer L3, the selection gate layer L2, and the selection gate layer L1 in the second variation of the embodiment, corresponding to the cross-section when Figure 5 is cut along line BB. Figure 13 is an XY plan view showing the structure of the selection gate layer L1, corresponding to the cross-section when Figure 12 is cut along line HH.

[0119] In the selected gate layer L2, each selected gate line SG2 omits one of the two conductive films disposed on both sides of the columnar bodies PL2 and PL12 in the X direction. Figures 12 and 13 illustrate the structure in which the conductive film disposed on the -Y side of the two conductive films disposed on both sides of the columnar bodies PL2 and PL12 in the X direction is omitted.

[0120] The selective gate line SG2_1 shown in Figures 12 and 13 has a conductive film SG2_1a. The selective gate line SG2_2 has a conductive film SG2_2a. The selective gate line SG2_3 has a conductive film SG2_3a.

[0121] As shown in Figure 13, the conductive film SG2_1a alternately approaches the +Y side of columnar body PL2 and columnar body PL12 multiple times as it advances from the -Y side towards the +Y side. At each approach point, the insulating film IF4 mediates between the conductive film SG2_1a and columnar bodies PL2 and PL12.

[0122] The portion of columnar body PL2 that faces conductive film SG2_1a via insulating film IF4 functions as selection transistor BT2 in selection mechanism SM202. Selection transistor BT2 has a vertical thin-film transistor (TFT) structure with channel region extending along the Z direction and gate on one side in the X direction.

[0123] The portion of columnar body PL12 facing the conductive film SG2_1a via insulating film IF4 functions as the selector transistor ST2 in selector mechanism SM202. Selector transistor ST2 has a vertical thin-film transistor (TFT) structure with channel region extending along the Z direction and a gate on one side in the X direction.

[0124] Furthermore, the conductive films SG2_2a and SG2_3a are the same as those for the conductive film SG2_1a.

[0125] Thus, in the selection mechanism SM202, the conductive film that functions as the selection gate line SG2 is disposed on one side of the columnar bodies PL2 and PL12 in the X direction. This allows the columnar bodies PL2 and PL12 to be brought closer together in the X direction. As a result, the density of the selection transistors BT2 and ST2 in the X direction can be increased, respectively.

[0126] Alternatively, as a third variation of the implementation, in the selection mechanism SM301, the conductive film that functions as the selection gate line SG1 can also be divided into two layers.

[0127] Semiconductor memory device 301 replaces the select gate layer L1 (see Figure 8) and has select gate layers L301u and L301d as shown in Figure 14. Figure 14 is a YZ cross-sectional view showing the structure of array layer L3, select gate layer L2, select gate layer L301u, and select gate layer L301d in the third variation of the embodiment, corresponding to the cross-section of Figure 5 cut along the CC line.

[0128] Selective gate layer L301d is disposed between substrate SB and selective gate layer L301u in the Z direction. Selective gate layer L301u is disposed between selective gate layer L301d and interconnect layer CL in the Z direction.

[0129] The selection mechanism SM301 is separately disposed on the selection gate layer L301u and the selection gate layer L301d. The selection mechanism SM301 includes a selection transistor BT1 and a selection transistor ST1. One of the selection transistors BT1 and ST1 is disposed on the selection gate layer L301u, and the other is disposed on the selection gate layer L301d. Figure 14 illustrates the structure in which the selection transistor BT1 is disposed on the selection gate layer L301u and the selection transistor ST1 is disposed on the selection gate layer L301d.

[0130] The selective gate layer L301u is equipped with multiple columnar bodies PL1, odd-numbered selective gate lines SG1_1, SG1_3, SG1_5, SG1_7, and multiple insulating films IF5u.

[0131] Selective gate line SG1_1 has multiple conductive films SG1_1a and SG1_1b. Selective gate line SG1_3 has multiple conductive films SG1_3a and SG1_3b. Selective gate line SG1_5 has multiple conductive films SG1_5a and SG1_5b. Selective gate line SG1_7 has multiple conductive films SG1_7a and SG1_7b.

[0132] In the selective gate layer L301d, there are multiple columnar bodies PL11, even-numbered selective gate lines SG1_2, SG1_4, SG1_6, SG1_8, and multiple insulating films IF5d.

[0133] Selective gate line SG1_2 has multiple conductive films SG1_2a and SG1_2b. Selective gate line SG1_4 has multiple conductive films SG1_4a and SG1_4b. Selective gate line SG1_6 has multiple conductive films SG1_6a and SG1_6b. Selective gate line SG1_8 has multiple conductive films SG1_8a and SG1_8b.

[0134] Conductive films SG1_2a and SG1_2b are separated from conductive films SG1_1a and SG1_1b in the Y direction and also in the Z direction. This suppresses electric field interference between conductive films SG1_2a and SG1_2b and conductive films SG1_1a and SG1_1b.

[0135] Conductive films SG1_4a and SG1_4b are separated from conductive films SG1_3a and SG1_3b in the Y direction and also in the Z direction. This suppresses electric field interference between conductive films SG1_4a and SG1_4b and conductive films SG1_3a and SG1_3b.

[0136] Conductive films SG1_8a and SG1_8b are separated from conductive films SG1_7a and SG1_7b in the Y direction and also in the Z direction. This suppresses electric field interference between conductive films SG1_8a and SG1_8b and conductive films SG1_7a and SG1_7b.

[0137] Thus, in the selection mechanism SM301, the multiple conductive films that function as the selection gate line SG1 are arranged to be spaced apart not only in the Y direction but also in the Z direction. This suppresses electric field interference between the multiple conductive films and allows the columnar bodies PL1 and PL11 in the Y direction to be brought closer together. Consequently, the local bit line LBL and local source line LSL in the Y direction are also brought closer together. As a result, the density of the selection transistor BT1 and the selection transistor ST1 in the Y direction can be increased, respectively.

[0138] Alternatively, as a fourth variation of the implementation, the selection mechanism SM401 of the gate layer L401 can also be configured as shown in FIG15. FIG15 is a plan view showing the structure of the gate layer L401 in the fourth variation of the implementation and the operation of the gate layer L401 when writing "1".

[0139] In the gate selection layer L401, the selection mechanism SM401, in addition to the selection transistors BT1_1 to BT1_4 and ST1_1 to ST1_4 (see Figure 9), also includes selection transistors BT401_1 to BT401_4 and ST401_1 to ST401_4.

[0140] The selector transistor BT401 is connected between the local source line LSL and the global bit line GBL. The drain of the selector transistor BT401 is connected to the local source line LSL, the source is connected to the global bit line GBL, and the gate is connected to the select gate line SG1. The selector transistor BT401 is driven via the select gate line SG1 connected to its gate.

[0141] The select gate line SG401R connected to the gate of select transistor BT401 is different from the select gate line SG1L connected to select transistor ST1 located on its +X side. Therefore, select transistor BT401 and select transistor ST1 can be individually controlled for on / off states.

[0142] The selector transistor ST401 is connected between the local bit line LBL and the global source line GSL. The drain of the selector transistor ST401 is connected to the local bit line LBL, the source is connected to the global source line GSL, and the gate is connected to the select gate line SG1. The selector transistor ST401 is driven via the select gate line SG401 connected to its gate.

[0143] The select gate line SG401L connected to the gate of select transistor ST401 is different from the select gate line SG1R connected to select transistor BT1 located on its -X side. Therefore, select transistor ST401 and select transistor BT1 can be individually controlled for on / off states.

[0144] In the memory cell group MG, the global bit line GBL is selected and connected in two stages using selector transistors BT1 and BT2, or selector transistors BT401 and ST2. Similarly, the global source line GSL is selected and connected in two stages using selector transistors ST1 and ST2, or selector transistors ST401 and BT2. The selection of the memory cell MT within the memory cell group MG is performed using the word line WL.

[0145] When writing a "1" to the selected memory cell MT_7n of the driving unit DU_7, as shown in Figure 15, the global bit line GBL is controlled to a "1" selection potential (e.g., -2.5 V), and the global source line GSL is controlled to a non-selection potential (e.g., 0.0 V). As shown in Figures 16 and 17, a "1" selection potential (e.g., +2.5 V) is applied to the word line WL_7n of the selected memory cell MT_7n, and a non-selection potential (e.g., 0 V) ​​is applied to the word lines WL_7n-1, WL_3n, and WL_3n-1 of the non-selected memory cells MT_7n-1, MT_3n, and MT_3n-1.

[0146] Select gate lines SG1L_3 and SG401L_3 correspond to the select memory cell MT_7n of the drive unit DU7. Select gate lines SG1L_3 and SG401L_3 are controlled to select potentials (e.g., +2.5 V), while other select gate lines are controlled to non-select potentials (e.g., 0 V).

[0147] In Figure 15, the selected gate line SG2_2a, indicated by the diagonal shaded line, is controlled at a selected potential (e.g., +2.5 V), while the other selected gate lines SG1_1a and SG1_3a are controlled at non-selected potentials (e.g., 0.0 V).

[0148] Therefore, on the -X side, the select transistors BT1_3 and BT2_7 of the driving unit DU_7 are selectively turned on, and the selection potential of the global bit line GBL is supplied to one end of the selection memory cell MT_7n of the driving unit DU_7 via the select transistors BT1_3 and BT2_7. Similarly, the select transistors BT401_3 and ST2_7 of the driving unit DU_7 are selectively turned on, and the selection potential of the global bit line GBL is supplied to the other end of the selection memory cell MT_7n of the driving unit DU_7 via the select transistors BT401_3 and ST2_7.

[0149] Correspondingly, the channel region CH of the selection memory cell MT_7n in the driving unit DU_7 becomes the selection potential (e.g., +2.5 V). In the selection memory cell MT_7n of the driving unit DU_7, relative to the channel region CH, the word line WL_7n applies an electric field exceeding the negative threshold value (e.g., -5 V) to the insulating film FE on the negative side, causing a negative shift of Vth in the memory cell MT. A "1" can be written to the memory cell MT_7n of the driving unit DU_7. The memory cell MT_7n can remain at "1" as long as its polarization state does not change due to external electric fields, etc.

[0150] At this time, the non-select memory cell MT_7n-1 in the selected drive unit DU_7 and the non-select memory cells MT_3n and MT_3n-1 in the non-select drive unit DU_3 are supplied with the selection potential of the global bit line GBL, but the electric field applied to the insulating film FE on the negative side below the threshold value (e.g. -2.5 V) will not cause writing to the memory cell MT.

[0151] Furthermore, on the +X side, selector transistors ST1_1, ST401_1, ST1_2, ST1_402, ST1_4, and ST401_4 are selectively turned on, and the non-selection potential of the global source line GSL is supplied to the non-selection memory cell MT via selector transistors ST1_1, ST401_1, ST1_2, ST1_402, ST1_4, and ST401_4. Since it is a non-selection potential, it does not cause writing to the memory cell MT.

[0152] Alternatively, when writing a "0" to the select memory cell MT_7n of the drive unit DU_7, as shown in Figure 18, the global bit line GBL is controlled to a "0" selection potential (e.g., +2.5 V), and the global source line GSL is controlled to a non-selection potential (e.g., 0.0 V). As shown in Figures 19 and 20, a "1" selection potential (e.g., +2.5 V) is applied to the word line WL_7n of the select memory cell MT_7n, and a non-selection potential (e.g., 0 V) ​​is applied to the word lines WL_7n-1, WL_3n, and WL_3n-1 of the non-select memory cells MT_7n-1, MT_3n, and MT_3n-1.

[0153] Select gate lines SG1L_3 and SG401L_3 correspond to the select memory cell MT_7n of the drive unit DU7. Select gate lines SG1L_3 and SG401L_3 are controlled to select potentials (e.g., +2.5 V), while other select gate lines are controlled to non-select potentials (e.g., 0 V).

[0154] In Figure 18, the selected gate line SG2_2a, indicated by the diagonal shaded line, is controlled at a selected potential (e.g., -2.5 V), while the other selected gate lines SG1_1a and SG1_3a are controlled at non-selected potentials (e.g., 0.0 V).

[0155] Therefore, on the -X side, the select transistors BT1_3 and BT2_7 of the driving unit DU_7 are selectively turned on, and the selection potential of the global bit line GBL is supplied to one end of the selection memory cell MT_7n of the driving unit DU_7 via the select transistors BT1_3 and BT2_7. Similarly, the select transistors BT401_3 and ST2_7 of the driving unit DU_7 are selectively turned on, and the selection potential of the global bit line GBL is supplied to the other end of the selection memory cell MT_7n of the driving unit DU_7 via the select transistors BT401_3 and ST2_7.

[0156] Correspondingly, the channel region CH of the selection memory cell MT_7n in the driving unit DU_7 becomes the selection potential (e.g., -2.5 V). In the selection memory cell MT_7n of the driving unit DU_7, relative to the channel region CH, the word line WL_7n applies an electric field exceeding the positive threshold value (e.g., +5 V) to the insulating film FE on the positive side, causing a positive shift of Vth in the memory cell MT. "0" can be written to the memory cell MT_7n of the driving unit DU_7. The memory cell MT_7n can remain "0" as long as its polarization state does not change due to external electric fields, etc.

[0157] At this time, the non-select memory cell MT_7n-1 in the selected drive unit DU_7 and the non-select memory cells MT_3n and MT_3n-1 in the non-select drive unit DU_3 are supplied with the selection potential of the global bit line GBL, but the electric field applied to the insulating film FE at a value lower than the threshold (e.g., +2.5 V) will not cause writing to the memory cell MT.

[0158] Furthermore, on the +X side, selector transistors ST1_1, ST401_1, ST1_2, ST1_402, ST1_4, and ST401_4 are selectively turned on, and the non-selection potential of the global source line GSL is supplied to the non-selection memory cell MT via selector transistors ST1_1, ST401_1, ST1_2, ST1_402, ST1_4, and ST401_4. Since it is a non-selection potential, it does not cause writing to the memory cell MT.

[0159] Alternatively, when performing a read operation on the selected memory cell MT_7n of the driving unit DU_7, as shown in Figure 21, the global bit line GBL is controlled to a read selection potential (e.g., +0.5 V), and the global source line GSL is controlled to a non-selection potential (e.g., 0.0 V). As shown in Figures 22 and 23, a read selection potential (e.g., +1.5 V) is applied to the word line WL_7n of the selected memory cell MT_7n, and a non-selection potential (e.g., 0 V) ​​is applied to the word lines WL_7n-1, WL_3n, and WL_3n-1 of the non-selected memory cells MT_7n-1, MT_3n, and MT_3n-1.

[0160] Select gate lines SG1L_3 and SG401R_3 correspond to the selection memory cell MT_7n of the drive unit DU7. Select gate lines SG1L_3 and SG401R_3 are controlled to the selection potential (e.g., +2.5 V), while the other select gate lines are controlled to the non-selection potential (e.g., 0 V).

[0161] In Figure 21, the selected gate line SG2_2a, indicated by the diagonal shaded line, is controlled at a selected potential (e.g., +1.5 V), while the other selected gate lines SG1_1a and SG1_3a are controlled at non-selected potentials (e.g., 0.0 V).

[0162] Therefore, on the -X side, the select transistors BT1_3 and BT2_7 of the driving unit DU_7 are selectively turned on, and on the +X side, the select transistors ST401_3 and ST2_7 of the driving unit DU_7 are selectively turned on. The selection potential of the global bit line GBL is supplied to one end of the selection memory cell MT_7n of the driving unit DU_7 via the select transistors BT1_3 and BT2_7, and the non-selection potential of the global source line GSL is supplied to the other end of the selection memory cell MT_7n of the driving unit DU_7 via the select transistors ST401_3 and ST2_7.

[0163] If a "1" is written into the selection memory cell MT_7n of the driving unit DU_7, the cell current in the channel region CH of the selection memory cell MT_7n flows from the conductive film BL to the conductive film SL, and the potential of the conductive film BL decreases. The sensing amplifier circuit 150 detects the "1" in response to the decrease in the potential of the conductive film BL. Thus, a "1" is read from the selection memory cell MT_7n of the driving unit DU_7. Alternatively, if a "0" is written into the selection memory cell MT_7n of the driving unit DU_7, the cell current in the channel region CH of the selection memory cell MT_7n hardly flows from the conductive film BL to the conductive film SL, and the potential of the conductive film BL is maintained. The sensing amplifier circuit 150 detects the "0" in response to the maintenance of the potential of the conductive film BL. Thus, a "0" is read from the selection memory cell MT_7n of the driving unit DU_7.

[0164] At this time, in the non-selection memory cell MT_7n-1 in the selection drive unit DU_7 and the non-selection memory cells MT_3n and MT_3n-1 in the non-selection drive unit DU_3, the selection potential of the global bit line GBL and the non-selection potential of the global source line GSL are supplied to both ends, but the non-selection potential is supplied to the word lines WL_7n-1, WL_3n, and WL_3n-1. Therefore, in the non-selection memory cell MT_7n-1 in the selection drive unit DU_7 and the non-selection memory cells MT_3n and MT_3n-1 in the non-selection drive unit DU_3, the self-memory cell MT will not be read.

[0165] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0166] 1. 301: Semiconductor memory device 2: Memory Cell Array 81: Interlayer insulating film 100: Peripheral Circuits 110: WL drive circuit 120:SG1 drive circuit 130:SG2 drive circuit 140:SL drive circuit 150: Sensing Amplifier Circuit 200: Interface A: Part BT1, BT1_1~BT1_4, BT2, BT2_1~BT2_12, BT401_1~BT401_4, ST1, ST1_1~ST1_4, ST2, ST2_1~ST2_12, ST401_1~ST401_4, vBL_1~vBL_m: Select transistor CH: Channel area CL: Connector Layer CN1, CN2, SG1_1a, SG1_1b, SG1_2a, SG1_2b, SG1_3a, SG1_3b, SG1_4a, SG1_4b, SG1_5a, SG1_5b, SG1_ 6a, SG1_6b, SG1_7a, SG1_7b, SG1_8a, SG1_8b, SG2_1a, SG2_1b, SG2_2a, SG2_2b, SG2_3a, SG2_3b: conductive film DU_1~DU_m: Drive units FE, IF1, IF4, IF5, IF5d, IF5u: Insulating film GBL: Global Bitline GSL: Global Source Line IF2: Insulation layer IF3: Slit L1, L2, L301d, L301u, L401: Select gate layer L3: Array layer LBL: Local Bit Line LSL: Local Source Line MG: Memory Cell Cluster MT, MT_1, MT_n, MT_n-1: Memory cells MT_3n, MT_3n-1, MT_7n-1: Non-selective memory cells MT_7n: Select memory cell PL1~PL13: columnar bodies SB:Substrate SG1_1~SG1_4, SG2_1: Select gate line SM1, SM2, SM101, SM202, SM301: Select the organization SST: Laminar Matrix vBL: Vertical Bitline vSL, vSL_1~vSL_m: Vertical source lines WL, WL_1~WL_n-1: Character lines X, Y, Z: Direction

Claims

1. A semiconductor memory device, comprising: Multiple first memory cells are stacked on top of a substrate and connected side-by-side between a first vertical bit line extending along the stacking direction and a first vertical source line extending along the stacking direction. And a first selection mechanism, disposed between the substrate and the plurality of first memory cells in the stacking direction, selectively connects the first vertical bit line to the first local bit line, and selectively connects the first vertical source line to the first local source line.

2. The semiconductor memory device as claimed in claim 1, further comprising: A second selection mechanism is disposed between the substrate and the first selection mechanism in the stacking direction, and selects the first local bit line to connect to the global bit line and the first local source line to connect to the global source line.

3. The semiconductor memory device of claim 1, wherein the first selection mechanism comprises: a first selection transistor having a drain connected to the first vertical bit line and a source connected to a first local bit line; and a second selection transistor having a drain connected to the first vertical source line and a source connected to the first local source line.

4. The semiconductor memory device of claim 2, wherein the first selection mechanism comprises: a first selection transistor with its drain connected to the first vertical bit line and its source connected to the first local bit line; and a second selection transistor with its drain connected to the first vertical source line and its source connected to the first local source line; the second selection mechanism comprises: a third selection transistor with its drain connected to the first local bit line and its source connected to the global bit line; and a fourth selection transistor with its drain connected to the first local source line and its source connected to the global source line.

5. The semiconductor memory device as claimed in claim 3, wherein the gate of the first select transistor and the gate of the second select transistor are connected together to the first select gate line.

6. The semiconductor memory device of claim 4, wherein the gate of the first select transistor and the gate of the second select transistor are connected together to a first select gate line, the gate of the third select transistor is connected to a second select gate line, and the gate of the fourth select transistor is connected to a third select gate line.

7. The semiconductor memory device of claim 5, wherein the first select transistor has a first columnar body comprising a semiconductor and extending along the stacking direction, the second select transistor has a second columnar body comprising a semiconductor and extending along the stacking direction, the first select transistor and the second select transistor are adjacent to each other in a first direction perpendicular to the stacking direction, the first select gate line has a first conductive film extending along the first direction and covering the side surfaces of the first columnar body and the second columnar body respectively via an insulating film.

8. The semiconductor memory device of claim 5, wherein the first select transistor has a first columnar body comprising a semiconductor and extending along the stacking direction, the second select transistor has a second columnar body comprising a semiconductor and extending along the stacking direction, the first select transistor and the second select transistor are adjacent to each other in a first direction perpendicular to the stacking direction, and the first select gate line has: a first conductive film extending along the first direction and covering a first side surface of the first columnar body and a first side surface of the second columnar body respectively via an insulating film; and a second conductive film extending along the first direction on opposite sides of the first select transistor and the second select transistor being intermediate, and covering a second side surface of the first columnar body and a second side surface of the second columnar body respectively via an insulating film.

9. The semiconductor memory device of claim 6, wherein the first select transistor has a first columnar body comprising a semiconductor and extending along the stacking direction; the second select transistor has a second columnar body comprising a semiconductor and extending along the stacking direction; the first select transistor and the second select transistor are adjacent to each other in a first direction perpendicular to the stacking direction; the first select gate line has a first conductive film extending along the first direction and covering the side surfaces of the first columnar body and the second columnar body respectively via an insulating film; the third select transistor has a third columnar body comprising a semiconductor and extending along the stacking direction; the fourth select transistor has a fourth columnar body comprising a semiconductor and extending along the stacking direction; the second select gate line has a third conductive film extending along a second direction perpendicular to both the stacking direction and the first direction and covering the side surfaces of the third columnar body via an insulating film; the third select gate line has a fourth conductive film extending along the second direction and covering the side surfaces of the third columnar body via an insulating film.

10. The semiconductor memory device of claim 6, wherein the first select transistor has a first columnar body comprising a semiconductor and extending along the stacking direction, the second select transistor has a second columnar body comprising a semiconductor and extending along the stacking direction, the first select transistor and the second select transistor are adjacent to each other in a first direction perpendicular to the stacking direction, and the first select gate line has: a first conductive film extending along the first direction and covering a first side surface of the first columnar body and a first side surface of the second columnar body respectively via an insulating film; The second conductive film extends along the first direction on opposite sides of the first and second selective transistors, with the first and second selective transistors positioned as the middle, and covers the second side surfaces of the first columnar body and the second columnar body respectively via an insulating film. The third selective transistor has a third columnar body containing a semiconductor and extending along the stacking direction. The fourth selective transistor has a fourth columnar body containing a semiconductor and extending along the stacking direction. The second selective gate line has a third conductive film extending along a second direction perpendicular to the stacking direction and the first direction, and covers the side surface of the third columnar body via an insulating film. The third selective gate line has a fifth conductive film extending along the second direction on the opposite side of the third selective transistor being positioned in the middle, and covering the second side of the third column via an insulating film. The third selective gate line has a fourth conductive film extending along the second direction and covering the side of the fourth column via an insulating film. And a sixth conductive film, extending along the second direction on the opposite side where the fourth selective transistor is positioned, and covering the second side of the fourth columnar body via an insulating film.

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