Bonded semiconductor structure and method for forming the same

TWI937763BActive Publication Date: 2026-09-01UNITED MICROELECTRONICS CORP
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Patent Information

Application Number
TW114110219
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-03-19
Publication Date
2026-09-01
Estimated Expiration
2045-03-18

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    Figure TWG2TB001908751_003
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Abstract

A semiconductor structure is bonded, including a first wafer having a first through-silicon via (TSV), and a second wafer bonded to the first wafer. The second TSV passes through the second wafer and includes a lower portion that is in direct contact with and electrically connected to the first TSV, and an upper portion disposed on the lower portion. The sidewalls of the lower portion, the bottom surface of the upper portion, and the sidewalls of the upper portion form a stepped profile.
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Claims

1. A junction semiconductor structure, comprising: A first wafer, including a first through-silicon via; A second wafer, bonded to the first wafer; a second through-silicon via, passing through the second wafer, comprising: a lower portion, directly contacting and electrically connected to the first through-silicon via; and an upper portion disposed on the lower portion, wherein a sidewall of the lower portion, a bottom surface of the upper portion, and a sidewall of the upper portion form a stepped profile; an etch stop layer, located in the second wafer and directly contacting the sidewall of the upper portion of the second through-silicon via, wherein a top surface of the etch stop layer is flush with a surface of a semiconductor substrate of the second wafer; and a liner disposed along the sidewall of the upper portion of the second through-silicon via, wherein a bottom surface of the liner directly contacts the top surface of the etch stop layer.

2. The bonding semiconductor structure as described in claim 1, wherein the width of the lower portion is smaller than the width of the upper portion.

3. The bonding semiconductor structure as described in claim 1, wherein the width of the lower portion is smaller than the width of the first through-silicon via.

4. The bonding semiconductor structure as described in claim 1 further includes a barrier layer disposed along the lower sidewall, the upper bottom surface, and the upper sidewall.

5. The bonding semiconductor structure as described in claim 1 further includes a conductive structure disposed in the second wafer, wherein the lower sidewall and the upper bottom surface of the second through-silicon via are in direct contact with and electrically connected to the conductive structure.

6. The bonding semiconductor structure as described in claim 1 further includes a bonding layer located between the first wafer and the second wafer, and directly contacting the lower sidewall of the second through-silicon via and a top surface of the first through-silicon via.

7. The bonding semiconductor structure as described in claim 1 further includes a bonding pad disposed on the second wafer and overlapping the upper portion of the second through-silicon via.

8. The bonding semiconductor structure as described in claim 1 further includes: A third wafer is bonded to the second wafer and is disposed opposite to the first wafer; a third through-silicon via passes through the third wafer and is in direct contact with and electrically connected to the second through-silicon via.

9. A method for manufacturing a bonded semiconductor structure, comprising: A first wafer is provided, the first wafer including a first through-silicon via; a second wafer is bonded to the first wafer; a first etching process is performed to form an opening in the second wafer, the opening exposing a top surface of an etch stop layer of the second wafer, the top surface of the etch stop layer being flush with a surface of a semiconductor substrate of the second wafer; a liner is formed on a sidewall of the opening and on the top surface of the etch stop layer; a second etching process is performed to extend the opening through the etch stop layer and the second wafer, exposing a top surface and sidewall of a conductive structure of the second wafer and a top surface of the first through-silicon via of the first wafer; and a second through-silicon via is formed within the opening.

10. A method for manufacturing a semiconductor structure as described in claim 9, wherein the second through-silicon via comprises: The lower part is in direct contact with and electrically connected to the first through-hole in silicon; and the upper part is disposed on the lower part, wherein a side wall of the lower part, a bottom surface of the upper part, and a side wall of the upper part form a stepped profile.

11. The method of manufacturing a bonded semiconductor structure as described in claim 10, wherein the width of the lower portion is smaller than the width of the upper portion.

12. The method of manufacturing a bonding semiconductor structure as described in claim 10, wherein the width of the lower portion is smaller than the width of the first through-silicon via.

13. The method for manufacturing a bonding semiconductor structure as described in claim 9, wherein the step of forming the second through-silicon via includes: A barrier layer is formed on one side wall of the opening, and the barrier layer is in direct contact with the conductive structure. And a conductive material is formed to fill the opening.

14. A method for manufacturing a bonded semiconductor structure as described in claim 9, wherein the second through-silicon via is electrically connected to the conductive structure and the first through-silicon via.

15. A method for manufacturing a semiconductor structure as described in claim 9, wherein the second wafer is bonded to the first wafer by fusion bonding.

16. The method for manufacturing a bonding semiconductor structure as described in claim 9 further includes forming a bonding pad on the second wafer, the bonding pad overlapping the second through-silicon via.

17. The method for manufacturing a bonded semiconductor structure as described in claim 9 further includes: A bonding layer is formed on the second wafer, the bonding layer covering the second through-silicon via; And a third wafer is bonded to the second wafer through the bonding layer.

Citation Information

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