Gate all around device and method of forming the same

Abstract

A horizontally surrounding gate (hGAA) device and a method for manufacturing the same are described herein. The hGAA device includes an oxide layer and a semiconductor material layer located between the source and drain regions of the device. The method includes the steps of: growing a conformal epitaxial layer on a nanosheet channel layer, followed by radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer. An alternative method includes the steps of: growing a conformal epitaxial layer on a nanosheet channel layer, followed by surface treatment, and then radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer.

Description

Wrap-around gate element and its formation method Generally speaking, the embodiments of this disclosure relate to methods for filling substrate features. More specifically, the embodiments of this disclosure relate to methods for forming high-quality I / O oxides. Transistors are critical components in most integrated circuits. Since the drive current and resulting speed of a transistor are proportional to its gate width, faster transistors typically require larger gate widths. Therefore, a trade-off must be made between transistor size and speed, and "fin-field-effect transistors" (finFETs) have been developed to resolve this conflicting goal of achieving the maximum drive current and the smallest size. FinFETs are characterized by fin-shaped channel regions, which can significantly increase the transistor's size without substantially increasing its footprint, and are now used in many integrated circuits. However, finFETs have their own drawbacks. As transistor feature sizes continue to shrink to achieve greater circuit density and higher efficiency, improved transistor structures are needed to improve electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage. Examples of transistor structures include planar structures, FinFET structures, and horizontal gate-all-around (hGAA) structures. The hGAA structure includes several lattice-matched channels suspended in a stacked configuration and connected via source / drain regions. The hGAA structure provides good electrostatic control and is widely applicable to complementary metal-oxide-semiconductor (CMOS) wafer fabrication. Conventional I / O oxide processes result in the immediate re-growth of poor-quality native oxides after ex-situ pre-cleaning, low-density ALD-type oxide deposition, linear reduction in nanosheet-to-nanosheet space deposition, limitations on downstream integration (i.e., multi-Vt), and the need for additional post-processing to densify the ALD film, which increases cost and complexity. Therefore, there is a need for improved methods for forming horizontally wrapped gate devices. One or more embodiments of this disclosure relate to a method of forming a semiconductor device. In one or more embodiments, the method of forming a semiconductor device includes the following steps: pre-cleaning a plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a first thickness; forming a conformal sacrificial epitaxial layer on each of the plurality of nanosheet channel layers; pre-cleaning the plurality of nanosheet channel layers on which a conformal sacrificial epitaxial silicon layer has been formed to remove native oxides and / or residues; and oxidizing the conformal sacrificial epitaxial silicon layer using plasma to form a silicon oxide layer on a nanosheet having a second thickness. Further embodiments of this disclosure relate to a method of forming a semiconductor device. In one or more embodiments, the method of forming a semiconductor device includes the steps of: pre-cleaning a plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a first thickness; forming a conformal sacrificial epitaxial layer on each of the plurality of nanosheet channel layers; annealing the plurality of nanosheet channel layers having the conformal sacrificial epitaxial layer thereon; and oxidizing the conformal sacrificial epitaxial layer using plasma to form an oxide layer on each of the plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a second thickness. Additional embodiments of this disclosure relate to horizontally wrapped gate devices. In one or more embodiments, the horizontally wrapped gate device includes: a plurality of horizontal nanosheet channel layers located between a source region and a drain region, each of the plurality of horizontal nanosheet channel layers having a top surface, a bottom surface, and two side surfaces, and having a first channel layer thickness in the range of 2 nm to 15 nm; and an oxide layer located on the top surface, bottom surface, and two side surfaces of each of the plurality of horizontal nanosheet channel layers, the oxide layer having an oxide layer thickness in the range of about 2.5 nm to about 10 nm. The first channel layer thickness is substantially equal to the second channel layer thickness before the formation of the oxide layer. Further embodiments of this disclosure relate to computer-readable media. In one or more embodiments, the non-transitory computer-readable media includes instructions that, when executed by a controller of a process chamber, cause the process chamber to perform the following operations: pre-clean a plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a first thickness; form a conformal sacrificial epitaxial layer on each of the plurality of nanosheet channel layers; anneal the plurality of nanosheet channel layers having the conformal sacrificial epitaxial layer thereon; and oxidize the conformal sacrificial epitaxial layer using plasma to form an oxide layer on each of the plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a second thickness. Additional embodiments of this disclosure relate to computer-readable media. In one or more embodiments, the non-transitory computer-readable media includes instructions that, when executed by a controller of a process chamber, cause the process chamber to perform the following operations: pre-clean a plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a first thickness; form a conformal sacrificial epitaxial layer on each of the plurality of nanosheet channel layers; pre-clean the plurality of nanosheet channel layers having a conformal sacrificial epitaxial silicon layer thereon to remove native oxides and / or residues; and oxidize the conformal sacrificial epitaxial silicon layer using plasma to form a silicon oxide layer on a nanosheet having a second thickness. Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the setup or processing set forth in the following specification. This disclosure can have other embodiments and can be implemented or performed in various ways. As used in this specification and the accompanying claims, the term "substrate" refers to a surface, or a portion of a surface, on which the process is performed. Those skilled in the art to which this application pertains will also understand that, unless the context clearly indicates otherwise, reference to a substrate may refer only to a portion of a substrate. Furthermore, reference to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon. As used herein, "substrate" refers to any substrate or material surface formed on a substrate, on which a film treatment is performed during the manufacturing process. For example, depending on the application, substrate surfaces on which treatment can be performed may include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials (such as metals, metal nitrides, metal alloys, and other conductive materials). Substrates may include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes such as grinding, etching, reduction, oxidation, hydroxylation (or generating or grafting target chemical moieties to impart chemical functionality), annealing, and / or baking of the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, any of the film treatment procedures disclosed herein (as described in more detail below) may also be performed on an underlayer formed on the substrate, and the term "substrate surface" is intended to include such an underlayer as referred to herein. Thus, for example, when a film / layer or a portion thereof has been deposited onto the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface contains will depend on the film to be deposited and the specific chemical substances used. As used in this specification and the accompanying claims, the terms "precursor," "reactant," "reactive gas," etc., are used interchangeably to refer to any gaseous species that can react with the substrate surface. A transistor is a circuit component or unit typically formed on a semiconductor device. Depending on the circuit design, transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other units. Typically, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric, which is interposed between the gate electrode and the channel region in the substrate. As used herein, the term "field-effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of a component. Enhancement-mode field-effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by an electric field within the component, generated by the voltage difference between the component's body and gate. The three terminals of a FET are: source (S), through which the carrier enters the channel; drain (D), through which the carrier exits the channel; and gate (G), used to regulate the channel conductivity. Typically, the current entering the channel at the source (S) is denoted as I0. S The current entering the channel at the drain (D) is labeled as I. D The drain-to-source voltage is denoted as V. DS By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I) can be controlled. D ). A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate whose voltage determines the conductivity of the device. This ability to change conductivity by applying a voltage is used to amplify or switch electronic signals. A MOSFET regulates the charge concentration based on the metal-oxide-semiconductor (MOS) capacitance between the host electrode and the gate electrode, which is located above the host and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a highly doped region separated by the host region. These regions can be p-type or n-type, but they are of the same type and opposite to the type of the host region. A "+" sign following the doping type indicates that the source and drain (different from the host) are highly doped. If the MOSFET is an n-channel or nMOS FET, then the source and drain are in the n+ region and the bulk is in the p region. If the MOSFET is a p-channel or pMOS FET, then the source and drain are in the p+ region and the bulk is in the n region. The source is called this because it is the origin of the charge carriers flowing through the channel (electrons for an n-channel and holes for a p-channel); similarly, the drain is where the charge carriers leave the channel. As used herein, the term "FinFET" refers to a MOSFET transistor built on a substrate, where the gate is located on two or three sides of the channel, forming a dual-gate or triple-gate structure. Because the channel region forms "fins" on the substrate, the common name for a FinFET device is FinFET. FinFET devices feature fast switching times and high current densities. As used herein, the term "gate all-around (GAA)" is used to refer to an electronic element (e.g., a transistor) in which gate material surrounds all sides of a channel region. The channel region of a GAA transistor may include nanowires or nano-slabs or nanosheets, rod-shaped channels, or other suitable channel configurations known to those skilled in the art to which this application pertains. In one or more embodiments, the channel region of a GAA element has multiple vertically spaced horizontal nanowires or horizontal rods, thereby making the GAA transistor a stacked horizontal gate all-around (hGAA) transistor. As used in this article, the term "nanowire" refers to a device with nanometer-scale (10⁻⁶) wires. −9 Nanowires are nanostructures with a diameter of approximately 1 meter. A nanowire can also be defined as a length-to-width ratio greater than 1000. Alternatively, a nanowire can be defined as a structure with a thickness or diameter limited to tens of nanometers or less and an unlimited length. Nanowires are used in transistors and some laser applications, and in one or more embodiments, are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) components. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure with a thickness ranging from about 0.1 nm to about 1000 nm. In one or more embodiments, a gate-all-around transistor is fabricated using a standard process flow. After removing the pseudo-gate, a sacrificial epitaxial layer (e.g., an epitaxial silicon layer) is conformally grown on all sides of the silicon nanosheet. In one or more embodiments, the substrate undergoes an optional first pre-cleaning to remove organic residues. Subsequently, the substrate is subjected to a second pre-cleaning to remove native oxides, such as silicon oxide (SiO2), at the interfaces of the silicon nanosheets. xThe substrate is then subjected to conformal radical plasma oxidation (RPO) and spacer treatment. As used herein, the term "conformal" means that the layer conforms to the feature or the profile of the layer. The conformality of the layer is typically quantified by the ratio of the average thickness of the layer deposited on the sidewalls of the feature to the average thickness of the same deposited layer on the field or upper surface of the substrate. Embodiments of this disclosure are described by way of diagrams, which depict elements (e.g., transistors) and processes for forming transistors according to one or more embodiments of this disclosure. The processes shown are merely illustrative possible uses of the disclosed processes, and those skilled in the art to which this application pertains will understand that the disclosed processes are not limited to the illustrative applications. One or more embodiments of this disclosure are described with reference to the accompanying drawings. In one or more embodiments, a gate-all-around transistor is fabricated using a standard process flow. In one or more embodiments, after removing the pseudo-gate, a conformal sacrificial epitaxial layer is grown on the nanosheet for integrated ( In-situ pre-cleaning is performed to remove the gate-like oxide. In one or more embodiments, the gate-like oxide is removed, followed by conformal sacrificial epitaxial layer growth without vacuum disruption. Vacuum break may occur between the epitaxial layer and the pre-cleaning RP. In other embodiments, a gate-all-around transistor is fabricated using a standard process flow, and after removing the gate-like electrode, a conformal sacrificial epitaxial layer is grown on the nanosheet, followed by an integrated surface treatment to improve mobility and bias temperature instability (BTI). In one or more embodiments, the surface treatment is performed, followed by the growth of the conformal sacrificial epitaxial layer without vacuum disruption. In some embodiments, vacuum disruption may occur between epitaxy and surface treatment. Figure 1A is a process flow diagram of method 100A for forming a semiconductor device according to some embodiments of the present disclosure. Method 100A is described below with reference to Figures 2A to 6B, which depict the manufacturing stages of a semiconductor structure according to some embodiments of the present disclosure. Figure 1B is a process flow diagram of method 100B for forming a semiconductor device according to some embodiments of the present disclosure. Method 100B is described below with reference to Figures 2A to 6B, which depict the manufacturing stages of a semiconductor structure according to some embodiments of the present disclosure. Figures 2A to 6B are cross-sectional views of an electronic device (e.g., hGAA) according to one or more embodiments. Methods 100A and 100B may be part of a multi-step process for the semiconductor device. Therefore, methods 100A and 100B can be performed in any suitable process chamber coupled to clustering tools. Clustering tools may include process chambers for manufacturing semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chambers for manufacturing semiconductor devices. Methods 100A and 100B commence at operation 102 by providing a substrate 200 having a top surface 202 (as illustrated in Figure 2A). In some embodiments, the substrate 200 may be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate in which the entire substrate is composed of a semiconductor material. A bulk semiconductor substrate may comprise any suitable semiconductor material and / or a combination of semiconductor materials used to form a semiconductor structure. For example, the semiconductor layer may comprise one or more materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 200 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon-germanium (SiGe), germanium-tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 200 comprises one or more of the following: silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although some examples of materials that can form a substrate have been described herein, any material that can serve as the basis for passive and active electronic components (such as transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic components, or any other electronic components) falls within the spirit and scope of this disclosure. In some embodiments, the semiconductor material may be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, any suitable process, such as ion implantation, may be used to dope the substrate. As used herein, the term "n-type" refers to a semiconductor generated during manufacturing by doping an intrinsic semiconductor with an electron donor element. The term n-type derives from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of a well (or hole). In contrast to an n-type semiconductor, a p-type semiconductor has a greater hole concentration than an electron concentration. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of the following: boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopant, or a combination thereof. In some embodiments, to prevent parasitic bottom element activation, the substrate may be doped to provide a high dose of dopant at a first location on the surface of the substrate 200. In one or more embodiments, a superlattice structure 204 is formed on top of the first location. For example, in some embodiments, the surface of the substrate may have about 10 18 atoms / cm 3 To about 10 19 atoms / cm 3 The dopant density. At least one superlattice structure 204 (as depicted in Figure 2A) is formed on top of the top surface 202 of the substrate 200. The superlattice structure 204 includes a plurality of semiconductor material layers 226 arranged alternately in a plurality of stacked pairs and corresponding plurality of nanosheet channel layers 224. In some embodiments, the group of stacked layers includes silicon (Si) and silicon germanium (SiGe). In some embodiments, the plurality of semiconductor material layers 226 include silicon germanium (SiGe), and the plurality of nanosheet channel layers 224 include silicon (Si). In other embodiments, the plurality of nanosheet channel layers 224 include silicon germanium (SiGe), and the plurality of semiconductor material layers include silicon (Si). In some embodiments, the plurality of semiconductor material layers 226 and the corresponding plurality of nanosheet channel layers 224 may contain any number of lattice-matching material pairs suitable for forming the superlattice structure 204. In some embodiments, the plurality of semiconductor material layers 226 and the corresponding plurality of nanosheet channel layers 224 contain from about 2 to about 50 pairs of lattice-matching materials. In one or more embodiments, the thickness of the plurality of semiconductor material layers 226 and the plurality of nanosheet channel layers 224, t 1. In the range of about 2 nm to about 50 nm, in the range of about 3 nm to about 20 nm, or in the range of about 2 nm to about 15 nm. In some embodiments, dielectric material 246 is deposited on substrate 200 using a conventional chemical vapor deposition method. In some embodiments, dielectric material 246 is recessed below the top surface 202 of substrate 200, such that substrate 200 forms the bottom portion of superlattice structure 204. In some embodiments, an alternative gate structure (e.g., a simulated gate structure 208) is formed above and adjacent to the superlattice structure 204. The simulated gate structure 208 defines a channel region for a transistor element. The simulated gate structure 208 can be formed using any suitable conventional deposition and patterning process known in the art to which this application pertains. In some embodiments, sidewall spacers 210 are formed along the outer sidewall of the gate-like structure 208. In some embodiments, the sidewall spacers 210 comprise suitable insulating materials known in the art to which this application pertains, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. In some embodiments, the sidewall spacers 210 are formed using any suitable conventional deposition and patterning process known in the art to which this application pertains, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition. In some embodiments, embedded source regions 232 and drain regions 234 are formed in source trenches and drain trenches, respectively. In some embodiments, source region 232 is formed near a first end of superlattice structure 204, and drain region 234 is formed near a opposite second end of superlattice structure 204. In the embodiment illustrated in Figure 2A, one of source region 232 or drain region 234 is not shown on the front face of superlattice structure 204. The other end of superlattice structure 204 has the other of source region 232 or drain region 234. In some embodiments, source region 232 and / or drain region 234 are formed of any suitable semiconductor material, such as, but not limited to, silicon, germanium, silicon germanium, silicon phosphorus, silicon arsenic, etc. In some embodiments, any suitable deposition process, such as epitaxial deposition, can be used to form source region 232 and drain region 234. In some embodiments, an inter-layer dielectric (ILD) layer 220 is deposited over a substrate 200 including source / drain regions 232, 234, the gate-like structure 208, and sidewall spacers 210. The ILD layer 220 can be deposited using conventional chemical vapor deposition methods, such as plasma-enhanced chemical vapor deposition and low-pressure chemical vapor deposition. In one or more embodiments, the ILD layer 220 is formed from any suitable dielectric material, such as, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride. In one or more embodiments, the ILD layer 220 is then polished back using conventional chemical mechanical planarization methods to expose the top of the gate-like structure 208. In some embodiments, the ILD layer 220 is polished to expose the top of the gate-like structure 208 and the top of the sidewall spacers 210. As shown in Figure 2B, in operation 104, the simulated gate structure 208 is removed to expose the channel region 214 of the superlattice structure 204. During the removal of the simulated gate structure 208, the ILD layer 220 protects the source / drain regions 232, 234. The simulated gate structure 208 can be removed using any conventional etching method, such as dry plasma etching or wet etching. In some embodiments, the simulated gate structure 208 comprises polysilicon and is removed by a selective etching process. In some embodiments, the simulated gate structure 208 comprises polysilicon, and the superlattice structure 204 comprises alternating layers of silicon (Si) and silicon-germanium (SiGe). As shown in Figure 2C, in operation 106, a plurality of semiconductor material layers 226 between a plurality of nanosheet channel layers 224 in the superlattice structure 204 are selectively etched. For example, when the superlattice structure 204 is composed of silicon (Si) layers and silicon-germanium (SiGe) layers, silicon-germanium (SiGe) is selectively etched to form channel nanowires 240. Any known etchant that is selective to the plurality of nanosheet channel layers 224 can be used to remove the plurality of semiconductor material layers 226, such as silicon-germanium (SiGe), wherein the etchant etches the plurality of semiconductor material layers 226 at a rate significantly higher than that of the plurality of nanosheet channel layers 224. In some embodiments, selective dry etching or wet etching processes can be used. In some embodiments, when the plurality of nanosheet channel layers 224 are silicon (Si) and the plurality of semiconductor material layers 226 are silicon germanium (SiGe), a wet etchant can be used to selectively remove the silicon germanium layers. The wet etchant can be, for example, but not limited to, an aqueous carboxylic acid / nitric acid / HF solution and an aqueous citric acid / nitric acid / HF solution. The removal of the plurality of semiconductor material layers 226 leaves pores 228 between the plurality of nanosheet channel layers 224. The pores 228 between the plurality of nanosheet channel layers 224 have a thickness of about 3 nm to about 20 nm. The remaining nanosheet channel layers 224 form a vertical array of channel nanowires 240 coupled to source / drain regions 232, 234. The channel nanowires 240 travel parallel to the top surface 202 of the substrate 200 and are aligned with each other to form a single row of channel nanowires 240. The formation of source region 232 and drain region 234 and the optional lateral etch stop layer advantageously provide self-alignment and structural integrity in the formation of the channel structure. In some embodiments, after removing the pseudo-gate, an integrated ( In-situ pre-cleaning. Perform pre-cleaning on components. In-situ pre-cleaning removes any oxides on the gate. Pre-cleaning removes native oxides present on the gate surface. Pre-cleaning processes may include dry etching, wet etching, or a combination of both. The isotropic etching process of operation 106 may include any suitable etching process that selectively etches the semiconductor material of the plurality of nanosheet channel layers 224. In some embodiments, the isotropic etching process of operation 106 includes one or more of a wet etching process or a dry etching process. In some embodiments, the isotropic etching process of operation 106 includes a dry etching process. In such embodiments, the dry etching process may include conventional plasma etching or remote plasma-assisted dry etching processes, such as SiCoNi available from Applied Materials, Inc., located in Santa Clara, California. TM Etching process. In SiCoNi TM During the etching process, the components are exposed to H 2. NF 3 and / or NH 3. Plasma species, such as plasma-excited hydrogen and fluorine species. For example, in some embodiments, the element may be simultaneously exposed to H... 2. NF 3 and NH 3. Plasma. It can be used in SiCoNi... TM SiCoNi was carried out in the pre-cleaned chamber TM Etching process, SiCoNi TM The pre-cleaning chamber can be integrated into one of a variety of multiprocessing platforms, including those from Applied Materials. ® Centura ® Dual ACP, Producer ® GT and Endura ® Platform. Wet etching processes may include hydrofluoric acid (HF) lasting processes, i.e., HF etching of the surface in a so-called "HF last" process to leave a hydrogen-terminated surface. Alternatively, any other liquid-based pre-epitaxy pre-cleaning process may be used. In some embodiments, the process includes sublimation etching to remove native oxides. The etching process may be plasma-based or thermal-based. Plasma processes may be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma). Please refer to Figures 2D and 2E, which are enlarged cross-sectional views 245a and 245b of the substrate in Figure 2C. In one or more embodiments, the thickness of the plurality of nanosheet channel layers 224 is t 1. In the range of about 2 nm to about 50 nm, in the range of about 3 nm to about 20 nm, or in the range of about 2 nm to about 15 nm. A plurality of nanosheet channel layers 224 extend between source / drain regions 232 / 234. Referring to Figures 3A and 3B, in operation 108, a sacrificial epitaxial layer 250 is conformally grown or formed on a plurality of nanosheet channel layers 224. In some embodiments, the conformal sacrificial epitaxial layer 250 comprises silicon (Si). An epitaxial regrowth process is performed on each of the plurality of nanosheet channel layers 224 through an aperture 228. In some embodiments, the epitaxial regrowth process is a selective epitaxy process. In some embodiments, the selective epitaxy process epitaxially grows the sacrificial epitaxial layer 250 through the aperture 228 (also referred to as a trench) in an epitaxial manner. In some embodiments, the epitaxial growth causes the sacrificial epitaxial layer 250 to merge into the contacts of the nanosheet channel layer 224. In some embodiments, the plurality of nanosheet channel layers 224 comprise silicon, and epitaxy causes the nanosheet channel layers 224 to merge and pinch off the aperture 228. In some embodiments, the epitaxial process results in the growth of Si <100>. In some embodiments, the epitaxial process results in the growth of Si <110>. In some embodiments, the epitaxial process results in contacts having a conical, flat-topped, or truncated conical shape. In some embodiments, epitaxial regeneration of operation 108 is performed at a lower temperature than conventional epitaxial processes. In one or more embodiments, epitaxial regeneration is performed at temperatures ranging from 500 °C to 900 °C, or from 500 °C to 800 °C, or from 500 °C to 750 °C, or from 500 °C to 720 °C. In one or more embodiments, epitaxial regeneration is performed at pressures ranging from 5 to 20 tors. In one or more embodiments, the sacrificial epitaxial layer 250 comprises epitaxially grown silicon (Si). In some embodiments, the thickness of the sacrificial epitaxial layer 250 is in the range of about 0.5 nm to about 2.5 nm, or in the range of about 1.2 nm to about 2.5 nm, or in the range of about 1.5 nm to about 2.5 nm. Please refer to Figure 1A. In method 100A, during operation 110, the component passes through... In-situ pre-cleaning removes any oxides on the sacrificial epitaxial layer. Pre-cleaning can remove native oxides present on the surface of the sacrificial epitaxial layer. The pre-cleaning process may include a dry etching process, a wet etching process, or a combination of both. In some embodiments, operations 104 and 106 are integrated to prevent vacuum damage. In some embodiments, operations 110 and 112 are integrated to prevent vacuum damage. In some embodiments, the apparatus or process tooling is configured to maintain the substrate under vacuum conditions to prevent the formation of an oxide layer after the pre-treatment cleaning process of operation 110. In embodiments of this type, the process tooling is configured to move the substrate from the pre-cleaning chamber to the etching process chamber without exposing the substrate to atmospheric conditions. Referring to Figure 1B, in one or more alternative embodiments, during operation 111 of method 100B, the element undergoes a surface treatment to improve mobility and reduce bias temperature instability (BTI). In one or more embodiments, the surface treatment includes hydrogen (H) 2) Annealing in an atmosphere. Annealing may be any suitable annealing process known to those skilled in the art to which this application pertains. In some embodiments, annealing is rapid heat treatment (RTP) annealing. In some embodiments, annealing is performed at temperatures ranging from 500 °C to 900 °C, or from 600 °C to 900 °C, or from 600 °C to 800 °C. In some embodiments, annealing is performed at pressures ranging from 5 to 20 tors. In some embodiments, operations 104 and 106 are integrated to prevent vacuum disruption. In some embodiments, operations 111 and 112 are integrated to prevent vacuum disruption. In some embodiments, the apparatus or process tool is configured to maintain the substrate under vacuum conditions to prevent the formation of an oxide layer after the surface treatment of operation 111. In embodiments of this type, the process tool is configured to move the substrate from a surface treatment chamber (e.g., an annealing chamber) to a plasma oxidation chamber for operation 112 without exposing the substrate to atmospheric conditions. Please refer to Figures 4A and 4B. In the prior art process, direct radical plasma oxidation (RPO) of the device forms an oxide layer 255, resulting in the consumption of silicon nanosheets (i.e., a plurality of nanosheet channel layers 224). Therefore, according to the prior art, the thickness of the plurality of nanosheet channel layers 224 after RPO, t n The thickness of the multiple nanosheet channel layers 224 before RPO is less than t 1. Referring to Figures 5A and 5B, in one or more embodiments, during operation 112, an oxide layer 260 is formed on a plurality of nanosheet channel layers 224. In one or more embodiments, hydrogen (H₂O) is produced at ambient pressure at a temperature ranging from about 700 °C to about 900 °C. 2) Gas and oxygen (O) 2) In an atmosphere of free radical plasma (RPO) oxidation of the sacrificial epitaxial layer 250, an oxide layer 260 is formed. The oxide layer 260 may comprise any suitable material known to those skilled in the art to which this invention pertains. In one or more embodiments, the oxide layer 260 comprises silicon oxide (SiO₂). x In one or more embodiments, the sacrificial epitaxial layer 250 comprises silicon (Si), and the oxide layer 260 comprises silicon oxide (SiO2). x ). Figure 5A is a schematic diagram illustrating how an oxide layer 260 is grown on a plurality of nanosheet channel layers 224. In one or more embodiments, the oxide layer 260 is conformally grown (or formed) on the surface of the plurality of nanosheet channel layers 224. Because the sacrificial epitaxial layer 250 is directly oxidized, the oxide layer 260 is dense. Oxidation consumes the sacrificial epitaxial layer 250 while advantageously not consuming the nanosheet channel layers 224. In one or more embodiments, the sacrificial epitaxial layer 250 comprises silicon (Si), and the oxide layer 260 comprises silicon oxide (SiO₂). x ), and silicon oxide (SiO) x The ratio of silicon (Si) to silicon is approximately 3:1. In one or more embodiments, after RPO oxidation, the plurality of nanosheet channel layers 224 have a second thickness, t 2. In one or more embodiments, the second thickness of the plurality of nanosheet channel layers 224, t 2. In the range of about 2 nm to about 50 nm, in the range of about 3 nm to about 20 nm, in the range of about 2 nm to about 15 nm, in the range of 2.5 nm to 10 nm, in the range of 4 nm to 8 nm, or in the range of 2.5 nm to 7.5 nm. In one or more embodiments, the second thickness, t 2, equal to the first thickness, t 1 indicates that the underlying nanosheet channel layer 224 was not consumed during RPO oxidation. In one or more embodiments, the second thickness, t 2, which is essentially equal to the first thickness, t 1 indicates that the underlying nanosheet channel layer 224 was not consumed during RPO oxidation. As used herein, the term "substantially equal" means that the second thickness is within ±0.5 nm, ±0.4 nm, ±0.3 nm, ±0.2 nm, or ±0.1 nm of the first thickness. In one or more embodiments, the sacrificial epitaxial layer 250 protects the nanosheet channel layer 224 from oxidation, thereby allowing the spacing between the nanosheet channel layers 224 to be adjusted while maintaining device performance. In other embodiments, the first thickness, t 1, greater than the second thickness t 2 indicates that a portion of the underlying nanosheet channel layer 224 was consumed during RPO oxidation. In one or more embodiments, approximately 0.5 nm to approximately 1.5 nm of the underlying nanosheet channel layer 224 was consumed during RPO oxidation. In addition to oxidizing the sacrificial epitaxial layer 250, in operation 114, the spacer 210 is partially oxidized, thereby reducing the dielectric constant, k-value, of the spacer 210. In some embodiments, operations 112 and 114 occur simultaneously in a single operation 113. In one or more embodiments, operation 116 of method 100 represents one or more post-oxidation processing operations. The one or more post-oxidation processing operations can be any process known to those skilled in the art for fabricating hGAA devices. Referring to Figures 6A and 6B, a high-k dielectric layer 254 is formed on the oxide layer 260. The high-k dielectric layer 254 can be any suitable high-k dielectric material deposited using any suitable deposition technique known to those skilled in the art. In some embodiments, the high-k dielectric layer 254 comprises hafnium oxide. In some embodiments, a conductive material 256, such as titanium nitride (TiN), tungsten (W), cobalt (Co), or aluminum (Al), is deposited on the high-k dielectric layer 254. Any suitable deposition process (e.g., but not limited to atomic layer deposition (ALD)) can be used to form the conductive material 256 to ensure a layer of uniform thickness is formed around the respective nanosheet channel layers 224. In some embodiments, gate electrodes 242 are formed on substrate 200 and surrounding respective nanosheet channel layers 224. Gate electrodes 242 can be formed from any suitable gate electrode material known in the art to which this application pertains. The gate electrode material is deposited using any suitable deposition process, such as atomic layer deposition (ALD), to ensure that gate electrodes 242 are formed around and between the respective nanosheet channel layers 224. In one or more embodiments, gate electrodes are deposited by CVD because the space available for gate electrode placement between nanosheets is limited. According to embodiments of this disclosure, the resulting element formed using the methods described herein is a horizontally surrounding gate element. Some embodiments of this disclosure relate to horizontally surrounding gate elements comprising a channel layer (i.e., nanosheet channel layer 224) made of nanosheets in a channel between a source region and a drain region. One or more embodiments of this disclosure relate to a method of forming a semiconductor device. In one or more embodiments, the method of forming a semiconductor device includes the following steps: selectively etching a superlattice structure comprising a plurality of semiconductor material layers and corresponding plurality of nanosheet channel layers arranged in a plurality of stacked pairs to remove each of the plurality of semiconductor material layers to form a plurality of pores in the superlattice structure, wherein the plurality of semiconductor material layers extend between source and drain regions; growing a conformal sacrificial epitaxial layer on the plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a first thickness; annealing the plurality of nanosheet channel layers having the conformal sacrificial epitaxial layer thereon; and oxidizing the conformal sacrificial epitaxial layer using plasma to form an oxide layer (e.g., silicon oxide) on each of the plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a second thickness. One or more embodiments relate to horizontally surrounding gate devices. The final GAA device of one or more embodiments always has discrete channels separated from each other from the source to the drain. In one or more embodiments, the gate material completely surrounds the discrete channels from each side. This differs from conventional GAA devices, where a finFET in a conventional GAA device is covered on only three sides. In one or more embodiments, the hGAA device includes a plurality of horizontal nanosheet channel layers located between the source and drain regions, the plurality of horizontal nanosheet channel layers having a top surface, a bottom surface, and two side surfaces; and oxide layers located on the top surface, bottom surface, and two side surfaces of the plurality of horizontal nanosheet channel layers. In one or more embodiments, the oxide layer has a thickness ranging from about 4 nm to about 8 nm, which is equal to the thickness of the epitaxial layer to which it is formed. In other embodiments, the oxide layer has a thickness ranging from about 2.5 nm to 7.5 nm. In some embodiments, the oxide layer comprises silicon oxide. In some embodiments, the plurality of horizontal channel layers comprise silicon (Si). In some embodiments, no plurality of horizontal channel layers are consumed during oxidation to form an oxide layer. Therefore, in one or more embodiments, each of the plurality of horizontal channel layers has a thickness substantially equal to the thickness of each of the plurality of horizontal channel layers prior to the formation of the oxide layer. As used herein, the term "substantially equal" means that the thickness of each of the horizontal channel layers in the final element is within ±0.5 nm, ±0.4 nm, ±0.3 nm, ±0.2 nm, or ±0.1 nm of the thickness of each of the horizontal channel layers prior to the oxidation of the element. Additional embodiments of this disclosure relate to a clustering tool 300, as shown in Figure 7, for forming GAA elements and for use in the methods described herein. Various multiprocessing platforms can be used, including Centura from Applied Materials®. ® Dual ACP, Producer ® GT and Endura ® The platform also includes other processing systems. The cluster tool 300 includes at least one central transfer station 314 having a plurality of sides. A robot 316 is housed within the central transfer station 314 and configured to move robot blades and wafers to each of the plurality of sides. The cluster tool 300 includes a plurality of process chambers 308, 310, and 312, also referred to as processing stations, connected to a central transfer station. Each process chamber provides an independent processing area isolated from adjacent processing stations. Process chambers can be any suitable chamber, including but not limited to: pre-cleaning chambers, deposition chambers, annealing chambers, etching chambers, selective etching chambers, etc. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be considered as limiting the scope of this disclosure. In some embodiments, the clustering tool 300 includes an epitaxial growth chamber and a radical plasma oxidation chamber. The epitaxial growth chamber is used to grow a conformal epitaxial layer 250, while the radical plasma oxidation chamber is used for radical plasma oxidation (RPO) of the conformal epitaxial layer 250 to form an oxide layer 260. In some embodiments, the clustering tool 300 includes a pre-cleaning chamber connected to a central transfer station. In other embodiments, the clustering tool 300 includes an annealing chamber connected to a central transfer station. In yet another embodiment, the clustering tool 300 includes both a pre-cleaning chamber and an annealing chamber connected to a central transfer station. In the embodiment shown in Figure 7, the factory interface 318 is connected to the front side of the cluster tool 300. The factory interface 318 includes a chamber 302 for loading and unloading on the front side 319 of the factory interface 318. The size and shape of the loading chamber and unloading chamber 302 can be varied, for example, depending on the substrate to be processed in the cluster tool 300. In the illustrated embodiment, the dimensions of the loading chamber and unloading chamber 302 are set to hold a wafer cassette in which a plurality of wafers are disposed. Robot 304 is located within the factory interface 318 and can move between the loading and unloading chambers 302. Robot 304 can transfer wafers from a cassette in the loading chamber 302 to a loading gate chamber 320 via the factory interface 318. Robot 304 can also transfer wafers from the loading gate chamber 320 to a cassette in the unloading chamber 302 via the factory interface 318. In some embodiments, robot 316 is a multi-armed robot capable of moving more than one wafer at a time independently. Robot 316 is configured to move wafers between chambers surrounding transfer chamber 314. Each wafer is mounted on a wafer transport blade located at the distal end of the first robotic mechanism. System controller 357 communicates with robot 316 and multiple process chambers 308, 310, and 312. System controller 357 can be any suitable component that controls the process chambers and robot. For example, system controller 357 can be a computer including central processing unit (CPU) 392, memory 394, input / output 396, suitable circuitry 398, and storage. Typically, the process can be stored as a software routine in the memory of the system controller 357. When executed by the processor, the software routine causes the process chamber to perform the process described herein. The software routine can also be stored and / or executed by a second processor (not shown) located remotely at the end of the processor-controlled hardware. Some or all of the methods described herein can also be executed in the hardware. Thus, the process can be implemented as software and executed using a computer system, implemented as hardware (e.g., dedicated integrated circuits or other types of hardware implementations), or implemented as a combination of software and hardware. When executed by the processor, the software routine transforms a general-purpose computer into a dedicated computer (controller) that controls the operation of the process chamber to perform the processing. In some embodiments, the system controller 357 is configured to control the epitaxial growth chamber to grow a conformal sacrificial epitaxial layer 250 on the nanosheet channel layer 224. In one or more embodiments, a processing tool includes: a central transfer station including a robot configured to move a wafer; a plurality of processing stations connected to the central transfer station and providing processing areas separated from processing areas of adjacent processing stations, the plurality of processing stations including: an epitaxial growth chamber and a radical plasma oxidation (RPO) chamber; and a controller connected to the central transfer station and the plurality of processing stations, the controller being configured to initiate the robot to move the wafer between the processing stations and to control the processes occurring in each processing station. Unless otherwise stated herein or clearly contradicted by the context, the terms "a," "an," "the," and similar designations used in the context of describing the materials and methods discussed herein (especially in the context of the following claims) shall be construed as covering both singular and plural. Unless otherwise stated herein, descriptions of numerical ranges herein are intended only as a simplified way of referring to each individual numerical value falling within that range, and each individual numerical value is incorporated into the specification as if it were described separately herein. Unless otherwise stated herein or clearly contradicted by the context, all methods described herein may be performed in any suitable order. Unless otherwise claimed, the use of any and all illustrative or exemplary language (e.g., "such as") provided herein is intended only to better illustrate certain materials and methods and does not constitute a limitation on the scope. No language in the specification should be construed as indicating that any unclaimed element is essential for implementing the disclosed materials and methods. Throughout this specification, references to "one embodiment," "some embodiments," "multiple embodiments," "one or more embodiments," or "one embodiment" mean that the specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, the use of terms such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in one embodiment" throughout this specification does not necessarily refer to the same embodiment of this disclosure. Furthermore, in one or more embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner. Although the disclosure herein has been described with reference to specific embodiments, those skilled in the art will understand that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of the disclosure. Therefore, this disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents. 100A, 100B: Methods 102~116: Operation 200: Substrate 202: Top Surface 204: Superlattice Structure 208: Gate-like Structure 210: Spacer 214: Channel Region 220: Interlayer Dielectric (ILD) Layer 224: Nanosheet Channel Layer 226: Semiconductor Material Layer 228: Pores 232 / 234: Source Region / Drain Region 240: Channel Nanowire 242: Gate Electrode 245a, 245b: Enlarged Cross-sectional View of Substrate 246: Dielectric Material 250: (Conformal) Sacrificial Epitaxial layer 254: High-k dielectric layer 255: Oxide layer 256: Conductive material 260: Oxide layer 300: Cluster tool 302: Loading / unloading chamber 304: Robot 308: Process chamber 310: Process chamber 312: Process chamber 314: Central transfer station 316: Robot 318: Factory interface 319: Front side 320: Loading gate chamber 355: Gas operating system 357: System controller 392: Central processing unit 394: Memory 396: Input / output 398: Circuit 1: First thickness t 2: Second thickness t n :thickness Therefore, the above-described features of this disclosure can be understood in detail by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of this disclosure and should not be considered as limiting its scope, as other equivalent embodiments are permissible. Figure 1A is a process flow diagram of a method for forming a semiconductor device according to some embodiments of the present disclosure; Figure 1B is a process flow diagram of a method for forming a semiconductor device according to some embodiments of the present disclosure; Figure 2A shows a cross-sectional view of an element according to one or more embodiments; Figure 2B shows a cross-sectional view of an element according to one or more embodiments; Figure 2C shows a cross-sectional view of an element according to one or more embodiments; The 2D drawing is an enlarged cross-sectional view of an element according to one or more embodiments; Figure 2E shows an enlarged cross-sectional view of an element according to one or more embodiments; Figure 3A shows an enlarged cross-sectional view of an element according to one or more embodiments; Figure 3B is an enlarged cross-sectional view of an element according to one or more embodiments; Figure 4A shows an enlarged cross-sectional view of an element based on the prior art; Figure 4B shows an enlarged cross-sectional view of an element based on the prior art; Figure 5A shows an enlarged cross-sectional view of an element according to one or more embodiments; Figure 5B shows an enlarged cross-sectional view of an element according to one or more embodiments; Figure 6A shows a cross-sectional view of an element according to one or more embodiments; Figure 6B is an enlarged cross-sectional view of the elements in Figure 6A according to one or more embodiments; and Figure 7 illustrates a clustering tool according to one or more embodiments. For ease of understanding, the same component symbols are used as much as possible to represent common components in the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without further description. Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None. 204: Superlattice structure 224: Nanosheet Channel Layer 228: Porosity 232 / 234: Source Region / Drain Region 245a: Enlarged cross-sectional view of the substrate 260: Oxide layer t 2: Second thickness

Claims

1. A processing tool comprising: at least one central transfer station including a robot configured to move a wafer; a plurality of processing chambers connected to the at least one central transfer station and providing a processing area separated from processing areas of adjacent processing chambers, the plurality of processing chambers including an epitaxial growth chamber, a pre-cleaning chamber, an annealing chamber and a radical plasma oxidation (RPO) chamber; and a controller configured to initiate the robot to move the wafer between the processing chambers and cause the processing tool to perform the following operation: selectively etching one of a superlattice structures comprising a plurality of nanosheet channel layers and corresponding plurality of semiconductor material layers arranged in a plurality of stacked pairs to remove each of the plurality of semiconductor material layers to form a plurality of pores in the superlattice structure; A conformal sacrificial epitaxial silicon layer is formed on each of the plurality of nanosheet channel layers through the plurality of pores; and the conformal sacrificial epitaxial silicon layer is oxidized by free radical plasma oxidation to form a silicon oxide layer on each of the plurality of nanosheet channel layers.

2. The processing tool as claimed in claim 1, wherein the controller is configured to cause the processing tool to perform the following operation: pre-cleaning a plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a first thickness.

3. The processing tool as claimed in claim 1, wherein the controller is configured to cause the processing tool to perform the following operation: pre-clean the plurality of nanosheet channel layers on which the conformal sacrificial epitaxial silicon layer is disposed, in order to remove native oxides and / or residues.

4. The processing tool as claimed in claim 1, wherein the plurality of semiconductor material layers extend between a source region and a drain region.

5. The processing tool as claimed in claim 5, wherein the controller is configured to cause the processing tool to further perform the following operations: forming the source region and the drain region, the source region being adjacent to a first end of the superlattice structure and the drain region being adjacent to a second opposite end of the superlattice structure.

6. The processing tool as claimed in claim 2, wherein after radical plasma oxidation, each of the plurality of nanosheet channel layers has a second thickness, wherein the first thickness and the second thickness are substantially equal.

7. The processing tool as claimed in claim 6, wherein the conformal sacrificial epitaxial silicon layer has a thickness ranging from about 0.5 nm to about 2.5 nm.

8. The processing tool as described in claim 6, wherein the first thickness is in the range of about 4 nm to about 8 nm.

9. The processing tool as described in claim 6, wherein the second thickness is in the range of about 4 nm to about 8 nm.

10. The processing tool as described in claim 6, wherein the second thickness is in the range of about 2.5 nm to about 7.5 nm.

11. The processing tool as claimed in claim 6, wherein forming the conformal sacrificial epitaxial silicon layer comprises: epitaxially growing the conformal sacrificial epitaxial silicon layer at a temperature ranging from 500 °C to 800 °C.

12. The processing tool as described in claim 6, wherein the operations are performed in the processing tool without breaking the vacuum.

13. The processing tool as claimed in claim 6, wherein oxidizing the conformal sacrificial epitaxial silicon layer comprises: radical plasma oxidation (RPO) of the conformal sacrificial epitaxial silicon layer at a temperature ranging from about 500 °C to about 900 °C, in an atmosphere of hydrogen (H2) and oxygen (O2), and at ambient pressure.

14. A processing tool comprising: at least one central transfer station including a robot configured to move a wafer; a plurality of processing chambers connected to the at least one central transfer station and providing a processing area separated from processing areas of adjacent processing chambers, the plurality of processing chambers including an epitaxial growth chamber, a pre-cleaning chamber, an annealing chamber, and a radical plasma oxidation (RPO) chamber; and a controller configured to cause the processing tool to perform the following operations: pre-cleaning a plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a first thickness; and forming a conformal sacrificial epitaxial silicon layer on each of the plurality of nanosheet channel layers; The plurality of nanosheet channel layers on which the conformal sacrificial epitaxial silicon layer is disposed are pre-cleaned to remove native oxides and / or residues; and the conformal sacrificial epitaxial silicon layer is oxidized using plasma to form a silicon oxide layer on each of the plurality of nanosheet channel layers, each of the plurality of nanosheet channel layers having a second thickness, wherein the first thickness and the second thickness are substantially equal.

15. The processing tool as claimed in claim 14, wherein the conformal sacrificial epitaxial silicon layer has a thickness ranging from about 0.5 nm to about 2.5 nm.

16. The processing tool as described in claim 14, wherein the first thickness is in the range of about 4 nm to about 8 nm.

17. The processing tool as described in claim 14, wherein the second thickness is in the range of about 4 nm to about 8 nm.

18. The processing tool as described in claim 14, wherein the second thickness is in the range of about 2.5 nm to about 7.5 nm.

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