Memory device and method for manufacturing the same

Abstract

A memory device and a method for manufacturing the same are provided. The memory device includes a substrate, a first stacked structure, a second stacked structure, at least one transistor, and a metal winding layer. The substrate includes an array region and a peripheral region. The first stacked structure is located in the array region. The first stacked structure includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer. The first conductive layer, the insulating layer, and the second conductive layer are stacked along a first direction. The second stacked structure is located in the peripheral region. At least one transistor is located in the second stacked structure. The at least one transistor has a conductive film, a dielectric film, and a semiconductor film stacked along the first direction. The metal winding layer is located above the first stacked structure and the second stacked structure. The metal winding layer is electrically connected to the at least one transistor, the first conductive layer, and the second conductive layer.

Claims

1. A memory device, comprising: a substrate including an array region and a peripheral region; a first stacked structure located in the array region, the first stacked structure including a first conductive layer, a second conductive layer and an insulating layer disposed between the first conductive layer and the second conductive layer, the first conductive layer, the insulating layer and the second conductive layer being stacked along a first direction; and a second stacked structure located in the peripheral region, the second stacked structure including a deflection portion adjacent to one end of the first conductive layer, the deflection portion including a plurality of semiconductor layers stacked extending along the first direction and in a direction perpendicular to the first direction; At least one transistor is located in the second stacked structure, the at least one transistor having a conductive film, a dielectric film and a semiconductor film stacked along the first direction; And a metal winding layer, located above the first stacked structure and the second stacked structure, wherein the metal winding layer is electrically connected to the at least one transistor, the first conductive layer and the second conductive layer.

2. The memory device as claimed in claim 1 further includes at least one channel post and a plurality of memory cells, the at least one channel post extending along a second direction opposite to the first direction and penetrating the first stacked structure, the first conductive layer being closer to the substrate than the second conductive layer, and the plurality of memory cells being located between the second conductive layer and the at least one channel post.

3. The memory device as claimed in claim 2 further includes a source contact structure and a drain contact structure, wherein the at least one transistor has a source, a drain, and a gate, the gate being formed by the conductive film, the dielectric film, and the semiconductor film, the source and the drain being located in the substrate, the source contact structure and the drain contact structure extending along the second direction to the surface of the substrate, and the height of the source contact structure from the substrate and the height of the drain contact structure from the substrate being greater than the height of the at least one channel post from the substrate.

4. The memory device as claimed in claim 2 further includes a conductive post that penetrates the first stack structure and extends along the second direction to the surface of the substrate, the conductive post being electrically connected to the substrate.

5. The memory device as claimed in claim 4 further includes a source contact structure and a drain contact structure, wherein the at least one transistor has a source, a drain and a gate, the gate being formed by the conductive film, the dielectric film and the semiconductor film, the source and the drain being located in the substrate, and the height of the source contact structure from the substrate and the height of the drain contact structure from the substrate are greater than the height of the conductive post from the substrate.

6. The memory device as claimed in claim 1 further includes a first conductive contact structure and a second conductive contact structure, the first conductive contact structure being above the first conductive layer and electrically connected to the first conductive layer, the second conductive contact structure being above the second conductive layer and electrically connected to the second conductive layer, and the first conductive contact structure and the second conductive contact structure being electrically connected to the metal winding layer.

7. The memory device as claimed in claim 1, further comprising at least one first spacer element in the second stacked structure, wherein the at least one first spacer element is located on the sidewalls of the conductive film and the semiconductor film of the at least one transistor.

8. The memory device as claimed in claim 7, further comprising a second spacer element in the second stacked structure, wherein the second spacer element is located at one end of the diffracted portion away from the first conductive layer.

9. A method for manufacturing a memory device, comprising: providing a substrate including an array region and a peripheral region; forming a layer stack in the array region, the layer stack including a semiconductor material layer, a dielectric layer, and an insulating layer between the semiconductor material layer and the dielectric layer; forming a channel pillar through the layer stack; forming a diffraction adjacent to the layer stack, wherein the diffraction includes a plurality of semiconductor layers stacked and extending along a first direction and a second direction, the first direction being perpendicular to the second direction; and forming at least one transistor in the peripheral region, the at least one transistor including a stacked conductive film, a dielectric film, and a semiconductor film.

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