Semiconductor device and methods of formation

Abstract

A transistor structure can be formed in the interconnect layer of a semiconductor device in a process including ultraviolet (UV) curing and ozone (O₃) treatment of a gate dielectric layer. UV curing and ozone treatment remove or reduce impurities formed in the gate dielectric layer. The UV curing operation disrupts hydrogen bonds in the gate dielectric layer. The ozone treatment process repairs the disrupted bonds to enhance the metal-oxide bonds of the high-dielectric-constant material in the gate dielectric layer. This enhancement of the metal-oxide bonds in the gate dielectric layer prevents oxygen in the gate dielectric layer from reacting with metals in adjacent gate electrodes and oxide semiconductor channels. Therefore, this transistor structure can exhibit a higher breakdown voltage and enhanced performance compared to transistor structures fabricated without UV curing and ozone treatment.

Claims

1. A method for forming a semiconductor device, comprising: Deposit gate electrodes on the dielectric layer of the interconnect layer; A high-k gate dielectric layer is deposited on the gate electrode; Perform ultraviolet (UV) light treatment on the high dielectric constant gate dielectric layer; perform ozone (O3) treatment on the high dielectric constant gate dielectric layer; deposit an oxide semiconductor channel layer on the high dielectric constant gate dielectric layer; deposit a capping layer on the oxide semiconductor channel layer; and deposit a plurality of source / drain electrodes through portions of the capping layer to portions of the oxide semiconductor channel layer.

2. The method as described in claim 1, wherein the ultraviolet light treatment operation and the ozone treatment operation are performed simultaneously.

3. The method as described in claim 1, wherein the ozone treatment operation is performed after the ultraviolet light treatment operation.

4. The method of claim 1, wherein performing the ultraviolet light processing operation includes exposing the high dielectric constant gate dielectric layer to ultraviolet light having wavelengths ranging from about 100 nanometers to about 440 nanometers.

5. The method of claim 1, wherein the time for performing the ultraviolet light processing operation is in the range of about 30 seconds to about 300 seconds.

6. The method of claim 1, wherein performing the ozone treatment operation comprises flowing a mixture of ozone (O3) and oxygen (O2) over the high dielectric constant gate dielectric layer, and wherein the concentration of ozone in the mixture is in the range of about 10% to about 25%.

7. A method for forming a semiconductor device, comprising: A gate dielectric layer of the transistor structure is deposited on the gate electrode of the transistor structure, wherein the transistor structure is formed in the interconnect layer of the semiconductor device; The gate dielectric layer is exposed to ultraviolet light (UV) and ozone (O3); an oxide semiconductor channel layer is deposited on the gate dielectric layer; a capping layer is deposited on the oxide semiconductor channel layer; a first source / drain electrode is deposited to penetrate a first portion of the capping layer onto a first portion of the oxide semiconductor channel layer; And deposit a second source / drain electrode to pass through the second portion of the capping layer onto the second portion of the oxide semiconductor channel layer.

8. The method as described in claim 7, wherein the oxide semiconductor channel layer and the gate dielectric layer are in direct contact.

9. The method of claim 7, wherein the gate electrode and the gate dielectric layer are in direct contact.

10. A semiconductor device, comprising: Gate electrode; Oxide semiconductor channel layer; A high-k gate dielectric layer is located between the gate electrode and the oxide semiconductor channel layer, wherein the high-k gate dielectric layer directly contacts at least one of the gate electrode or the oxide semiconductor channel layer; a capping layer is located on the oxide semiconductor channel layer; a first source / drain electrode extends through a first portion of the capping layer to a first portion of the oxide semiconductor channel layer; And the second source / drain electrode passes through the second portion of the capping layer to the second portion of the oxide semiconductor channel layer.

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