Semiconductor structure and method for forming the same

Abstract

A semiconductor structure is provided, comprising: a substrate, an epitaxial layer disposed on the substrate, and at least one structural unit. Each structural unit includes: a central contact disposed in the epitaxial layer, a pair of electrode structures disposed on both sides of the central contact, a pair of side well regions disposed outside the pair of electrode structures, a pair of side-doped regions disposed in the pair of side well regions, a bottom well region disposed under the pair of electrode structures, and a bottom-doped region disposed in the bottom well region. The bottom-doped region includes: a pair of first bottom-doped regions disposed under the pair of electrode structures, and a second bottom-doped region disposed under the central contact.

Claims

1. A semiconductor structure, comprising: One substrate; An epitaxial layer is disposed on the substrate, wherein the epitaxial layer has a first conductivity type; At least one structural unit, wherein each structural unit includes: a central contact disposed in the epitaxial layer; a pair of electrode structures disposed on both sides of the central contact; a pair of side well regions disposed outside the pair of electrode structures and having a second conductivity type different from the first conductivity type; a pair of side-doped regions disposed in the pair of side well regions; a bottom well region disposed under the pair of electrode structures and having the second conductivity type; and a bottom-doped region disposed in the bottom well region, wherein the bottom-doped region includes: a pair of first bottom-doped regions respectively disposed under the pair of electrode structures; and a second bottom-doped region disposed under the central contact, wherein the pair of first bottom-doped regions and the second bottom-doped region have different conductivity types.

2. The semiconductor structure as claimed in claim 1, wherein the central contact has an upper portion and a lower portion, wherein the width of the upper portion is greater than the width of the lower portion.

3. The semiconductor structure as claimed in claim 2, wherein the pair of first underdoped regions are both disposed below the upper portion of the central contact and on both sides of the lower portion of the central contact.

4. The semiconductor structure as described in claim 2, further comprising: A pair of sidewall dielectric layers are disposed on both sides of the lower portion of the central contact, wherein the lower portion of the central contact is separated from the bottom well area by the pair of sidewall dielectric layers.

5. The semiconductor structure as described in claim 1, wherein the pair of side well regions and the bottom well region are spaced apart from each other.

6. The semiconductor structure as claimed in claim 1, wherein the bottom surface of the electrode pair structure is lower than the bottom surface of the side well region.

7. The semiconductor structure as claimed in claim 1, wherein the outermost side surface of the electrode pair structure protrudes beyond the side surface of the bottom well region.

8. The semiconductor structure as claimed in claim 1, wherein the pair of first bottom-doped regions covers a portion of the bottom surface of the electrode pair structure.

9. The semiconductor structure as claimed in claim 1, wherein the second bottom doped region completely covers the bottom surface of the central contact.

10. The semiconductor structure as claimed in claim 1, wherein each side of the doped region of the opposite side includes: a first side doped region and a second side doped region, wherein the first side doped region is closer to the counter electrode structure than the second side doped region.

11. The semiconductor structure as claimed in claim 1, further comprising a barrier layer disposed between either the central contact or the counter electrode structure.

12. The semiconductor structure as claimed in claim 11, wherein the pair of first bottom-doped regions are spaced apart from the central contact by the barrier layer.

13. The semiconductor structure as described in claim 1 further includes a pair of side contacts, respectively disposed on the opposite side doped regions.

14. The semiconductor structure as claimed in claim 13, wherein the bottom surface of the central contact is lower than the bottom surface of the opposite contact.

15. The semiconductor structure as described in claim 1 further includes a top electrode disposed on the central contact.

16. The semiconductor structure as claimed in claim 1, wherein the structural unit is symmetrical about the central contact.

17. A method for forming a semiconductor structure, comprising: Provide a substrate; An epitaxial layer is formed on the substrate, wherein the epitaxial layer has a first conductivity type; Forming at least one structural unit, wherein forming each structural unit includes: forming a trench in the epitaxial layer; forming a pair of side well regions and a bottom well region around the trench, wherein the pair of side well regions and the bottom well region have a second conductivity type different from the first conductivity type; forming a pair of side-doped regions in the pair of side well regions; forming a bottom-doped region in the bottom well region, wherein forming the bottom-doped region includes: forming a first bottom-doped predetermined region at a predetermined location in the bottom well region; extending the trench into the bottom well region and truncating the first bottom-doped predetermined region to form a pair of first bottom-doped regions; and forming a second bottom-doped region at the bottom of the trench; forming a pair of electrode structures in the trench; and forming a central contact between the pair of electrode structures.

18. A method for forming a semiconductor structure as described in claim 17, wherein forming the electrode pair structure comprises: A dielectric layer is formed along the trench and with the surface conformability of the epitaxial layer; A gate electrode material is formed on the dielectric layer; A portion of the gate electrode material and a portion of the dielectric layer are removed to expose a portion of the bottom-doped region; the remaining gate electrode material is oxidized to form a pair of electrode structures comprising a pair of gate electrodes and a pair of gate dielectric layers covering the pair of gate electrodes.

19. A method for forming a semiconductor structure as described in claim 18, wherein after forming the gate electrode material, the method further comprises: A predetermined inter-dielectric layer is formed on the gate electrode material; a portion of the predetermined inter-dielectric layer is removed. And pattern the predetermined interlayer dielectric layer to form an interlayer dielectric layer.

20. A method for forming a semiconductor structure as described in claim 17, further comprising, before forming the electrode pair structure: The epitaxial layer is annealed at 1500˚C~1800˚C.

21. The method of forming a semiconductor structure as described in claim 17, further comprising, before forming the central contact: A barrier layer is formed on the epitaxial layer by compliance.

22. The method for forming a semiconductor structure as described in claim 21 further includes: A rapid thermal annealing process is performed on the barrier layer to form a metal semiconductor layer at the interface between the barrier layer and the epitaxial layer.

23. The method for forming a semiconductor structure as described in claim 17 further includes: A pair of side contacts are formed on the opposite side doped regions.

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