Panel structure, pixel structure, and method for repairing pixel structure

Abstract

A pixel structure includes a substrate, multiple vertical diode (VDI) chips, flip-chip (FPS) chips, and an upper wiring layer. The substrate has a lower wiring layer comprising multiple first and second wirings, the first wirings being of a first polarity and the second wirings being of a second polarity. Multiple VDI chips are disposed on the substrate and coupled to the first wirings. FPS chips are disposed on the substrate and coupled to one of their first and second wirings. The upper wiring layer is disposed on the multiple VDI chips and FPS chips, and includes multiple third wirings, each coupled to a VDI chip, the third wirings being of a second polarity.

Description

[Technical Field]

[0001] This case relates to a substrate structure for a micro light-emitting diode, and more particularly to a substrate structure that includes multiple types of micro light-emitting diodes. [Previous Technology]

[0002] Micro-LEDs are widely used in the lighting and display industries. Based on their layered structure, they can be mainly divided into flip-chip micro-LEDs and vertical micro-LEDs. In flip-chip micro-LEDs, the positive electrode (P-electrode) and negative electrode (N-electrode) are located on the same side of the chip and on the same horizontal plane; while in vertical micro-LEDs, the positive and negative electrodes are located on the top and bottom sides of the chip, respectively, and arranged vertically. Because the positive and negative electrodes of flip-chip micro-LEDs are located on the same side, they are prone to current congestion. In contrast, vertical micro-LEDs have a more uniform electrode distribution, effectively improving current distribution and thus increasing luminous efficiency. Furthermore, vertical micro-LEDs have excellent heat dissipation performance, making them ideal for high-precision or small-size displays.

[0003] As display technology moves towards higher resolution and higher pixels per inch (PPI), the pixel size of light-emitting diode (LED) displays will become smaller and smaller, and the chip size also needs to be reduced accordingly. Vertical LEDs, with their excellent heat dissipation performance and high luminous efficiency, hold a key position in the display industry.

[0004] However, existing technologies still face many challenges in the mass transfer and grain repair of vertical micro-light-emitting diodes, which is the main reason why vertical micro-light-emitting diodes have not yet dominated the market.

[0005] On the other hand, with the advancement of technology, micro-LED display devices are expected to gradually replace traditional liquid crystal displays and become the mainstream in the market. Existing micro-LEDs include two types: solid color micro-LEDs and color-conversion micro-LEDs. Solid color micro-LED systems can directly emit light of the corresponding color, while color-conversion micro-LED systems can use inkjet materials to convert the color of the emitted light.

[0006] Compared to color-conversion micro-light-emitting diodes (LEDs), pure-color LEDs have advantages such as simple structure, wider color gamut, and higher reliability. However, the manufacturing process of pure-color LEDs requires multiple complex mass transfers, and their repair process is also quite complex. In contrast, although the manufacturing process of color-conversion LEDs only requires one mass transfer, and their repair process is relatively simple, color-conversion LEDs also have disadvantages such as complex structure, narrower color gamut, and lower reliability.

[0007] On the other hand, there are variations in the production equipment and manufacturing technology of micro-light-emitting diodes, resulting in specification differences between different types of micro-light-emitting diodes (such as tri-color light-emitting diodes for red, green, and blue light). For example, the height difference between various micro-light-emitting diodes may range from 2 μm to 10 μm.

[0008] Generally, the height differences in micro-light-emitting diodes (LEDs) mainly stem from process variations in the following structural layers: epitaxial layer, electrode layer, bonding layer, and encapsulation layer. Height differences between LEDs will adversely affect subsequent eutectic bonding processes, such as leading to poor bonding and reduced process yield. Furthermore, these height differences can negatively impact alignment accuracy during the manufacturing process and the optical performance of the final product.

[0009] Therefore, how to effectively solve the height difference between micro light-emitting diodes to improve process stability and yield is a major challenge for the development of the light-emitting diode industry.

[0010] On the other hand, due to the thickness difference between the red, green, and blue LED grains, the conventional LED manufacturing process uses a filling technique to fill the gaps between each LED with a filler material to fix multiple elements within the LED, thereby planarizing the filler material to overcome the problem caused by this thickness difference. Furthermore, different filler materials can be used for different elements within the LED to sequentially fix each element.

[0011] However, existing filling technologies still suffer from poor flatness of the filling material, which can cause open circuits between components and prevent the micro-LED from emitting light normally. In addition, when different filling materials are used to fix the components in the micro-LED, the interface between the filling materials may also lead to a decrease in the yield of the micro-LED manufacturing process and the reliability of the micro-LED itself.

[0012] On the other hand, the manufacturing process of micro-light-emitting diode (LED) display devices requires multiple mass transfers to move millions of LED units. However, existing mass transfer technologies cannot achieve precise positioning, and there is currently no suitable method to arrange scattered LED units neatly and evenly on the same surface. Therefore, existing mass transfer technologies cannot accurately and effectively move a large number of LED units, creating a bottleneck in the manufacturing process of micro-light-emitting diode display devices.

[0013] On the other hand, existing mass transfer technology uses a thin film made of polydimethylsiloxane (PDMS) (hereinafter referred to as PDMS film) to transfer micro-light-emitting diode units. However, there is currently no suitable method to keep multiple micro-light-emitting diode units neat and unskewed after they are detached from the PDMS film, which makes the manufacturing process of micro-light-emitting diode display devices encounter a bottleneck. [Summary of the Invention]

[0014] In view of this, the inventors propose a pixel structure comprising: a substrate, a plurality of vertical diode chips, a flip-chip diode chip, and an upper wiring layer. The substrate has a lower wiring layer comprising a plurality of first wirings and a second wiring, the first wirings belonging to a first polarity and the second wiring belonging to a second polarity. The plurality of vertical diode chips are disposed on the substrate and are respectively coupled to the first wirings. The flip-chip diode chip is disposed on the substrate and coupled to one of the first wirings and the second wiring. The upper wiring layer is disposed on the plurality of vertical diode chips and the flip-chip diode chip, the upper wiring layer comprising a plurality of third wirings respectively coupled to the vertical diode chips, the third wirings belonging to the second polarity.

[0015] In some embodiments, the pixel structure further includes a plurality of blocks and a light-transmitting filling layer. The plurality of blocks define a plurality of receiving sites. The plurality of vertical diodes and the flip-chip diodes are respectively located within the plurality of receiving sites. The light-transmitting filling layer covers the flip-chip diodes. The top surface of the light-transmitting filling layer is substantially coplanar with the top surfaces of the blocks.

[0016] In some embodiments, the plurality of vertical diode grains include at least one ineffective vertical diode grain and at least one effective vertical diode grain, wherein the color category of the light beam corresponding to the flip-chip diode grain is different from the color category of the light beam corresponding to the at least one effective vertical diode grain.

[0017] In some embodiments, the pixel structure further includes multiple first light conversion material layers, each covering the vertical diode grain.

[0018] In some embodiments, the pixel structure further includes a second light conversion material layer covering the flip-chip diode grain.

[0019] The inventors also propose a panel structure comprising: a substrate, a first pixel structure, a second pixel structure, and an upper wiring layer. The substrate has a lower wiring layer comprising multiple first wirings and multiple second wirings, the first wirings belonging to a first polarity and the second wirings belonging to a second polarity. The first pixel structure has multiple first receiving sites, the first pixel structure comprising multiple first vertical diode chips and a flip-chip diode chip. The multiple first vertical diode chips are disposed on the substrate and are respectively located within the first receiving sites, and are respectively coupled to the first wirings. The flip-chip diode chip is disposed on the substrate and is located within one of its first receiving sites, and is coupled to one of its first wirings and one of its second wirings. The second pixel structure has multiple second receiving sites, the second pixel structure comprising multiple second vertical diode chips and a filling layer. Multiple second vertical diode chips are disposed on the substrate and located within the second receiving sites, and are respectively coupled to the first traces. A fill layer is disposed on the substrate and located within one of the second receiving sites. An upper trace layer is disposed on the first pixel structure and the second pixel structure, and the upper trace layer includes multiple third traces, which are respectively coupled to the first vertical diode chips and the second vertical diode chips, and the third traces belong to the second polarity.

[0020] The inventors also propose a method for repairing a pixel structure, comprising: providing a substrate; forming a lower wiring layer on the substrate, the lower wiring layer including a first wiring and a second wiring, the first wiring belonging to a first polarity and the second wiring belonging to a second polarity; disposing a vertical diode die on the substrate and connecting it to the first wiring; and determining whether the vertical diode die is effective in order to decide whether to dispose of a flip-chip diode die on the substrate.

[0021] In some embodiments, the pixel structure repair method further includes setting the flip-chip diode on the substrate when it is determined that the vertical diode die is invalid.

[0022] In some embodiments, the pixel structure repair method further includes: when it is determined that the vertical diode chip is invalid, setting the flip-chip diode chip on the substrate, wherein the flip-chip diode chip is a short-wavelength light-emitting diode chip; and coating a light conversion material layer on the flip-chip diode chip.

[0023] In some embodiments, the pixel structure repair method further includes: forming a plurality of blocks on the substrate, the plurality of blocks defining a plurality of receiving sites; setting a plurality of vertical diodes on the substrate and respectively located within the receiving sites; and when it is determined that the vertical diodes are all effective, setting a filling layer within the remaining receiving sites, the remaining receiving sites not containing the vertical diodes.

[0024] In some embodiments, the pixel structure repair method further includes forming an upper wiring layer on the plurality of vertical diodes and the flip-chip diodes, the upper wiring layer including a third wiring coupled to the vertical diodes, the third wiring belonging to the second polarity.

[0025] The inventors also propose a hybrid micro-light-emitting diode structure, comprising: a substrate; a red micro-light-emitting diode crystal disposed on the substrate; a green micro-light-emitting diode crystal disposed on the substrate; a blue micro-light-emitting diode crystal disposed on the substrate; a spare micro-light-emitting diode crystal disposed on the substrate; and an isolation layer disposed on the substrate, the isolation layer surrounding the spare micro-light-emitting diode crystal and forming an inkjet space with the spare micro-light-emitting diode crystal, wherein the inkjet space... The space is used to fill an inkjet material; a filling layer is disposed on the substrate such that the red micro-light-emitting diode (LED) chip, the green LED chip, the blue LED chip, the spare LED chip, and the isolation layer are fixed on the substrate; and a light-transmitting layer is disposed on the filling layer; wherein any one of the red LED chip, the green LED chip, the blue LED chip, and the spare LED chip is adjacent to at least one of the other three.

[0026] In some embodiments, the spare micro-light-emitting diode grain is an ultraviolet micro-light-emitting diode grain, and the light-transmitting layer contains an anti-ultraviolet material.

[0027] In some embodiments, the spare micro-light-emitting diode grain is another blue micro-light-emitting diode grain.

[0028] In some embodiments, the spare micro-light-emitting diode grain is adjacent to the blue micro-light-emitting diode grain.

[0029] In some embodiments, the spare micro-light-emitting diode (LED) grain is more adjacent to the red LED grain or the green LED grain.

[0030] In some embodiments, the isolation layer includes an opaque material, wherein the opaque material surrounds the standby micro-light-emitting diode grain and the inkjet space.

[0031] In some embodiments, the isolation layer includes an opaque material and an isolation material, wherein the opaque material surrounds the inkjet space and the isolation material surrounds the standby micro-light-emitting diode grain.

[0032] In some embodiments, when one of the red micro-light-emitting diode (LED) grain, the green LED grain, and the blue LED grain is damaged, the inkjet space is filled with an inkjet material corresponding to the color of that grain.

[0033] The inventors also propose a method for repairing a hybrid micro-light-emitting diode structure, comprising: placing a red micro-light-emitting diode, a green micro-light-emitting diode, a blue micro-light-emitting diode, and a spare micro-light-emitting diode on a substrate; placing an isolation layer on the substrate to surround the spare micro-light-emitting diode, such that the isolation layer and the spare micro-light-emitting diode form an inkjet space; lighting up the red, green, and blue micro-light-emitting diodes respectively to check whether any one of them is damaged; and when one of the red, green, and blue micro-light-emitting diodes is damaged, performing the following steps: filling the inkjet space with an inkjet material corresponding to the color of the damaged red, green, and blue micro-light-emitting diode.

[0034] In some embodiments, the spare micro-light-emitting diode grain is selected from an ultraviolet micro-light-emitting diode grain or another blue micro-light-emitting diode grain.

[0035] In some embodiments, the method for repairing the hybrid micro-light-emitting diode structure further includes: when the red micro-light-emitting diode, the green micro-light-emitting diode, and the blue micro-light-emitting diode are not damaged, performing the following steps: filling a substrate with a filler material to form a filler layer, wherein the filler layer is disposed on the substrate to fix the red micro-light-emitting diode, the green micro-light-emitting diode, the blue micro-light-emitting diode, the spare micro-light-emitting diode, and the isolation layer on the substrate; and disposing a light-transmitting layer on the filler layer.

[0036] The inventors also propose a panel structure comprising: a first diode grain and a second diode grain. The first diode grain includes a first electrode having a first electrode thickness. The second diode grain includes a second electrode having a second electrode thickness, the first electrode thickness being greater than the second electrode thickness, and the grain heights of the first diode grain and the second diode grain are substantially the same.

[0037] In some embodiments, the panel structure further includes a plurality of pixel structures, each including the first diode grain and the second diode grain. The first electrode of the first electrode of the first diode grain of each pixel structure has substantially the same thickness, and the second electrode of the second electrode of the second diode grain of each pixel structure has substantially the same thickness.

[0038] In some embodiments, the first diode grain and the second diode grain are each a vertical diode grain, and the first electrode and the second electrode are each a bottom electrode of the vertical diode grain.

[0039] In some embodiments, the bottom electrode is a trapezoidal structure, and the thickness of the first electrode and the thickness of the second electrode are the height of the trapezoidal structure.

[0040] In some embodiments, the panel structure further includes a third diode grain and a third electrode, the third electrode having a third electrode thickness greater than the thickness of the second electrode and the thickness of the first electrode greater than the thickness of the third electrode, and the grain heights of the first diode grain, the second diode grain and the third diode grain are substantially the same.

[0041] The inventors also propose a method for manufacturing a diode grain, comprising: providing a substrate; forming an epitaxial layer on the substrate; forming a connecting layer on the epitaxial layer; disposing a bottom electrode layer on the connecting layer; grinding the bottom electrode layer; and forming a top electrode layer below the epitaxial layer to form a first diode grain.

[0042] In some embodiments, the method for manufacturing diode grains further includes: providing another substrate; forming another epitaxial layer on the other substrate; forming another interconnect layer on the other epitaxial layer; disposing another bottom electrode layer on the other interconnect layer; measuring a first height from the bottom of the substrate to the top of the bottom electrode layer; measuring a second height from the bottom of the other substrate to the top of the other bottom electrode layer; comparing the first height and the second height; and when it is determined that the first height is greater than the second height, grinding the bottom electrode layer until the first height decreases to the second height.

[0043] In some embodiments, the method for manufacturing diode grains further includes the step of not grinding the bottom electrode layer until the first height drops to the second height when it is determined that the second height is less than a lower limit height.

[0044] In some embodiments, the method of manufacturing a diode grain further includes: forming another top electrode layer under the other epitaxial layer to form a second diode grain; and transferring the first diode grain and the second diode grain to the same panel structure.

[0045] In some embodiments, there are multiple first diodes and multiple second diodes, and the panel structure includes multiple pixel structures, each pixel structure including one of the first diodes and one of the second diodes.

[0046] The inventors also propose a vertical micro-light-emitting diode unit, comprising: a first backplate and a second backplate. The first backplate includes a first substrate, a first circuit layer, a first contact pad, and a transparent electrode layer. The first circuit layer is disposed on the first substrate. The first contact pad is disposed on the first circuit layer. The transparent electrode layer is disposed on the first circuit layer and the first contact pad. The second backplate includes a second substrate, a second circuit layer, a eutectic metal layer, an alloy layer, a micro-light-emitting diode die, a second contact pad, and an isolation layer. The second circuit layer is disposed on the second substrate. The eutectic metal layer is disposed on the second circuit layer. The alloy layer is disposed on the eutectic metal layer. The micro-light-emitting diode die is disposed on the alloy layer. The second contact pad is disposed on the micro-light-emitting diode die. The isolation layer is disposed on the second substrate to surround the micro-light-emitting diode die. A first backplate is disposed on a second backplate to form a chamber. The projected areas of the first contact pad and the second contact pad along the normal direction of the first backplate at least partially overlap, and a transparent electrode layer connects the second contact pad and the insulating layer. When the first backplate is disposed on the second backplate, the insulating layer deforms such that the thickness of the deformed insulating layer is equal to the sum of the thickness of the first contact pad, the thickness of the second circuit layer, the thickness of the eutectic metal layer, the thickness of the alloy layer, the thickness of the micro-LED grain, and the thickness of the second contact pad.

[0047] In some embodiments, the chamber is in a vacuum state.

[0048] In some embodiments, the chamber is filled with an inert gas.

[0049] In some embodiments, the isolation layer includes an opaque material.

[0050] In some embodiments, the isolation layer includes an opaque material and a translucent material, wherein the opaque material surrounds the micro-light-emitting diode grain and the second contact pad, and the translucent material surrounds the second circuit layer, the eutectic metal layer and the alloy layer.

[0051] In some embodiments, the alloy layer is trapezoidal in shape, with the upper base of the trapezoid connected to the eutectic metal layer and the lower base of the trapezoid connected to the micro-light-emitting diode grain.

[0052] The inventors also propose a vertical micro-light-emitting diode structure, comprising: a first micro-light-emitting diode unit, a second micro-light-emitting diode unit, and a third micro-light-emitting diode unit. The first micro-light-emitting diode unit comprises the vertical micro-light-emitting diode unit described in any of the preceding embodiments, wherein the micro-light-emitting diode grain of the first micro-light-emitting diode unit is a red micro-light-emitting diode grain. The second micro-light-emitting diode unit comprises the vertical micro-light-emitting diode unit described in any of the preceding embodiments, wherein the micro-light-emitting diode grain of the second micro-light-emitting diode unit is a green micro-light-emitting diode grain. The third micro-light-emitting diode unit comprises the vertical micro-light-emitting diode unit described in any of the preceding embodiments, wherein the micro-light-emitting diode grain of the third micro-light-emitting diode unit is a blue micro-light-emitting diode grain. Any one of the first, second, and third micro-light-emitting diode units is adjacent to at least one of the other two.

[0053] In some embodiments, the thickness of the first contact pad of the second micro-light-emitting diode unit and the thickness of the first contact pad of the third micro-light-emitting diode unit are greater than the thickness of the first contact pad of the first micro-light-emitting diode unit.

[0054] The inventors also propose a method for manufacturing a vertical micro-light-emitting diode unit, comprising: forming a first backplate; forming a second backplate; and disposing the first backplate on the second backplate to form a cavity. The step of forming the first backplate comprises: disposing a first circuit layer on a first substrate; disposing a first contact pad on the first circuit layer; and disposing a transparent electrode layer on the first circuit layer and the first contact pad. The step of forming the second backplate comprises: disposing a second circuit layer on a second substrate; disposing a micro-light-emitting diode die on the second circuit layer; disposing a second contact pad on the micro-light-emitting diode die; and disposing an isolation layer on the second substrate to surround the micro-light-emitting diode die. The projected areas of the first contact pad and the second contact pad along the normal direction of the first backplate at least partially overlap, and the transparent electrode layer connects the second contact pad and the isolation layer.

[0055] The inventors also propose a method for manufacturing a vertical micro-light-emitting diode structure, comprising: forming a first backplate; forming a second backplate; and disposing the first backplate on the second backplate to form a plurality of chambers. The step of forming the first backplate comprises: disposing a plurality of first circuit layers on a first substrate; disposing a plurality of first contact pads on corresponding first circuit layers; and disposing a plurality of transparent electrode layers on corresponding first circuit layers and first contact pads. The step of forming the second backplate comprises: disposing a plurality of second circuit layers on a second substrate; disposing a red micro-light-emitting diode die, a green micro-light-emitting diode die, and a blue micro-light-emitting diode die on corresponding second circuit layers; disposing a plurality of second contact pads corresponding to the plurality of first contact pads on the red micro-light-emitting diode die, the green micro-light-emitting diode die, and the blue micro-light-emitting diode die, respectively; and disposing an isolation layer on the second substrate to surround the red micro-light-emitting diode die, the green micro-light-emitting diode die, and the blue micro-light-emitting diode die. The projected areas of each first contact pad and the corresponding second contact pad along the normal direction of the first back plate overlap at least partially, and each transparent electrode layer connects to the corresponding second contact pad and the isolation layer.

[0056] The inventors also propose a pre-alignment device suitable for multiple micro-LED units, comprising: a vibratory machine, an alignment disk, multiple electromagnets, and a controller. The vibratory machine includes multiple sidewalls and a base plate, with the sidewalls disposed around the base plate. The alignment disk is disposed on the base plate and includes multiple grooves arranged in an array. Each groove is used to accommodate each micro-LED unit, and the bottom of each groove includes a through hole. Each electromagnet is disposed in each through hole, and each electromagnet is used to generate a magnetic field along the extension direction of the through hole. The controller is electrically connected to the vibratory machine and the multiple electromagnets and is used to control the generation of the magnetic field by each electromagnet. The thickness of the alignment disk is less than the height of each sidewall.

[0057] In some embodiments, each of the grooves is trapezoidal in shape, and the width of the bottom of each groove is less than the width of the top surface of each groove.

[0058] In some embodiments, each of the grooves is rectangular in shape.

[0059] The inventors also propose a pre-arrangement method suitable for multiple micro-light-emitting diode units, comprising: placing multiple micro-light-emitting diode units on an array disk, wherein the array disk includes multiple grooves and each groove has a through hole at its bottom; generating an attractive force along the extension direction of the through hole; and generating a vibrational force to cause the array disk to vibrate, wherein each micro-light-emitting diode unit vibrates and moves into its respective groove; wherein, in response to the attractive force being greater than the vibrational force, each micro-light-emitting diode unit is fixed in its respective groove; and in response to the attractive force being less than the vibrational force, each micro-light-emitting diode unit detaches from its respective groove.

[0060] In some embodiments, the attraction force is a magnetic attraction force.

[0061] In some embodiments, each of the micro-light-emitting diode units includes a micro-light-emitting diode grain, a carrier layer and a magnetic conductive layer, wherein the carrier layer is disposed on the magnetic conductive layer and the micro-light-emitting diode grain is disposed on the carrier layer; wherein the height of each micro-light-emitting diode unit is greater than the depth of each groove.

[0062] In some embodiments, the shape of the bearing layer and the shape of the magnetic conductive layer are both trapezoidal, and the width of the bottom of the magnetic conductive layer is smaller than the width of the bottom of each groove.

[0063] In some embodiments, the material of the carrier layer is conductive and non-magnetic.

[0064] In some embodiments, the pre-alignment method further includes: stopping the generation of the vibration force in response to each of the micro-light-emitting diode units being fixed in each of the grooves; and stopping the generation of the attraction force.

[0065] In some embodiments, the attraction force is a vacuum suction force.

[0066] The inventors also propose an aligning device suitable for multiple micro-light-emitting diode units, comprising a support disk and an aligning disk. The support disk includes multiple grooves. Each groove extends along a first direction and the multiple grooves are spaced apart along a second direction, and the first direction is orthogonal to the second direction. The aligning disk is disposed on the support disk. The aligning disk includes multiple columns, and the multiple columns are spaced apart along the second direction and each column is aligned with each groove. Each column is provided with multiple recesses, the bottom of each recess includes a through hole, and the multiple recesses in each column are spaced apart along the first direction.

[0067] In some embodiments, the alignment device further includes: a vacuum machine coupled to the plurality of trenches; and a controller electrically connected to the vacuum machine for controlling the vacuum machine.

[0068] In some embodiments, the array of trays includes a conductive film, and the conductive film is disposed on the wall of each of the grooves.

[0069] In some embodiments, the alignment device further includes: a tilting mechanism disposed on the lower surface of the support plate and electrically connected to the controller; wherein the controller is further used to control the tilting mechanism.

[0070] In some embodiments, the alignment device further includes: a vibrator disposed on the lower surface of the support plate and electrically connected to the controller; wherein the controller is further used to control the vibrator.

[0071] The inventors also propose a method for arranging multiple micro-light-emitting diode units, comprising: moving multiple pre-arranged micro-light-emitting diode units disposed on a carrier plate to a vertical position above an arranging disk, wherein the arranging disk includes multiple grooves, each groove including a through hole at its bottom, and each micro-light-emitting diode unit being aligned with each groove; and generating an attractive force along the extension direction of the through hole to attract each micro-light-emitting diode unit from the carrier plate to the bottom of each groove.

[0072] In some embodiments, the attraction force is a vacuum suction force.

[0073] In some embodiments, the aligning method further includes: stopping the generation of the attractive force; placing a transparent cover plate above the aligning tray, wherein a conductive film is formed on the lower surface of the transparent cover plate, and a conductive film is also formed on the wall surface of each of the grooves of the aligning tray; and energizing the plurality of micro-light-emitting diode units through the conductive film of the transparent cover plate and the conductive film of the aligning tray.

[0074] In some embodiments, the aligning method further includes: removing the transparent cover plate; and removing the damaged plurality of micro-light-emitting diode units.

[0075] In some embodiments, the alignment method further includes: stopping the generation of the attractive force; and tilting the alignment disk so that each of the micro-light-emitting diode units aligns with one of the walls of the groove.

[0076] In some embodiments, the alignment method further includes: stopping the generation of the attractive force; and generating a vibrational force to cause the alignment disk to vibrate; wherein, in response to the vibration of the alignment disk, each of the micro-light-emitting diode units aligns with one of the walls of the respective groove.

Implementation Method

[0078] To make the objectives, means, and effects of the technical means disclosed in the different embodiments of this disclosure more easily understood, the following description, in conjunction with the accompanying drawings, provides a detailed explanation of specific embodiments of the proposed technical means. The descriptions of technical means in the following embodiments of this disclosure are for illustrative purposes only and do not represent all embodiments of this disclosure, nor do they limit this disclosure to specific embodiments. All other embodiments obtained by those skilled in the art based on the different embodiments of this disclosure without excessive experimentation should fall within the scope of protection intended by this disclosure. Unless otherwise defined, all technical and technical terms used in this disclosure have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. The terminology used in this disclosure is for the purpose of describing specific implementations only and is not intended to limit this disclosure.

[0079] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element and make physical or electrical contact with each other "directly"; or it can include elements existing between the two and make physical or electrical contact with each other "indirectly". When an element is referred to as being "connected", "coupled", "set on", or "electrically connected" to another element, it can be two or more elements making physical or electrical contact with each other "directly" or "indirectly".

[0080] In all descriptions relating to specific numerical values ​​in this disclosure, although not directly described, they all contain the meaning of "approximately" or "substantially," that is, these specific numerical values ​​will cover the possible range of numerical error, thereby representing the range of error implied by possible unintended effects and deviations in the process or material selection. The error range can include the range of changes that do not significantly alter the material, structure, configuration, properties, or effects, for example, a range of deviations of 0% to 10%, wherein the error range is clear to those skilled in the art. For example, describing "two objects are substantially parallel," but if in fact a slight height difference is observed between the two objects, but this difference is negligible relative to the size of the objects themselves (e.g., less than 10%) and does not affect the effect, then the observed relative configuration between the two objects will still be interpreted as being within the range of "substantially parallel" as described in this disclosure.

[0081] The terms "vertical," "horizontal," "left," "right," "up," "down," "inner," "outer," "front," "back," and similar expressions used in this disclosure are merely to indicate relative positional relationships based on diagrams and are not intended to limit the elements using these terms to implementation only in a representational manner. When the absolute position of the described object changes, the description of the relative position may also change accordingly.

[0082] The term "column" as used in this disclosure is not limited to multiple units arranged sequentially "from left to right" and "from right to left" in the drawings. Multiple units arranged sequentially "from top to bottom" and "from bottom to top" in the drawings can also be referred to as "columns". The "trapezoidal" pattern mentioned in this disclosure refers to a pattern where the width of the upper base is smaller than the width of the lower base, but this is not intended to limit the pattern of the "trapezoidal". In other words, a "trapezoidal" pattern where the width of the upper base is greater than the width of the lower base is still within the scope of the patent application in this case.

[0083] The terms "a" or "an" as used in this disclosure are used to describe the elements and components of the invention. These terms are used for convenience of description and to give a basic concept of the invention. This description should be understood to include one or at least one, and unless explicitly stated otherwise, the singular includes the plural. The term "comprising" is an open-ended term and should therefore be interpreted as "including but not limited to". The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated listed items.

[0084] The terms “a,” “another,” “first,” “second,” and “third” used in this disclosure are used to distinguish the elements referred to, and unless otherwise specified, are not used to order or limit the differences between the elements referred to, nor are they used to limit the scope of this case.

[0085] FIG1 is a cross-sectional view of a pixel structure according to some embodiments. Please refer to FIG1. ​​In this embodiment, the pixel structure 50 includes a substrate 500, a plurality of vertical diode dies 520, flip-chip diode dies 530, and an upper wiring layer 540. The plurality of vertical diode dies 520 and flip-chip diode dies 530 are disposed above the substrate 500, and the upper wiring layer 540 is disposed above the plurality of vertical diode dies 520 and flip-chip diode dies 530. The above may be, but is not limited to, directly above. For example, the upper wiring layer 540 in FIG1 has a third wiring 541. The third wiring 541 can be connected to the upper electrode 542 directly above the vertical diode die 520 only through a thin strip-shaped finger electrode structure. At the same time, the third wiring 541 does not pass directly above the flip-chip diode die 530. A lower wiring layer 510 may be disposed above the substrate 500. The lower wiring layer 510 includes a first wiring 511 and a second wiring 512. Part of the first wiring 511 is connected to the lower electrode 513 of the vertical diode die 520, and one of the first wiring 511 is connected to the lower electrode 513 of the flip-chip die 530. The second wiring 512 is connected to the other lower electrode 513 of the flip-chip die 530. It should be understood that the layout of the lower wiring layer 510 shown in FIG1 is only an example for the purpose of understanding and does not limit the lower wiring layer 510 to be located inside the substrate 500. The lower wiring layer 510 can also be disposed on the surface of the substrate 500. In other words, the substrate 500 can be a single-sided, double-sided, or multilayer circuit board.

[0086] The main difference between the first trace 511 and the second trace 512 lies in their polarity. Here, the first trace 511 belongs to the first polarity, and the second trace 512 belongs to the second polarity; furthermore, the third trace 541 also belongs to the second polarity. The polarities of the first and second polarities are opposite; that is, when the first polarity is P-pole, the second polarity is N-pole; when the first polarity is N-pole, the second polarity is P-pole. Figure 2A is a schematic diagram of the layered structure of a vertical diode grain according to some embodiments; Figure 2B is a schematic diagram of the layered structure of a flip-chip diode grain according to some embodiments. Please refer to Figures 1, 2A, and 2B together.

[0087] As shown in Figure 2A, the layered structure of the vertical diode grain 520 can be roughly divided into a first electrode 521, a first doped layer 522, a first quantum well 523, a second doped layer 524, and a second electrode 525. The first electrode 521 and the second electrode 525 have opposite polarities, and the electrodes can be conductive materials, such as metals. The first doped layer 522 and the second doped layer 524 have opposite polarities, and the doped layers can be P-type or N-type doped layers. The doping elements are selected according to the number of valence electrons of the layer material to form P-type or N-type doped layers. For example, the layer material of the doped layer is gallium nitride (GaN), the dopant of the P-type doped layer can be magnesium (Mg) of group 2, and the dopant of the N-type doped layer can be silicon (Si) of group 5. The quantum well is used to confine the movement of carriers to form a quantum binding effect, thereby improving the luminous efficiency of the diode grain. The first electrode 521 is used to connect to the first trace 511 and belongs to the first polarity, while the second electrode 525 is used to connect to the third trace 541 and belongs to the second polarity. The first electrode 521 and the second electrode 525 are arranged in a vertical direction, and the current (electron flow) of the first trace 511 flows to the third trace 541 through the vertical diode die 520.

[0088] As shown in Figure 2B, the layered structure of the flip-chip diode die 530 can be roughly divided into a third electrode 531, a third doped layer 532, a second quantum well 533, a fourth doped layer 534, a fourth electrode 535, and a substrate layer 536. The third electrode 531 and the fourth electrode 535 have opposite polarities, and the third doped layer 532 and the fourth doped layer 534 have opposite polarities. The substrate layer 536 is used in the die fabrication process to support the layered structure, such as a sapphire substrate 500. In some embodiments, the flip-chip diode die 530 may not have a substrate layer 536. The third electrode 531 is used to connect to the first trace 511 and belongs to the first polarity, and the fourth electrode 535 is used to connect to the second trace 512 and belongs to the second polarity. The third electrode 531 and the fourth electrode 535 are arranged in a horizontal direction. The current (electron flow) of the first trace 511 flows to the second trace 512 through the flip-chip diode grain 530.

[0089] Referring to FIG. For example, as shown in FIG. The color category may be defined according to the main band wavelength of the emitted light of the diode die or according to the original factory nominal specification of the diode die. The cover diode grain 530 also has a color category, in this embodiment, the cover diode grain 530 may be red, green, or blue. It should be understood that the color categories of the vertical diode die 520 and the flipped diode die 530 are not limited to red, green and blue. Furthermore, in other embodiments, the vertical diode die 520 and / or the overlay diode die 530 do not have a color category per se, however the beam corresponding to the vertical diode die 520 or the overlay diode die 530 has a color category, as detailed later.

[0090] In some embodiments, the pixel structure 50 comprises a substrate 500 , a plurality of vertical-type diode die 520 , an overlying diode die 530 , an upper trace layer 540 , a plurality of first stoppers 550 , and a second packing layer 539 . As shown in FIG. Furthermore, the third trace 541 is primarily located directly above the first stopper 550 . The first stopper block 550 may be used to avoid the interference of light emitted by the diode grains into its adjacent diode grains. Accordingly, in this embodiment, the first stopper block 550 surrounds the diode grain through the opaque material. In some embodiments, the opaque material may be a black matrix (BM) material or a material with light reflectivity, such as, but not limited to, bauxite, dielectric multilayer films, and reflective resin materials. The second packing layer 539 covers over the crystalline diode grain 530 of the laminated diode, and the top surface of the second packing layer 539 is substantially coplanar with the top surface of the first stopper 550 . The second packing layer 539 may be a light-transmitting material to allow the light emitted by the laminated diode grain 530 to penetrate the second packing layer 539 . Light-transmitting materials may be, but are not limited to, silicone, epoxy resin, polyimide, benzocyclobutene, perfluorocyclobutane, SU8 photoresist, acrylic resin, polyethylene phthalate and polyether amine.

[0091] Figure 3A is a schematic diagram of the configuration of a vertical diode die according to some embodiments; Figure 3B is a schematic diagram of the configuration of a flip-chip diode die according to some embodiments. Please refer to Figures 3A and 3B together. When the vertical diode die 520 is disposed on the substrate 500, the first electrode 521 of the vertical diode die 520 is connected to the electrode 513 below the surface of the substrate 500, while the second electrode 525 of the vertical diode die 520 is not yet connected to a trace, thus forming an open circuit state. Conversely, when the flip-chip diode die 530 is disposed on the substrate 500, the third electrode 531 and the fourth electrode 535 of the flip-chip diode die 530 are respectively connected to the electrode 513 below the surface of the substrate 500, thus forming a conductive state. Therefore, the flip-chip diode 530 can be tested immediately after being transferred to the substrate 500 to confirm whether there are defects in the diode itself, or whether there are defects in the connection between the diode and the substrate 500. However, the vertical diode 520 can only be tested after the upper wiring layer 540 is formed at the end of the packaging process. This makes it difficult to replace the vertical diode 520 in the pixel structure 50 after most of the packaging process has been completed.

[0092] Figures 4A-4D are top views of the pixel structure according to different embodiments. Please refer to Figures 4A-4D together. In this embodiment, the pixel structure 50 includes vertical diode grains V1, V2, V3, and flip-chip diode grains F. The arrangement relationship between the flip-chip diode grain F and the other vertical diode grains V1, V2, V3 can be arbitrarily combined. In some embodiments, all pixel structures 50 contained in the same panel structure 51 have the same arrangement relationship, such as the periodic arrangement of pixel structures 50 in Figure 4A. In other embodiments, the same panel structure 51 may contain pixel structures 50 with multiple arrangement relationships, such as the alternating periodic arrangement of pixel structures 50 in Figures 4A and 4B. Each pixel structure 50 includes four receiving sites, as shown in Figure 4A, the receiving site in the upper left corner corresponds to the flip-chip diode grain F. In some embodiments, the first trace 511 of the substrate 500 forms a lower electrode 513 at each accommodating site, while the second trace 512 forms a lower electrode 513 only at the accommodating site corresponding to the flip-chip diode grain F.

[0093] Within the vertical diode dies V1, V2, and V3, there may be valid vertical diode dies 520 and invalid vertical diode dies 520. In some embodiments, a valid vertical diode die 520 refers to a die itself or the connection between the die and the substrate 500 that is free from defects, while an invalid vertical diode die 520 refers to a die itself or the connection between the die and the substrate 500 that is defective. These defects are defined according to the process yield standards. For example, a beam intensity threshold at a specific wavelength is used as the defect criterion. In other embodiments, a valid vertical diode die 520 refers to a die and its appendages that produce a light-emitting effect free from defects, while an invalid vertical diode die 520 refers to a die and its appendages that produce a light-emitting effect that is defective, as will be detailed later.

[0094] FIG5 is a top view of a panel structure according to some embodiments. Please refer to FIG5. In this embodiment, the pixel structures 50 of FIG4D are periodically arranged to form a panel structure 51. This embodiment only shows four sets of pixel structures 50 included in the panel structure 51. Among them, the pixel structure 50 in the upper left of FIG5 includes an invalid vertical diode die V2', and the pixel structure 50 in the lower right of FIG5 includes an invalid vertical diode die V3'. These pixel structures 50 are defined as the first pixel structure 50. The vertical diode dies 520 included in the pixel structures 50 in the upper right and lower left of FIG5 are all valid vertical diode dies 520. These pixel structures 50 are defined as the second pixel structure 50. In this embodiment, flip-chip diode dies F can be used to replace the invalid vertical diode dies V2' and V3'. In detail, in this embodiment, the pixel structure 50 includes vertical diode chips 520 of various color categories. When any vertical diode chip 520 of a color category is invalid, the pixel structure 50 will be unable to generate a light beam of that color category, resulting in a defect. Furthermore, as mentioned above, the replacement process for the vertical diode chips 520 is relatively complex. In this embodiment, a flip-chip diode chip F is disposed within the pixel structure 50 having invalid vertical diode chips V2' and V3' to generate a light beam of the color category. Thus, a specific type of flip-chip diode chip F can be selected and directly configured at a preset receiving site to replace the invalid vertical diode chips V2' and V3'. Furthermore, the installed flip-chip diode chip F can be immediately inspected to ensure that there are no defects.

[0095] In some embodiments, the color category of the flip-chip diode F is the same as the color category of the ineffective vertical diodes V2' and V3'. Therefore, the light beam generated by the flip-chip diode F can cover the spectral range originally intended to be covered by the ineffective vertical diodes V2' and V3'. In some embodiments, a specific pixel structure 50 includes ineffective vertical diodes V2' and V3', and the color category of the flip-chip diode F is different from the color category of the effective vertical diodes included in the specific pixel structure 50. Therefore, the light beam generated by the flip-chip diode F can cover the spectral range that the light beam generated by the specific pixel structure 50 cannot cover. In some embodiments, the second pixel structure 50 includes receiving sites corresponding to the flip-chip diode F, which are filled with a third filler layer 580. The third filler layer 580 can be used to seal the substrate 500 below the receiving site electrode 513, and it can be made of the light-transmitting or opaque material described in this disclosure. In some embodiments, the third filler layer 580 can also be made of the same material as the first stop 550 or the second filler layer 539. In this embodiment, the panel structure 51 simultaneously includes a first pixel structure 50 and a second pixel structure 50. In other words, each pixel structure 50 on the panel structure 51 does not necessarily include flip-chip diode chips F, and each pixel structure 50 on the panel structure 51 does not necessarily include the third filler layer 580. In addition, the panel structure 51 may include invalid vertical diode chips V2', V3', which can also be removed.

[0096] Figure 6 is a flowchart of the pixel structure repair method according to the first embodiment; Figures 7A to 7H are process diagrams of the pixel structure repair method according to the first embodiment. Please refer to Figures 7A to 7H in sequence according to the steps in Figure 6. In some embodiments, the pixel structure 50 repair method (hereinafter referred to as the "repair method") can be used to repair pixels containing invalid vertical diode grains V2' and V3' to generate pixel structure 50. The repair method is described below according to different embodiments. It should be understood that although the flowcharts disclosed herein are presented in a specific order, the order is only illustrative and implementations using other different orders are conceivable.

[0097] Referring to FIG. In this embodiment, a first trace 511 and a second trace 512 are provided above the substrate 500, respectively connected to the lower electrode 513 . The lower electrode 513 is disposed at a specific position above the substrate 500 , equivalent to the containment site. Wherein, within a specific capacitance site there is a pair of lower electrodes 513 , suitable for connecting the laminated diode grain 530 , the traces to which the pair of lower electrodes 513 are connected are the first and second traces 512 , respectively. The material of the substrate 500 may be, but is not limited to, silicon (Si), silicon dioxide (SiO2), gallium arsenide (GaAs), silicon carbide (SiC), glass, silicone (Silicone), epoxy resin (Epoxy), polyamide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist (Acrylic resin, acrylic resin Resin), polyethylene phthalate (PET) and polyetherimide (Polyetherimide). The lower electrode 513 and traces are conductive materials, such as metals, shaped by, but not limited to, coating, electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), regioselective deposition (ASD), and atomic layer deposition (ALD).

[0098] Referring to Figure 7B, the repair method sets the vertical type diode die 520 on the substrate 500 (step S513). The vertical type diode die 520 is disposed on the substrate 500 , the first electrode 521 of which may be electrically connected to the lower electrode 513 of the lower trace layer 510 by soldering. Referring again to FIG. 7C , the repair method forms a first stopper 550 on a substrate 500 (step S514 ), a first stopper 550 can be formed on the surface of the substrate 500 , and can also be attached to the surface of the substrate 500 after forming. The first stopper block 550 forms a capacitive site 551 around the position of the respective lower electrode 513 , two capacitive sites 551 of FIG.

[0099] Referring to Figure 7D, the repair method forms a first filling layer 538 between the first blocks 550 (step S515). The first filling layer 538 is used to cover and protect the vertical diode grain 520, exposing only a portion of the second electrode 525; in addition, the first filling layer 538 can also be used to cover and protect the lower electrode 513 within the vacancy, exposing only a portion of the lower electrode 513. The first filling layer 538 can be made of the light-transmitting material or the opaque material described in this disclosure, and the materials used for different receiving sites 551 can be different. For example, the vertical diode grain 520 is covered with a first filling layer 538 formed of a light-transmitting material, while the vacancy can be covered with a first filling layer 538 formed of an opaque material.

[0100] Refer to Figure 7E. The repair method configures the upper electrode 542 and the wiring on the first filling layer 538 (step S516). In this embodiment, the upper electrode 542 is disposed on the vertical diode die 520 and electrically connected to the second electrode 525 of the vertical diode die 520. The upper wiring layer 540 is disposed on the upper electrode 542 and the first stop 550 to form a third wiring 541. The third wiring 541 mainly passes directly above the first stop 550 and extends to the surface of the upper electrode 542 through a thin strip structure. The upper electrode 542 is a light-transmitting conductive material, such as, but not limited to, indium tin oxide (ITO), zinc oxide (ZnO), fluorine-doped tin oxide (FTO), graphene, and poly(3,4-ethylenedioxythiophene)-polystyrene sulfonate (PEDOT:PSS). The upper trace is made of conductive material and can be formed on the upper electrode 542 and the first stop block 550 using the trace fabrication process described in this disclosure.

[0101] In step S517, the repair method determines whether each pixel has invalid vertical diode chips V2' and V3'. For example, the repair method provides a power supply and electrically connects the first trace 511 to the first polarity of the power supply and the third trace 541 to the second polarity of the power supply, so that current passes through each vertical diode. Subsequently, the repair method uses a camera to photograph each pixel structure 50 to determine whether the pixel structure 50 does not generate a beam of a specific color category, or whether the beam intensity of a specific accommodating point 551 does not reach the intensity threshold, thereby determining whether each vertical diode chip 520 in the pixel structure 50 is valid. When the repair method determines that each pixel does not have invalid vertical diode chips V2' and V3' (step S517, the determination result is "no"), a filling layer is formed between the first blocks 550 (step S518), for example, a third filling layer 580 is formed in the vacancy. In some embodiments, the third filler layer 580 fills the receiving site 551 until the top surface of the third filler layer 580 is substantially coplanar with the top surface of the first stop 550.

[0102] When the repair method determines that any pixel contains invalid vertical diode chips V2' and V3' (step S517, the determination result is "yes"), then a flip-chip diode chip 530 is set (step S519). In some other embodiments, between steps S517 and S519, the repair method further includes determining whether the number of invalid vertical diode chips V2' and V3' is greater than a quantity threshold (not shown). The quantity threshold may refer to the defect acceptance standard of the panel structure 51 (including multiple pixel structures 50). When the repair method determines that the number of invalid vertical diode chips V2' and V3' is less than the quantity threshold, step S518 is executed; when the repair method determines that the number of invalid vertical diode chips V2' and V3' is greater than or equal to the quantity threshold, step S519 is executed.

[0103] Referring to Figures 7F and 7G together, in this embodiment, the repair method determines the state of a specific pixel structure 50 to determine the presence and / or color category of a defect. The repair method selects a specific flip-chip diode die 530 and transfers it to the receiving site 551 of the pixel structure 50 by an aspirating method. The color category of the specific flip-chip diode die 530 corresponds to the color category of the defect. Subsequently, referring to Figure 7H, the repair method forms a filling layer between the first blocks 550 (step S518), for example, forming a second filling layer 539 on the flip-chip diode die 530. In this embodiment, the second filling layer 539 fills the receiving site 551 until the top surface of the second filling layer 539 is substantially coplanar with the top surface of the first block 550.

[0104] Figure 8 is a flowchart of the pixel structure repair method according to the second embodiment; The major difference between the repair methods of the second embodiment and the first embodiment lies in steps S527 through steps S5212. In this embodiment, the vertical type diode die 520 itself does not have a color category. For example, the vertical type diode die 520 is a short wavelength light-emitting diode die, such as, but not limited to, a blue light diode or a UV light diode. In this embodiment, short-wavelength light-emitting diode grains are used to excite a photoconverting material to produce an emitted beam corresponding to a specific color class. Short-wavelength light-emitting diode grains may refer to light-emitting diode grains used to generate an excitation beam. The wavelength of the excitation beam is lower than that of the emission beam of the photoconverting material, or, below the wavelength of the absorption edge of the photoconverting material. Photoconverting materials can be either fluorescent materials or quantum dots (Quantum Dots), fluorescent materials can adopt Sulfides, Oxides, Oxysulfides, Nitrides, and Oxy nitrides), halides, or organic polymers, such as but not limited to titanium aluminum garnet (YAG), zinc silicate (Zn₂SiO₄), zinc sulfide (ZnS), and poly(p-phenylene vinylidene). The materials of the quantum dots may be, but are not limited to, cadmium selenide (CdSe), indium phosphide (InP), zinc selenide (ZnTeSe), lead sulfide (PbS), and perovskite.

[0105] In step S527, the repair method determines whether each pixel has invalid vertical diode chips V2' and V3'. In this embodiment, the repair method can determine whether the beam generated by the vertical diode chip 520 exceeds the intensity threshold, or whether the generated beam exceeds a preset wavelength range. When the repair method determines that each pixel does not have invalid vertical diode chips V2' and V3' (step S527, the determination result is "No"), a filling layer is formed between the first blocks 550 (step S528); when the repair method determines that any pixel has invalid vertical diode chips V2' and V3' (step S527, the determination result is "Yes"), a flip-chip diode chip 530 is set (step S529). In this embodiment, the repair method determines that there is a receiving site 551 for invalid vertical diode chips V2' and V3' within the pixel structure 50, thereby confirming the color category of the corresponding emitted beam. For example, in Figure 4D, vertical diode chip V1 corresponds to a red emitted light beam, vertical diode chip V2 corresponds to a green emitted light beam, and vertical diode chip V3 corresponds to a blue emitted light beam. Therefore, for the pixel structure 50 in the lower right corner of Figure 5, if it is confirmed that the lower left corner of pixel structure 50 contains an invalid vertical diode chip V3', it can be determined that pixel structure 50, after completion, has the defect of being unable to generate blue light. It should be understood that "corresponds" here means that the receiving site 551 corresponding to a specific vertical diode chip V1, V2, V3 is the same as the receiving site 551 corresponding to an emitted light beam of a specific color, but it is not limited to specific vertical diode chips V1, V2, V3 producing emitted light beams of a specific color. For example, vertical diode chip V1 produces a red light beam; or, vertical diode chip V1 produces ultraviolet light, which is then converted to produce a red light beam. Based on this, the repair method selects a specific flip-chip diode die 530 and transfers it to the receiving site 551 of the pixel structure 50. The color category of the specific flip-chip diode die 530 corresponds to the color category of the defect. Subsequently, the repair method forms a filling layer between the first blocks 550 (step S528), for example, forming a second filling layer 539 on the flip-chip diode die 530.

[0106] Referring to FIG9A, the repair method forms a second stop 560 on top of the first stop 550 (step S5210). In this embodiment, the second stop 560 is located directly above the first stop 550 and surrounds only the receiving site 551 containing the vertical diode grain 520. In other embodiments, the second stop 560 may also be located within the first stop 550 surrounding the receiving site 551. Furthermore, the second stop 560 may also surround the receiving site 551 containing the flip-chip diode grain 530. The second stop 560 may be made of the opaque material described in this disclosure. In some embodiments, the second stop 560 is made of the same material as the first stop 550.

[0107] Referring to FIG9B, the repair method forms a first light conversion material layer 526 between the second blocks 560 (step S5211). The first light conversion material layer 526 has a color category, which corresponds to a specific receiving site 551 on the pixel structure 50. In this embodiment, the color category of each first light conversion material 526 is different from the color category of the flip-chip diode chip 530. For example, the two first light conversion material layers 526 in FIG9B are used to generate red and green emission beams, respectively, while the flip-chip diode chip 530 is used to generate a blue emission beam. Referring to FIG9C, the repair method forms a protective layer 570 on the first block 550 (step S5212). In this embodiment, the protective layer 570 is used to cover and protect the vertical diode chip 520, the flip-chip diode chip 530, and the light conversion material layer. The protective layer 570 can be made of the light-transmitting material described in this disclosure. In some embodiments, the protective layer 570 is made of the same material as the second filler layer 539.

[0108] Figure 10 is a flowchart of the pixel structure repair method according to the third embodiment; Figure 11 is a process diagram of the pixel structure repair method according to the third embodiment. Please refer to Figures 10 and 11 together. The main difference between the repair method of the third embodiment and the second embodiment lies in steps S538 to S5311. In this embodiment, the flip-chip diode chip 530 itself does not have a color category. For example, the flip-chip diode chip 530 is a short-wavelength light-emitting diode chip.

[0109] In step S537, when the repair method determines that any pixel has invalid vertical diode grains V2' and V3' (step S537, the determination result is "yes"), a flip-chip diode grain 530 is set (step S539). In this embodiment, the repair method determines that there are accommodating sites 551 for invalid vertical diode grains V2' and V3' within the pixel structure 50, thereby confirming the color category of the corresponding emitted beam. However, the flip-chip diode grain 530 does not need to correspond to the color category of the defect. Subsequently, the repair method forms a second light conversion material layer 537 between the first blocks 550 (step S538). The second light conversion material layer 537 has a color category and corresponds to the color category of the defect. For example, Figure 11 includes three first light conversion material layers 526, used to generate red, green, and blue emitted light beams, respectively. If the vertical diode die 520 corresponding to the red beam is invalid, the repair method forms a second light conversion material layer 537 corresponding to the red beam on the flip-chip diode die 530. In other embodiments, when the repair method determines that the vertical diode die 520 at a specific location of the pixel structure 50 is invalid, the first light conversion material layer 526 is not formed on that specific location.

[0110] In some other embodiments, the repair method determines that there are invalid vertical diode die V2', V3' accommodating sites 551 within the pixel structure 50. Then, in step S538, the repair method forms a second light conversion material layer 537 between the first blocks 550 to cover the flip-chip diode die 530. Next, a second block 560 is formed on the first block 550 (step S5310). In step S5311, the repair method forms a first light conversion material layer 526 between the second blocks 560 to cover the vertical diode die 520. The first light conversion material layers 526 and the second light conversion material layers 537 have different color categories. Next, a protective layer 570 is formed on the first block 550 (step S5312). In this embodiment, the repair method does not need to confirm the color category of the defect before selecting a second light conversion material layer 537 with the corresponding color category. Therefore, the placement site 551 of pixel structure 50 is not necessarily related to the color category.

[0111] Referring again to Figure 1, in some embodiments, the pixel structure 50 includes a substrate 500, a plurality of vertical diode chips 520, flip-chip diode chips 530, and an upper wiring layer 540. The flip-chip diode chips 530 can be disposed in the pixel structure 50 after the repair process or before the repair process. In some embodiments, the pixel structure 50 may face the problem that pure color micro-light-emitting diodes need to undergo multiple complex mass transfers and complex repair processes during the manufacturing process, while color-conversion micro-light-emitting diodes have problems such as complex structure, narrow color gamut, and low reliability. In some embodiments, the hybrid micro-light-emitting diode structure and its repair method described in the following embodiments can be used to implement or apply to the pixel structure 50. By combining pure color micro-light-emitting diodes and color-conversion micro-light-emitting diodes in the micro-light-emitting diode, a pixel structure 50 with a simple structure, wide color gamut, high reliability, and simple repair process can be achieved. However, this disclosure is not limited to this. In different design considerations or application scenarios, other structures, processes or manufacturing processes may be adopted to realize the pixel structure 50 disclosed herein.

[0112] Referring to Figures 12 to 14, a hybrid micro-light-emitting diode structure 40 includes a substrate 400, a plurality of micro-light-emitting diode grains 410 (including a red micro-light-emitting diode grain 410R, a green micro-light-emitting diode grain 410G, a blue micro-light-emitting diode grain 410B, and a spare micro-light-emitting diode grain 410S), an isolation layer 420, a filler layer 430, and a light-transmitting layer 440. The red micro-light-emitting diode grain 410R, the green micro-light-emitting diode grain 410G, the blue micro-light-emitting diode grain 410B, the spare micro-light-emitting diode grain 410S, and the isolation layer 420 are disposed on the substrate 400. In some embodiments, the spare micro-light-emitting diode grain 410S may be another blue micro-light-emitting diode grain or an ultraviolet (UV) micro-light-emitting diode grain, and is not limited thereto.

[0113] The isolation layer 420 surrounds the spare micro-light-emitting diode (LED) chip 410S and forms an inkjet space 450 with the spare LED chip 410S, wherein the inkjet space 450 is used to fill an inkjet material IM. In other words, in some embodiments, the combination of the spare LED chip 410S, the isolation layer 420, the inkjet space 450, and the inkjet material IM can be regarded as a color-converting LED. By filling the inkjet space 450 with the inkjet material IM and illuminating the spare LED chip 410S, the color-converting LED system can emit light corresponding to the color of the inkjet material IM. In other words, in some embodiments, the light emitted by the spare LED chip 410S (e.g., blue light or ultraviolet light) can be converted to different colors by the inkjet material IM, allowing the color-converting LED to emit light of different colors.

[0114] Any one of the red light-emitting diode (LED) chip 410R, the green LED chip 410G, the blue LED chip 410B, and the spare LED chip 410S is adjacent to at least one of the other three. Taking FIG13 as an example, in this embodiment, the red LED chip 410R, the green LED chip 410G, the blue LED chip 410B, and the spare LED chip 410S are sequentially arranged along a first direction (e.g., but not limited to the X-axis direction) on the substrate 400 to form a rectangular array with 4 rows and 1 column.

[0115] Taking Figure 14 as an example, in this embodiment, the red micro-light-emitting diode (LED) chip 410R, the green LED chip 410G, the blue LED chip 410B, and the spare LED chip 410S are arranged sequentially along a first direction (e.g., but not limited to the X-axis direction) and a second direction (e.g., but not limited to the Y-axis direction) to be disposed on the substrate 400, thereby forming a rectangular array with 2 rows and 2 columns.

[0116] It should be noted that the arrangement order of the red light-emitting diode (LED) chip 410R, the green LED chip 410G, the blue LED chip 410B, and the spare LED chip 410S is not limited to the above embodiments (including Figures 12 and 14). For example, the spare LED chip 410S can be disposed between any two of the red LED chip 410R, the green LED chip 410G, and the blue LED chip 410B (not shown). Alternatively, the red LED chip 410R can be disposed between any two of the green LED chip 410G, the blue LED chip 410B, and the spare LED chip 410S (not shown).

[0117] In some embodiments, the hybrid micro-light-emitting diode structure 40 can be applied in a micro-light-emitting diode display device. The hybrid micro-light-emitting diode structure 40 constitutes a pixel in the micro-light-emitting diode display device, and the red micro-light-emitting diode chip 410R, the green micro-light-emitting diode chip 410G, the blue micro-light-emitting diode chip 410B, and the spare micro-light-emitting diode chip 410S are each a sub-pixel. The phrase "any one of the red micro-light-emitting diode chip 410R, the green micro-light-emitting diode chip 410G, the blue micro-light-emitting diode chip 410B, and the spare micro-light-emitting diode chip 410S is adjacent to at least one of the other three" means that each sub-pixel in a single pixel is adjacent to at least one of the other three sub-pixels. If two adjacent sub-pixels belong to different pixels, they are not considered "adjacent" as described herein.

[0118] Please refer to Figures 12, 13, 15, and 16. The manufacturing process of the hybrid micro-light-emitting diode structure 40 and the repair method when the micro-light-emitting diode chip 410 is damaged will be described below using Figures 12 and 13 as examples. First, the red micro-light-emitting diode chip 410R, the green micro-light-emitting diode chip 410G, the blue micro-light-emitting diode chip 410B, and the spare micro-light-emitting diode chip 410S are disposed on the substrate 400 (step S40). In some embodiments, the micro-light-emitting diode chip 410 can be disposed on the substrate 400 through mass transfer technology.

[0119] In some embodiments, the substrate 400 may be made of an opaque insulating material, such as, but not limited to, silicon (Si), silicon dioxide (SiO2), gallium arsenide (GaAs), and silicon carbide (SiC). In other embodiments, the substrate 400 may be made of a transparent insulating material, such as, but not limited to, glass, silicone, epoxy, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene phthalate (PET), and polyetherimide.

[0120] In some embodiments, when multiple micro-light-emitting diode (LED) chips 410 are disposed on the substrate 400, each LED chip 410 is electrically connected to at least one driving circuit (not shown) in the hybrid LED structure 40 through paired electrodes (including N-polarity and P-polarity). In some embodiments, the hybrid LED structure 40 can drive each LED chip 410 to emit light through a single driving circuit. In other embodiments, the hybrid LED structure 40 can also drive each LED chip 410 to emit light through multiple driving circuits respectively. In other words, in some embodiments, each LED chip 410 can be driven independently to emit light independently.

[0121] In some embodiments, when the spare micro-light-emitting diode (LED) chip 410S is another blue LED chip, the spare LED chip 410S is adjacent to the blue LED chip 410B (as shown in FIG. 12). Therefore, when multiple LED chips 410 are disposed on the substrate 400 using mass transfer technology, the blue LED chip 410B and the spare LED chip 410S can be simultaneously transferred and disposed in adjacent positions, thereby improving the efficiency of mass transfer. In some embodiments, the spare LED chip 410S is further adjacent to the red LED chip 410R or the green LED chip 410G. Taking FIG. 14 as an example, in this embodiment, the spare LED chip 410S is adjacent to the green LED chip 410G and the blue LED chip 410B.

[0122] After step S40, an isolation layer 420 is disposed on the substrate 400 to surround the standby micro-light-emitting diode (LED) die 410S, such that the isolation layer 420 and the standby LED die 410S form an inkjet space 450 (step S41). In some embodiments, the isolation layer 420 can be disposed on the substrate 400 by deposition techniques, such as, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), area selective deposition (ASD), and atomic layer deposition (ALD).

[0123] Please refer to Figures 13 and 17. As shown in Figure 13, in some embodiments, the isolation layer 420 includes an opaque material 420A (as shown in Figure 13), and the opaque material 420A surrounds the standby micro-LED chip 410S and the inkjet space 450. In other embodiments, the isolation layer 420 includes an opaque material 420A and an isolation material 420B (as shown in Figure 17), the opaque material 420A surrounds the inkjet space 450, and the isolation material 420B surrounds the standby micro-LED chip 410S. In other words, in this embodiment, the isolation material 420B is formed on the substrate 400 to surround the standby micro-LED chip 410S, and then the opaque material 420A is formed on the isolation material 420B to surround the inkjet space 450.

[0124] In some embodiments, the isolation layer 420 is used to prevent the light emitted by the standby micro-light-emitting diode (LED) chip 410S from interfering with the adjacent LED chip 410. Therefore, the isolation layer 420 surrounds the inkjet space 450 through an opaque material 420A. In some embodiments, the opaque material 420A may be a black matrix (BM) material or a light-reflective material, such as, but not limited to, alumina, dielectric multilayer film, and reflective resin material. In some embodiments, the isolation material 420B may be a light-transmitting material (e.g., but not limited to, silicone, epoxy resin, polyimide, benzocyclobutene, perfluorocyclobutane, SU8 photoresist, acrylic resin, polyethylene terephthalate, and polyetherimide) or an opaque material (e.g., but not limited to, black matrix material, alumina, dielectric multilayer film, and reflective resin material).

[0125] After step S41, the red micro-light-emitting diode (LED) chip 410R, the green LED chip 410G, and the blue LED chip 410B are lit up respectively to check whether any of them is damaged and unable to emit light (step S42). In some embodiments, the failure of the LED chip 410 to emit light may include its own defects preventing it from emitting light, or physical damage during the mass transfer process, and is not limited thereto.

[0126] When one of the red LED chip 410R, the green LED chip 410G, and the blue LED chip 410B is damaged, it means that the hybrid LED structure 40 cannot emit light of the correct color. In this case, the hybrid LED structure 40 needs to be repaired. Therefore, in some embodiments after step S42, the inkjet space 450 can be filled with inkjet material IM corresponding to the color of the damaged LED chip 410 (step S43) to compensate for the missing color light in the hybrid LED structure 40. For example, when the red LED chip 410R is damaged and cannot emit light, it means that the hybrid LED structure 40 cannot emit red light. At this time, the inkjet space 450 can be filled with red inkjet material IM to change the color of the light emitted by the standby micro-light-emitting diode chip 410S, thereby enabling the hybrid micro-light-emitting diode structure 40 to emit red light through the standby micro-light-emitting diode chip 410S and the red inkjet material IM.

[0127] In some embodiments, the inkjet material IM is a quantum dot (QD). A quantum dot is a nanomaterial used to change the wavelength of light emitted by the micro-light-emitting diode (μLED) grains 410 (hereinafter referred to as μLED light) to change the color of the μLED light. For example, a larger quantum dot system (e.g., a diameter of 5 to 6 nanometers, but not limited thereto) can convert the color of the μLED light to red or orange, and a smaller quantum dot system (e.g., a diameter of 2 to 3 nanometers, but not limited thereto) can convert the color of the μLED light to blue or green. In some embodiments, the quantum dot system is selected from materials such as cadmium selenide (CdSe), indium phosphide (InP), zinc telluride selenide (ZnTeSe), and perovskite, but not limited thereto.

[0128] In some embodiments, when one of the red LED chip 410R, the green LED chip 410G, and the blue LED chip 410B is damaged, the damaged LED chip 410 can be constantly turned off to reduce the power consumption of the hybrid LED structure 40 during use. For example, when the red LED chip 410R is damaged, the red LED chip 410R is constantly turned off, so that only the green LED chip 410G, the blue LED chip 410B, and the spare LED chip 410S in the hybrid LED structure 40 can emit light.

[0129] After the micro-light-emitting diode (LED) grains 410 in the hybrid LED structure 40 are repaired, the hybrid LED structure 40 can continue its manufacturing process. Therefore, in some embodiments after step S43, a filler material is filled onto the substrate 400 to form a filler layer 430 (step S44). Here, the filler layer 430 is disposed on the substrate 400, and the filler layer 430 is used to fix each LED grain 410 and the isolation layer 420 onto the substrate 400. In some embodiments, the filler material can be a transparent material with adhesive properties, such as, but not limited to, adhesive, underfill, anisotropic conductive adhesive (ACP), anisotropic conductive film (ACF), non-conductive adhesive (NCP), and non-conductive film (NCF).

[0130] Finally, after step S44, the light-transmitting layer 440 is disposed on the filler layer 430 (step S45) to strengthen and protect the hybrid micro-light-emitting diode structure 40. In some embodiments, the material of the light-transmitting layer 440 may be a rigid material with light transmittance, such as, but not limited to, glass and acrylic. In other embodiments, when the standby micro-light-emitting diode grain 410S is an ultraviolet micro-light-emitting diode grain, the material of the light-transmitting layer 440 may be a rigid material with light transmittance and UV resistance, such as, but not limited to, polycarbonate (PC) and polymethyl methacrylate (PMMA).

[0131] When the red LED chip 410R, green LED chip 410G, and blue LED chip 410B are all undamaged, the inkjet space 450 does not need to be filled with any inkjet material IM. Therefore, in some embodiments after step S42, the filling material can be directly filled onto the substrate 400 to form a filling layer 430 (step S44), and the light-transmitting layer 440 can be disposed on the filling layer 430 (step S45). In some embodiments, when the red LED chip 410R, green LED chip 410G, and blue LED chip 410B are all undamaged, the spare LED chip 410S can be constantly turned off to reduce the power consumption of the hybrid LED structure 40 during use. In other words, at this time, only the red micro-light-emitting diode grain 410R, the green micro-light-emitting diode grain 410G, and the blue micro-light-emitting diode grain 410B in the hybrid micro-light-emitting diode structure 40 can emit light.

[0132] According to any embodiment, the hybrid micro-light-emitting diode structure combines the characteristics of a pure-color micro-light-emitting diode and a color-conversion micro-light-emitting diode, giving the hybrid micro-light-emitting diode structure the advantages of both small area and high color accuracy. Furthermore, because the repair process of the hybrid micro-light-emitting diode structure is simple, when a panel or display device made from the hybrid micro-light-emitting diode structure has a defect, the manufacturer can easily find the location of the defect and repair it, thereby improving the yield and reliability of the panel and display device.

[0133] Referring again to Figure 1, in some embodiments, the pixel structure 50 includes a substrate 500, a plurality of vertical diode dies 520, flip-chip diode dies 530, and an upper wiring layer 540. In some embodiments, the vertical diode dies 520 or flip-chip diode dies 530 may face variations in production equipment or manufacturing technology during application, resulting in specification differences between different types of diode dies. The height differences between diode dies may adversely affect subsequent eutectic bonding processes, such as causing poor bonding and reducing process yield. These height differences may also negatively impact alignment accuracy during the process and the optical performance of the final product. In some embodiments, the diode dies and their manufacturing methods described in the following embodiments can be used to implement or apply to the vertical diode dies 520 or flip-chip diode dies 530, and the pixel structure 50 can also be used to implement or apply to the panel structures described in the following embodiments. However, this disclosure is not limited to this. In different design considerations or application scenarios, other structures, processes or fabrication methods may be used to realize the vertical diode grain 520 or flip-chip diode grain 530 disclosed herein.

[0134] Figure 18 is a schematic diagram of multiple diode grains with different grain heights according to some embodiments. In this embodiment, there are three diode grains 60, namely a first diode grain 601, a second diode grain 602, and a third diode grain 603. In this embodiment, the diode grains 60 are vertical diode grains, and each vertical diode grain includes a top electrode 62 (i.e., top electrodes 621, 622, 623), an epitaxial layer 63 (i.e., epitaxial layers 631, 632, 633), a bottom electrode 64 (i.e., bottom electrodes 641, 642, 643), and a second substrate 65 (i.e., second substrate 651, 652, 653). The bottom electrode 64 is disposed on the second substrate 65, the epitaxial layer 63 is disposed on the bottom electrode 64, and the top electrode 62 is disposed on the epitaxial layer 63. In other embodiments, the vertical diode die may not include the second substrate 65, and the epitaxial layer 63 may also be a multilayer structure, such as including P-type or N-type doped layers. The first diode die 601, the second diode die 602, and the third diode die 603 shown in FIG18 are placed on the same horizontal plane. The first reference line BL1 represents the height of the horizontal plane, and the second reference line BL2 represents the height of the upper surface of one of the diode dies 60, for example, the height of the upper surface of the top electrode 622 of the second diode die 602 in FIG18. In this embodiment, the height of the first diode die 601 is higher than the second reference line BL2, and the height of the third diode die 603 is lower than the second reference line BL2. The main reason is the process variation between the individual diode dies 60, resulting in the first diode die 601 having a thicker bottom electrode 641, and the third diode die 603 having a thinner epitaxial layer 633.

[0135] FIG19 is a flowchart of a method for manufacturing a diode die according to some embodiments; FIG20A to FIG20K are schematic diagrams of a method for manufacturing a diode die according to some embodiments. Please refer to FIG20A to FIG20K sequentially based on FIG19. As shown in FIG20A, the manufacturing method includes providing a first substrate 61 (step S601) and forming an epitaxial layer 63 on the first substrate 61 (step S602). The material of the first substrate 61 can be selected from the group consisting of silicon (Si), silicon dioxide (SiO2), aluminum oxide (Al2O3), gallium arsenide (GaAs), silicon carbide (SiC), glass, silicone, epoxy resin, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene phthalate (PET), polyetherimide, and combinations thereof. The material of the epitaxial layer 63 can be selected from the group consisting of gallium nitride (GaN), gallium arsenide (GaAs), indium gallium phosphide (InGaP), zinc selenide (ZnSe), silicon carbide (SiC), aluminum gallium nitride (AlGaN), zinc sulfide (ZnS), silicon (Si), and combinations thereof. The epitaxial layer 63 has the same or approximately the same lattice constant as the first substrate 61. The process for forming the epitaxial layer 63 can be a deposition method, such as, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), zone selective deposition (ASD), and atomic layer deposition (ALD).

[0136] As shown in FIG20B, the manufacturing method includes forming a first interconnect layer 66 on the epitaxial layer 63 (step S603). The first interconnect layer 66 serves as an intermediate layer between the epitaxial layer 63 and the bottom electrode 64 to enhance the bonding strength between the two. The process for forming the first interconnect layer 66 can be a deposition method or a coating method. As shown in FIG20C and FIG20D, the manufacturing method includes setting an electrode layer on the first interconnect layer 66 (step S604), so that the bottom electrode 64 is indirectly bonded to the epitaxial layer 63. In this embodiment, the bottom electrode 64 is pre-formed and then set on the first interconnect layer 66. Therefore, the bottom electrode 64 can have a thicker layered structure to facilitate further processing of the bottom electrode 64 in subsequent processes. The process for setting the electrode layer can be a pressing and annealing process. The bottom electrode 64 can be a conductive material, such as, but not limited to, gold, silver, copper, aluminum, or alloys containing such metals.

[0137] As shown in FIG20E, the manufacturing method includes polishing the electrode layer (step S605). In this embodiment, process variations in the bottom electrode 64 may cause the thickness specification of the bottom electrode 64 to be non-compliant. The polishing process in step S605 makes the thickness specification of the bottom electrode 64 conform to the absolute thickness acceptance specification and / or the relative thickness acceptance specification. The absolute thickness acceptance specification refers to an absolute value, for example, limiting the thickness value of the bottom electrode 64 to an acceptable range between 10 μm and 100 μm. In some embodiments, the bottom electrode 64 of the diode grain 60 is shaped into a special shape (e.g., trapezoidal) for use in a pre-alignment process. The special shape (e.g., trapezoidal) must conform to a specified absolute value range. Accordingly, the manufacturing method includes polishing the electrode layer to make its thickness conform to the thickness specification acceptance range of the special shape. The relative thickness allowable specification refers to a relative value, such as limiting the thickness value of the bottom electrode 64 of a specific diode grain 60 so that the height of the specific diode grain 60 is substantially the same as the height of other diode grains 60, as will be described in detail later.

[0138] As shown in FIG20F, the manufacturing method includes forming a second interconnect layer 67 on the electrode layer (step S606). The second interconnect layer 67 serves as an intermediate dielectric layer between the second substrate 65 and the bottom electrode 64 to enhance the bonding strength between the two. The process for forming the second interconnect layer 67 can be a deposition method or a coating method. As shown in FIG20G, the manufacturing method includes setting the second substrate 65 on the second interconnect layer 67 (step S607), so that the second substrate 65 is indirectly bonded to the bottom electrode 64. The process for setting the second substrate 65 can be a pressing and annealing method. The material of the second substrate 65 can be selected from the group consisting of silicon (Si), silicon dioxide (SiO2), aluminum oxide (Al2O3), gallium arsenide (GaAs), silicon carbide (SiC), glass, silicone, epoxy resin, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene phthalate (PET), polyetherimide, and combinations thereof. The material of the second substrate 65 can be different from that of the first substrate 61. For example, the first substrate 61 may be a substrate that facilitates the formation of the epitaxial layer 63, while the second substrate 65 may be a reflective substrate to improve the luminous efficiency of the diode grain 60. Alternatively, the material of the second substrate 65 can be the same as that of the first substrate 61. For example, both the first substrate 61 and the second substrate 65 may be sapphire substrates.

[0139] As shown in FIG20H, the manufacturing method includes removing the first substrate 61 (step S608). Based on this, the diode substrate of the semi-finished product is transferred from the first substrate 61 to the second substrate 65. In this embodiment, when the diode substrate is inverted, the second substrate 65 is located at the bottom of the diode substrate, and the epitaxial layer 63 is located at the top, to facilitate subsequent processes on the epitaxial layer 63. As shown in FIG20I, the manufacturing method includes performing another electrode process (step S609). Specifically, in this embodiment, another electrode layer is formed on the surface of the epitaxial layer 63 and is cut into multiple independent grains, such that each independent grain has a top electrode 62. The material of the top electrode 62 can be a conductive material, and can be the same as or different from the material of the bottom electrode 64. The top electrode 62 can be formed by deposition or lamination.

[0140] As shown in FIG20J, the manufacturing method includes cutting the electrode layer (step S610). In this embodiment, the bottom electrode layer is cut to form bottom electrodes 64 of individual grains. In some embodiments, the manufacturing method may use a specific angle to cut the electrode layer so that the side surface of the bottom electrode 64 of each individual grain has an angle, thereby forming a trapezoidal bottom electrode 64. The manufacturing method of this embodiment only cuts the bottom electrode layer. In other embodiments, the manufacturing method cuts the bottom electrode layer and the second substrate 65 to form the bottom electrode 64 of each individual grain and the bottom substrate (e.g., the first diode grain 601 shown in FIG18).

[0141] As shown in FIG20K, the manufacturing method includes removing the second substrate 65 (step S611) and forming diode grains 60 (step S612). In this embodiment, the manufacturing method produces at least seven diode grains 60, which can be applied to the panel structure 600. FIG21 is a schematic diagram of diode grains according to some embodiments. Please refer to FIG21. In this embodiment, the diode grain 60 includes a top electrode 62, an epitaxial layer 63, a bottom electrode 64, and a conductor layer 68 (i.e., conductor layers 681, 682, 683). The bottom electrode 64 is disposed on the conductor layer 68, the epitaxial layer 63 is disposed on the bottom electrode 64, and the top electrode 62 is disposed on the epitaxial layer 63. The conductor layer 68 can be a second connection layer 67 or a conductive layer formed on the surface of the bottom electrode 64 (or the second connection layer 67) to protect the bottom electrode 64 and connect to the external substrate. In this embodiment, the bottom electrode 64 has a trapezoidal structure, with its sidewalls forming the hypotenuse of the trapezoid and its thickness representing the height of the trapezoid. The trapezoidal structure of the bottom electrode 64 facilitates pre-alignment of the diode chips 60 before transfer. For example, the trapezoidal structure of the bottom electrode 64 corresponds to a trapezoidal recess on the alignment pad, allowing a large number of aligned diode chips 60 to be transferred to the external substrate in one go. In this embodiment, the diode chips 60 may have a lower height limit to facilitate alignment with the recesses on the alignment pad.

[0142] The manufacturing methods described in the foregoing embodiments (e.g., some or all of steps S601 to S612) can be repeated to produce the first diode grain 601, the second diode grain 602, and the third diode grain 603. However, process variations may exist in the manufacturing method, resulting in differences in the size specifications of each diode grain 60. For example, one or more of the epitaxial layer 63 formed in step S602, the first interconnect layer 66 formed in step S603, and the electrode layer provided in step S604 may have thickness differences.

[0143] Figure 22 is a schematic diagram comparing the heights of multiple semi-finished substrates according to some embodiments. Please refer to Figure 22. In this embodiment, the first diode substrate 601', the second diode substrate 602', and the third diode substrate 603' correspond to the semi-finished substrates in step S604 (refer to Figure 20D; the first connecting layer 66 is not shown in Figure 22). When the first diode substrate 601', the second diode substrate 602', and the third diode substrate 603' are placed on the same horizontal plane, the third reference line BL3 represents the height of the horizontal plane, and the fourth reference line BL4 represents the height of the upper surface of the diode substrate with the lowest height, such as the height of the upper surface of the bottom electrode 643 of the third diode substrate 603' in Figure 22. In this embodiment, the first diode substrate 601' has a height H61, and its bottom electrode 641 has a thickness D61; the second diode substrate 602' has a height H62, and its bottom electrode 642 has a thickness D62; the third diode substrate 603' has a height H63, and its bottom electrode 643 has a thickness D63. The thickness D61 is greater than the thickness D62, and the thickness D62 is greater than the thickness D63; the height H61 is greater than the height H62, and the height H62 is greater than the height H63. The main reason for this is that the bottom electrode 641 of the first diode substrate 601' has a larger thickness D61 due to process variations, while the epitaxial layer 633 of the third diode substrate 603' has a smaller thickness due to process variations.

[0144] Figure 23 is a flowchart of a method for manufacturing diode chips according to some other embodiments; Figures 24A to 24B are schematic diagrams of a method for manufacturing diode chips according to some other embodiments. Please refer to Figures 24A to 24B sequentially based on Figure 23. In this embodiment, step S605 of the manufacturing method further includes steps S6051 to S6054. In step S6051, the manufacturing method measures the height of multiple semi-finished substrates to obtain the heights H61, H62, and H63 of each diode substrate. For example, the first substrate 61 (i.e., first substrates 611, 612, 613) of each diode substrate are placed on the same third reference line BL3, and a laser thickness gauge measures the upper surface of the bottom electrode 64 of each diode substrate to obtain the height of the diode substrate.

[0145] Subsequently, the manufacturing method includes comparing the heights of each semi-finished substrate (step S6052) to obtain a minimum height value (step S6053). As shown in FIG24A, the manufacturing method determines that the third diode substrate 603' has the minimum height; therefore, the fourth reference line BL4 is disposed on the top surface of the bottom electrode 643 of the third diode substrate 603'. In some embodiments, the minimum height value refers to the height value of the semi-finished diode substrate with the lowest height among the plurality of semi-finished diode substrates expected to be placed in the same panel structure 600. The manufacturing method includes grinding the electrode layers of each semi-finished substrate to achieve the minimum height value (step S6054). In this embodiment, the top surfaces of both the first diode substrate 601' and the second diode substrate 602' exceed the fourth reference line BL4; therefore, the manufacturing method grinds both to grind the height H61 to the value of height H63, and the height H62 is also ground to the value of height H63. As shown in Figure 24B, after step S6054, the values ​​of height H61, height H62 and height H63 are essentially the same. Each bottom electrode 64 is ground so that the thickness D61 is greater than the thickness D63, and the thickness D63 is greater than the thickness D62.

[0146] In some embodiments, "substantially identical" may refer to sampling multiple sets of samples from the plurality of diode grains 60 formed on each diode substrate, wherein the height of the diode grains 60 in each set of samples does not differ significantly (e.g., based on a 5% significance level). In other embodiments, "substantially identical" may refer to the allowable variation in height between the various diode substrates (diode grains 60) being within the accuracy range of the polishing machine G6. In other embodiments, "substantially identical" may refer to the allowable variation in height between the various diode substrates (diode grains 60) being less than the allowable variation in thickness between the bottom electrodes 64 of the various diode substrates (diode grains 60). For example, in this embodiment, if the thickness D61 is 100 μm and the thickness D62 is 80 μm, then the variation ratio between the thickness D61 and the thickness D62 is (100-80) / 80, i.e., 25%. Therefore, when the height variation ratio between each diode substrate (diode grain 60) is less than 25%, they can be considered substantially the same. It should be understood that the variation ratio illustrated in this embodiment is merely an example value for illustrative purposes, and the actual height variation ratio should be defined based on the actual thickness variation ratio.

[0147] Based on the above, in step S6052, the manufacturing method includes comparing the height of one substrate (first height) with the height of another substrate (second height). In some embodiments, the manufacturing method includes not performing the step of grinding the bottom electrode layer until the first height decreases to the second height when it is determined that the second height is less than a certain lower limit height. For example, as shown in FIG24A, when the value of height H63 is less than the lower limit height but the value of height H62 is greater than the lower limit height, the grinding machine G6 does not perform the grinding of the height H61 of the first diode substrate 601' to the value of height H63, nor does it perform the grinding of the height H62 of the second diode substrate 602' to the value of height H63. However, the grinding machine G6 may perform the grinding of the height H61 of the first diode substrate 601' to the value of height H62. The lower limit height can be defined according to process requirements. For example, the lower limit height can be the sum of the dimensional specifications of the first substrate 61 and the epitaxial layer 63 in the semi-finished substrate, such as the sum of the upper limits of the acceptable thickness range, to prevent the bottom electrode 64 from being completely ground away. As another example, the lower limit height can be a value within the acceptable thickness range required for pre-aligning the diode die 60, such as the minimum acceptable thickness value, to allow the pre-aligning process to be performed on the diode die 60 produced from the diode substrate.

[0148] FIG25 is a schematic diagram of a panel structure according to some embodiments. Please refer to FIG25. A first diode substrate 601' is processed into a first diode die 601 through the steps of FIG23, a second diode substrate 602' is processed into a second diode die 602 through the steps of FIG23, and a third diode substrate 603' is processed into a third diode die 603 through the steps of FIG23. In some embodiments, the manufacturing method includes transferring the first diode die 601, the second diode die 602, and the third diode die 603 to a third substrate 69 to form a panel structure 600. Accordingly, in this embodiment, the panel structure 600 includes a first diode die 601, a second diode die 602, and a third diode die 603, and the plurality of diode dies 60 on the panel structure 600 have substantially the same height. As shown in Figure 25, the first reference line BL1 is disposed on the upper surface of the panel structure 600, and the second reference line BL2 is disposed on the upper surface of the top electrode 62 of the diode grain 60. The first diode grain 601, the second diode grain 602, and the third diode grain 603 have substantially the same height; however, the thickness D61 of the bottom electrode 64 of each diode grain 60 is greater than the thickness D63, and the thickness D63 is greater than the thickness D62.

[0149] In some embodiments, the panel structure 600 includes multiple pixel structures. For example, the first diode die 601, the second diode die 602, and the third diode die 603 shown in FIG. 25 are located in the same pixel structure, corresponding to red light, green light, and blue light, respectively. The manufacturing method includes transferring multiple first diode dies 601 generated by processing the first diode substrate 601' to various pixel structures on the panel structure 600, transferring multiple second diode dies 602 generated by processing the second diode substrate 602' to various pixel structures on the panel structure 600, and transferring multiple third diode dies 603 generated by processing the third diode substrate 603' to various pixel structures on the panel structure 600. Accordingly, the thickness of the bottom electrode 64 of the same type of diode die 60 within each pixel structure is substantially the same. For example, the bottom electrode 641 of the first diode 601 within each pixel structure has a thickness D61, the bottom electrode 642 of the second diode 602 has a thickness D62, and the bottom electrode 643 of the third diode 603 has a thickness D63, and the height of each diode 60 is substantially the same.

[0150] Referring again to FIG1, in some embodiments, the pixel structure 50 includes a substrate 500, a plurality of vertical diode dies 520, flip-chip diode dies 530, and an upper wiring layer 540. In some embodiments, the vertical diode dies 520 or flip-chip diode dies 530 may face the problem of thickness difference between diode dies due to variations in production equipment or manufacturing technology during application. Although this thickness difference problem can be overcome by filling the gaps between diode dies with filler material to fix the diode dies, existing filling technology still has the problem of poor flatness of filler material, which causes open circuits between components and causes the micro-light-emitting diode to fail to emit light normally. In some embodiments, the vertical micro-light-emitting diode structure, vertical micro-light-emitting diode unit, and manufacturing method thereof of the following embodiments can be used to implement or apply to the pixel structure 50. However, this disclosure is not limited thereto. Under different design considerations or application scenarios, other structures, processes, or manufacturing processes can be used to implement the pixel structure 50 disclosed in this disclosure.

[0151] Please refer to Figures 26 to 31. Figure 26 shows the vertical diode die 520 disposed within the receiving site 551 in Figure 1. To facilitate the explanation of the connection relationship between the vertical diode die 520 and its surrounding components, the upper wiring layer 540 is magnified and represented as the first circuit layer 311, and the lower wiring layer 510 is magnified and represented as the second circuit layer 321. In this embodiment, a vertical micro-light-emitting diode unit 30 includes a first backplate 31 and a second backplate 32. As shown in Figure 27, the first backplate 31 includes a first substrate 310, a first circuit layer 311, a first contact pad 312, and a transparent electrode layer 313. The first circuit layer 311 is disposed on the first substrate 310. The first contact pad 312 is disposed on the first circuit layer 311. The transparent electrode layer 313 is disposed on the first circuit layer 311 and the first contact pad 312.

[0152] As shown in Figure 28, the second backplate 32 includes a second substrate 320, a second circuit layer 321, a eutectic metal layer 322, an alloy layer 323, a micro-light-emitting diode (LED) die 324, a second contact pad 325, and an isolation layer 326. The second circuit layer 321 is disposed on the second substrate 320. The eutectic metal layer 322 is disposed on the second circuit layer 321. The alloy layer 323 is disposed on the eutectic metal layer 322. The micro-light-emitting diode (LED) die 324 is disposed on the alloy layer 323. The second contact pad 325 is disposed on the micro-light-emitting diode (LED) die 324. The isolation layer 326 is disposed on the second substrate 320 to surround the micro-light-emitting diode (LED) die 324. In other words, in some embodiments, the thickness L2 of the isolation layer 326 is greater than the sum of the thickness of the second circuit layer 321, the thickness of the eutectic metal layer 322, the thickness of the alloy layer 323, and the thickness of the micro-light-emitting diode grain 324, so that the isolation layer 326 can surround the micro-light-emitting diode grain 324.

[0153] As shown in Figures 26 and 29, the transparent electrode layer 313 of the first backplate 31 faces the second contact pad 325 and the isolation layer 326 of the second backplate 32 and is disposed on the second backplate 32, and a chamber 327 is formed between the first backplate 31 and the second backplate 32. In some embodiments, the chamber 327 is in a vacuum state to avoid the generation of water vapor in the vertical micro-light-emitting diode unit 30, thereby preventing water vapor from causing short circuits and damage between the components in the vertical micro-light-emitting diode unit 30. In addition, in other embodiments, the chamber 327 may also be filled with an inert gas to achieve the same protective effect.

[0154] In some embodiments, the projected areas of the first contact pad 312 and the second contact pad 325 along the normal direction of the first back plate 31 at least partially overlap, and the transparent electrode layer 313 connects the second contact pad 325 and the insulating layer 326. Taking Figures 29 to 31 as an example, in this embodiment, the first contact pad 312 and the second contact pad 325 are coaxial with axis A1 (as shown in Figure 29), such that the projected areas of the first contact pad 312 and the second contact pad 325 along axis A1 overlap (as shown in Figures 30 and 31).

[0155] In some embodiments, when the first backplate 31 is disposed on the second backplate 32, the insulating layer 326 is deformed such that the thickness L1 of the deformed insulating layer 326 is equal to the sum of the thickness of the first contact pad 312, the thickness of the second circuit layer 321, the thickness of the eutectic metal layer 322, the thickness of the alloy layer 323, the thickness of the micro-light-emitting diode grain 324, and the thickness of the second contact pad 325. In other words, in some embodiments, the thickness L2 of the insulating layer 326 before deformation (as shown in FIG. 28) is greater than the thickness L1 of the insulating layer 326 after deformation (as shown in FIG. 26).

[0156] As shown in Figures 30 and 31, in some embodiments, the area of ​​the first contact pad 312 is smaller than the area of ​​the first circuit layer 311, the area of ​​the first circuit layer 311 is smaller than the area of ​​the micro-LED chip 324, and the area of ​​the second contact pad 325 is smaller than the area of ​​the micro-LED chip 324. Since the first circuit layer 311, the first contact pad 312, and the second contact pad 325 are all opaque, the areas of the first circuit layer 311, the first contact pad 312, and the second contact pad 325 must all be smaller than the area of ​​the micro-LED chip 324 to avoid obscuring the light emission of the micro-LED chip 324. Furthermore, in some embodiments, the projected areas of the first circuit layer 311 and the isolation layer 326 along the normal direction of the first backplate 31 at least partially overlap. In other words, since a portion of the first circuit layer 311 is disposed on the isolation layer 326, the first circuit layer 311 will not completely obscure the light emission of the micro-LED chip 324.

[0157] Please refer to Figures 26 to 32. The manufacturing process and steps of the vertical micro-light-emitting diode unit 30 will be described below using Figures 26 to 31 as an example. As shown in Figure 32, when the manufacturing of the vertical micro-light-emitting diode unit 30 begins, the first backplate 31 and the second backplate 32 are formed separately (steps S30 and S31). It should be noted that the order between step S30, which forms the first backplate 31, and step S31, which forms the second backplate 32, can be interchanged. In other words, the vertical micro-light-emitting diode unit 30 can form the first backplate 31 first and then the second backplate 32 (as shown in Figure 32), or it can form the second backplate 32 first and then the first backplate 31.

[0158] As shown in FIG27, in step S30 of forming the first backplane 31, the first circuit layer 311 is first disposed on the first substrate 310 (step S300). In some embodiments, the material of the first substrate 310 is a light-transmitting insulating material, such as, but not limited to, glass, silicone, epoxy resin, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene phthalate (PET), and polyetherimide. In some embodiments, the first circuit layer 311 can be disposed on the first substrate 310 by deposition techniques, wherein the deposition techniques are, but are not limited to, sputtering, electron beam evaporation, chemical vapor deposition (CVD), physical vapor deposition (PVD), area selective deposition (ASD), and atomic layer deposition (ALD).

[0159] After step S300, the first contact pad 312 is disposed on the first circuit layer 311 (step S301), and then the transparent electrode layer 313 is disposed on the first circuit layer 311 and the first contact pad 312 (step S302). Here, the first circuit layer 311, the first contact pad 312, and the transparent electrode layer 313 are electrically connected to each other. In some embodiments, the first contact pad 312 can be disposed on the first circuit layer 311 by screen printing technology, wherein the material of the first contact pad 312 is a conductive material, such as, but not limited to, gold, copper, and aluminum. In some embodiments, the transparent electrode layer 313 can be a transparent conductive film, such as, but not limited to, indium tin oxide (ITO), tin oxide (SnO2), antimony tin oxide (ATO), conductive polymer (PEDOT), carbon nanotubes (CNTs), silver nanowires, and graphene.

[0160] As shown in FIG28, in step S31 of forming the second backplane 32, the second circuit layer 321 is first disposed on the second substrate 320 (step S310). In some embodiments, the material of the second substrate 320 may be an opaque insulating material, such as, but not limited to, silicon (Si), silicon dioxide (SiO2), gallium arsenide (GaAs), and silicon carbide (SiC). In other embodiments, the material of the second substrate 320 may be the aforementioned light-transmitting insulating material.

[0161] After step S310, the micro-light-emitting diode (LED) chip 324 is disposed on the second circuit layer 321 (step S311), and then the second contact pad 325 is disposed on the LED chip 324 (step S312). Here, the second circuit layer 321, the LED chip 324, and the second contact pad 325 are electrically connected to each other. In some embodiments, the second contact pad 325 can be disposed on the second circuit layer 321 by screen printing technology, wherein the material of the second contact pad 325 is a conductive material, such as, but not limited to, gold, copper, and aluminum.

[0162] After step S312, an isolation layer 326 is disposed on the second substrate 320 to surround the micro-light-emitting diode (LED) grain 324 (step S313), wherein the isolation layer 326 can be disposed on the second substrate 320 by the aforementioned deposition technique. Finally, the transparent electrode layer 313 of the first backplate 31 is disposed on the second backplate 32 facing the second contact pad 325 and the isolation layer 326 (step S32) to complete the fabrication of the vertical LED unit 30. At this time, a cavity 327 is formed between the first backplate 31 and the second backplate 32, and the projected areas of the first contact pad 312 and the second contact pad 325 along the normal direction of the first backplate 31 at least partially overlap. The transparent electrode layer 313 connects to the second contact pad 325, such that the first circuit layer 311 is electrically connected to the second circuit layer 321. Therefore, the first circuit layer 311 and the second circuit layer 321 can be used as the two electrodes (including the P electrode and the N electrode) of the vertical micro-light-emitting diode unit 30.

[0163] Please refer to Figures 26 and 33. As shown in Figure 26, in some embodiments, the isolation layer 326 includes an opaque material 326A (as shown in Figure 26). In other embodiments, the isolation layer 326 includes an opaque material 326A and a transparent material 326B (as shown in Figure 33). In some embodiments, the isolation layer 326 is used to prevent the light emitted by the micro-LED grains 324 from interfering with the light emitted by the micro-LED grains 324 adjacent to them. Therefore, the opaque material 326A only needs to surround the micro-LED grains 324. In some embodiments, the opaque material 326A can be a black matrix (BM) material or a light-reflective material, such as, but not limited to, alumina, dielectric multilayer films, and reflective resin materials. In some embodiments, the light-transmitting material 326B is, for example, but not limited to, silicone, epoxy resin, polyimide, benzocyclobutene, perfluorocyclobutane, SU8 photoresist, acrylic resin, polyethylene phthalate, and polyetherimide. It should be noted that, because the insulating layer 326 is malleable, the opaque material 326A in the insulating layer 326 is only used to make the insulating layer 326 opaque without affecting the malleability of the insulating layer 326.

[0164] In some embodiments, the micro-light-emitting diode (LED) chips 324 are disposed on the second circuit layer 321 using mass transfer technology. It should be noted that when the micro-light-emitting diode (LED) chips 324 are disposed on the second circuit layer 321 via mass transfer, a eutectic metal layer 322 and an alloy layer 323 (as shown in Figures 26, 28, and 29) must first be disposed on the second circuit layer 321 as carriers for the mass transfer of the LED chips 324, so that the LED chips 324 can be disposed on the second circuit layer 321 and electrically connected thereto. The eutectic metal layer 322 is used to pre-align the LED chips 324 to their placement positions, and the alloy layer 323 is used to bond the LED chips 324. In some embodiments, the alloy layer 323 is trapezoidal in shape, wherein the upper base of the trapezoid is connected to the eutectic metal layer 322, and the lower base of the trapezoid is connected to the micro-light-emitting diode (LED) grain 324. In other words, the longer of the two parallel base sides of the trapezoid is connected to the LED grain 324.

[0165] Referring to Figures 34 and 35, in some embodiments, multiple vertical micro-light-emitting diode units 30 can constitute a vertical micro-light-emitting diode structure 3. Taking Figure 34 as an example, in this embodiment, the vertical micro-light-emitting diode structure 3 includes three vertical micro-light-emitting diode units 30 (for ease of explanation, they are referred to as the first micro-light-emitting diode unit 30R, the second micro-light-emitting diode unit 30G, and the third micro-light-emitting diode unit 30B, respectively). Among them, the micro-light-emitting diode grain 324R of the first micro-light-emitting diode unit 30R is a red micro-light-emitting diode grain, the micro-light-emitting diode grain 324G of the second micro-light-emitting diode unit 30G is a green micro-light-emitting diode grain, and the micro-light-emitting diode grain 324B of the third micro-light-emitting diode unit 30B is a blue micro-light-emitting diode grain.

[0166] In some embodiments, the first contact pads 312R, 312G, and 312B respectively have at least partial overlaps with the projected areas of the second contact pads 325R, 325G, and 325B along the normal direction of the first back plate 31, and each transparent electrode layer 313R, 313G, and 313B is connected to the corresponding second contact pads 325R, 325G, 325B and the isolation layer 326. Taking Figures 37 to 39 as examples, in this embodiment, the first contact pad 312R and the second contact pad 325R are coaxial with axis A1 (as shown in Figure 37), so that the projected areas of the first contact pad 312R and the second contact pad 325R along axis A1 overlap (as shown in Figures 38 and 39); the first contact pad 312G and the second contact pad 325G are coaxial with axis A2 (as shown in Figure 37), so that the projected areas of the first contact pad 312G and the second contact pad 325G along axis A2 overlap (as shown in Figures 38 and 39); the first contact pad 312B and the second contact pad 325B are coaxial with axis A3 (as shown in Figure 37), so that the projected areas of the first contact pad 312B and the second contact pad 325B along axis A3 overlap (as shown in Figures 38 and 39).

[0167] In some embodiments, the vertical micro-light-emitting diode structure 3 can be applied in a micro-light-emitting diode display device. The vertical micro-light-emitting diode structure 3 constitutes a pixel in the micro-light-emitting diode display device, and the first micro-light-emitting diode unit 30R, the second micro-light-emitting diode unit 30G, and the third micro-light-emitting diode unit 30B are each a sub-pixel. In some embodiments, any one of the first micro-light-emitting diode unit 30R, the second micro-light-emitting diode unit 30G, and the third micro-light-emitting diode unit 30B is adjacent to at least one of the other two. In other words, each sub-pixel in a single pixel of the micro-light-emitting diode display device is adjacent to at least one of the other two sub-pixels. If two adjacent sub-pixels belong to different pixels, they are not considered "adjacent" as described herein.

[0168] Please refer to Figures 26 to 31 and Figures 34 to 40. The manufacturing process and steps of the vertical micro-light-emitting diode structure 3 will be described below using Figures 26 to 31 and Figures 34 to 39 as examples. As shown in Figure 40, when the manufacturing of the vertical micro-light-emitting diode structure 3 begins, the first backplate 31 and the second backplate 32 are formed separately (steps S33 and S34). It should be noted that the order between step S33, which forms the first backplate 31, and step S34, which forms the second backplate 32, can be interchanged. In other words, the vertical micro-light-emitting diode structure 3 can be formed by first forming the first backplate 31 and then forming the second backplate 32 (as shown in Figure 40), or it can be formed by first forming the second backplate 32 and then forming the first backplate 31.

[0169] As shown in Figure 35, in step S33 of forming the first backplate 31, a plurality of first circuit layers 311 are first disposed on the first substrate 310 (step S330). In other words, the first circuit layers 311R, 311G, and 311B of each of the vertical micro-light-emitting diode units 30R, 30G, and 30B are disposed on the same first substrate 310. It should be noted that the first circuit layers 311R, 311G, and 311B are disposed adjacent to each other on the first substrate 310, and the first circuit layers 311R, 311G, and 311B are not electrically connected to each other.

[0170] After step S330, a plurality of first contact pads 312R, 312G, and 312B are disposed on the corresponding plurality of first circuit layers 311R, 311G, and 311B (step S331). Subsequently, a plurality of transparent electrode layers 313R, 313G, and 313B are disposed on the corresponding plurality of first circuit layers 311 and the plurality of first contact pads 312R, 312G, and 312B (step S332). A gap is left between each of the plurality of first contact pads 312R, 312G, and 312B, and a gap is also left between each of the plurality of transparent electrode layers 313R, 313G, and 313B (as shown in Figure 35). Herein, the first circuit layer 311R, the first contact pad 312R and the transparent electrode layer 313R are electrically connected to each other, the first circuit layer 311G, the first contact pad 312G and the transparent electrode layer 313G are electrically connected to each other, and the first circuit layer 311B, the first contact pad 312B and the transparent electrode layer 313B are electrically connected to each other.

[0171] As shown in FIG36, in step S34 of forming the second backplate 32, a plurality of second circuit layers 321R, 321G, and 321B are first disposed on the second substrate 320 (step S340). Similar to the first backplate 31, the second circuit layers 321R, 321G, and 321B of the vertical micro-light-emitting diode units 30R, 30G, and 30B are disposed on the same second substrate 320, and a gap is left between the plurality of second circuit layers 321R, 321G, and 321B.

[0172] After step S340, red LED dies 324R, green LED dies 324G, and blue LED dies 324B are disposed on corresponding second circuit layers 321R, 321G, and 321B (step S341). Subsequently, multiple second contact pads 325R, 325G, and 325B are disposed on the red LED dies 324R, green LED dies 324G, and blue LED dies 324B respectively (step S342), wherein each second contact pad 325R, 325G, and 325B corresponds to each first contact pad 312R, 312G, and 312B respectively. Here, the LED dies 324 are electrically connected to the second circuit layer 321 and the second contact pads 325.

[0173] After step S342, an isolation layer 326 is disposed on the second substrate 320 to surround the red micro-light-emitting diode (LED) chip 324R, the green LED chip 324G, and the blue LED chip 324B (step S343). Finally, the plurality of transparent electrode layers 313R, 313G, and 313B of the first backplate 31 are disposed on the second backplate 32 facing the plurality of second contact pads 325R, 325G, 325B, and the isolation layer 326 (step S35) to complete the fabrication of the vertical LED structure 3. At this time, a plurality of chambers 327 are formed between the first backplate 31 and the second backplate 32, and the projected areas of each first contact pad 312R, 312G, 312B and each second contact pad 325R, 325G, 325B along the normal direction of the first backplate 31 at least partially overlap. In this configuration, each transparent electrode layer 313R, 313G, and 313B is connected to a corresponding second contact pad 325R, 325G, and 325B, such that each first circuit layer 311R, 311G, and 311B is electrically connected to a corresponding second circuit layer 321R, 321G, and 321B. Thus, the paired first circuit layer 311 and second circuit layer 321 can each be used as a two-electrode (including a P-pole and a N-pole) of the vertical micro-light-emitting diode unit 30R, 30G, and 30B.

[0174] It should be noted that the thickness of the red LED chip 324R is greater than the thickness of the green LED chip 324G and the blue LED chip 324B, and the thickness of the green LED chip 324G is approximately equal to the thickness of the blue LED chip 324B. Therefore, in some embodiments, the thickness of the first contact pad 312G and the first contact pad 312B is greater than the thickness of the first contact pad 312R, so that the first backplate 31 can be stably disposed on the second backplate 32.

[0175] Similar to the manufacturing process of the vertical micro-light-emitting diode unit 30, in some embodiments, the micro-light-emitting diode dies 324R, 324G, and 324B are respectively disposed on the second circuit layer 321 by mass transfer technology. Furthermore, when the micro-light-emitting diode (LED) chips 324R, 324G, and 324B are mass-transferred to the corresponding second circuit layers 321R, 321G, and 321B, a eutectic metal layer 322 and an alloy layer 323 (as shown in Figures 34, 36, and 37) must first be provided on the second circuit layers 321R, 324G, and 321B to serve as carriers for the mass transfer of each LED chip 324R, 324G, and 324B. Only then can the LED chips 324R, 324G, and 324B be disposed on the corresponding second circuit layers 321R, 321G, and 321B and electrically connected to them.

[0176] According to any embodiment, using a dual-backplane structure (i.e., a first backplane and a second backplane) to assemble and manufacture micro-light-emitting diodes can avoid various problems caused by current filling techniques. Furthermore, by adjusting the contact pad thickness according to the grain thickness of the micro-light-emitting diodes of different emission colors, the contact pads on the top surface of each micro-light-emitting diode unit are located as close to the same plane as possible. This also prevents the micro-light-emitting diodes from having open circuits, thereby improving the yield and reliability of the micro-light-emitting diodes during manufacturing.

[0177] Referring again to FIG1, in some embodiments, the pixel structure 50 includes a substrate 500, a plurality of vertical diode chips 520, flip-chip diode chips 530, and an upper wiring layer 540. In some embodiments, the pixel structure 50 may face the problem that mass transfer technology cannot accurately and effectively move a large number of vertical diode chips 520 or flip-chip diode chips 530, causing a bottleneck in the panel structure manufacturing process. Referring also to FIG21, in some embodiments, the vertical diode chips 520 can adopt a structure like diode chip 60, which includes a top electrode 62, an epitaxial layer 63, a bottom electrode 64, and a conductor layer 68. The bottom electrode 64 can be a trapezoidal structure to facilitate the pre-alignment of the diode chips 60 before transfer, so that a large number of diode chips 60 can be effectively transferred. In some embodiments, the pre-alignment apparatus and pre-alignment method described below can be applied to the transfer of the vertical diode die 520 or the flip-chip diode die 530. However, this disclosure is not limited thereto. Under different design considerations or application scenarios, other structures, processes or fabrication methods may be used to process the vertical diode die 520 or the flip-chip diode die 530 disclosed herein.

[0178] Referring to Figures 41 and 42, a pre-alignment device 2 includes a vibrator 20, an alignment tray 21, multiple electromagnets 22, and a controller 23. The vibrator 20 includes multiple sidewalls 201 and a base plate 202, with the sidewalls 201 disposed around the base plate 202 (as shown in Figure 42). The alignment tray 21 is disposed on the base plate 202 and includes multiple grooves 210 arranged in an array, with each groove 210 having a through hole 211 at its bottom. Taking Figure 42 as an example, in this embodiment, the alignment tray 21 includes 36 grooves 210 arranged in an array of 6 rows and 6 columns.

[0179] Each electromagnet 22 is disposed in each through hole 211, and each electromagnet 22 is used to generate a magnetic field along the extension direction of the through hole 211. Taking FIG41 as an example, in this embodiment, the extension direction of the through hole 211 is the Y direction. Here, each electromagnet 22 generates a magnetic field along the Y direction. The controller 23 is electrically connected to the plurality of electromagnets 22, and the controller 23 is used to control each electromagnet 22 to generate a magnetic field. In other words, in some embodiments, each electromagnet 22 can be controlled independently. Therefore, when the controller 23 controls all the electromagnets 22 to be energized to generate a magnetic field, the magnitude of the magnetic field generated by each electromagnet 22 is the same, so that each through hole 211 in the entire array 21 has a magnetic field of the same magnitude.

[0180] In some embodiments, the electromagnet 22 is a coil of wire comprising at least one turn. Furthermore, in this embodiment, the electromagnet 22 further comprises a columnar body (e.g., but not limited to, a cylinder, triangular prism, square prism, or polygonal prism) of a magnetically conductive material, and at least one coil of wire in the electromagnet 22 is wrapped around this columnar body to magnetize it, thereby enhancing the strength of the magnetic field generated by the electromagnet 22. The magnetically conductive material of this columnar body is, for example, but not limited to, iron (Fe), cobalt (Co), nickel (Ni), chromium (Cr), molybdenum (Mo), and alloys comprising at least two of the above materials.

[0181] In some embodiments, the controller 23 may be a circuit module integrated into the vibratory machine 20 and having control functions. Taking FIG41 as an example, in this embodiment, the controller 23 is a circuit layer and is disposed in the base plate 202 of the vibratory machine 20. In other embodiments, the controller 23 may also be a hardware component (not shown) independent of the pre-alignment device 2 and having control functions, such as, but not limited to, a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a microcontroller unit (MCU).

[0182] Please refer to Figures 41 to 46, where Figures 45 and 46 are enlarged schematic diagrams of a single groove 210 in the dashed box R21 and the dashed box R22 in Figure 44, respectively. The following description uses the pre-alignment device 2 shown in Figure 41 as an example to illustrate the pre-alignment method for multiple micro-light-emitting diode units 24, but this is not intended to limit the device, hardware, or software components that perform the pre-alignment method. When the pre-alignment device 2 begins to pre-align multiple micro-light-emitting diode units 24, the user can place the multiple micro-light-emitting diode units 24 on the alignment tray 21 of the pre-alignment device 2 (step S20). Taking Figure 44 as an example, in this embodiment, the multiple scattered micro-light-emitting diode units 24 are arbitrarily placed on the alignment tray 21.

[0183] After step S20, the pre-alignment device 2 generates an attractive force F21 along the extension direction of each through hole 211 (step S21), and the pre-alignment device 2 generates a vibration force F22 through the vibrator 20 to cause the alignment tray 21 to vibrate (step S22). In some embodiments, when the alignment tray 21 begins to vibrate, each micro-light-emitting diode unit 24 vibrates and moves into each groove 210 of the alignment tray 21. As shown in FIG45 or FIG46, in this embodiment, since the pre-alignment device 2 generates an attractive force F21 along the extension direction of each through hole 211, the direction of force application of the attractive force F21 is parallel to the Y direction. In addition, the direction of force application of the vibration force F22 generated by the vibrator 20 is also parallel to the Y direction, and the direction of force application of the vibration force F22 is opposite to the direction of force application of the attractive force F21. Therefore, in some embodiments, the attractive force F21 generated by the pre-alignment device 2 and the vibration force F22 generated by the vibrator 20 can cancel each other out. Specifically, when the attractive force F21 is greater than the vibration force F22, the vibration force F22 is eliminated, leaving only the attractive force F21; when the attractive force F21 is less than the vibration force F22, the attractive force F21 is eliminated, leaving only the vibration force F22.

[0184] In some embodiments, when the attractive force F21 is greater than the vibration force F22 (as shown in FIG45), the micro-light-emitting diode unit 24 that has moved into the groove 210 is fixed in each groove 210 by the attractive force F21. In other embodiments, when the attractive force F21 is less than the vibration force F22 (as shown in FIG46), the micro-light-emitting diode unit 24 that has moved into the groove 210 is dislodged from each groove 210 by the vibration force F22. Thus, through the interaction between the attractive force F21 and the vibration force F22, each micro-light-emitting diode unit 24 can gradually move into each groove 210 to be arranged into another array, wherein the other array corresponds to the array formed by the arrangement of multiple grooves 210. Taking FIG42 as an example, in this embodiment, since the aligning disk 21 shown in FIG42 contains 36 grooves 210, the pre-aligning device 2 shown in FIG42 can arrange 36 micro-light-emitting diode units in a neat and orderly manner on the same surface through the pre-aligning method.

[0185] In some embodiments, the thickness of the alignment tray 21 is less than the height of each sidewall 201. Therefore, when the alignment tray 21 begins to vibrate, even if the attractive force F21 on the micro-light-emitting diode unit 24 is less than the vibration force F22, the micro-light-emitting diode unit 24 can be blocked by the sidewalls 201 around the vibrating machine 20 and will not be disengaged from the pre-alignment device 2 by the vibration force F22.

[0186] In some embodiments, the attractive force F21 generated by the pre-alignment device 2 in step S22 is a magnetic attraction or a vacuum attraction. Taking Figures 45 and 46 as examples, in this embodiment, the attractive force F21 generated by the pre-alignment device 2 is a magnetic attraction. Here, the pre-alignment device 2 includes a physical element for generating a magnetic field, such as, but not limited to, an electromagnet 22. Furthermore, in this embodiment, each micro-light-emitting diode unit 24 needs to be magnetically permeable so that the magnetic field generated by the electromagnet 22 can generate a magnetic attraction force (i.e., attractive force F21) on each micro-light-emitting diode unit 24. Therefore, in some embodiments, each micro-light-emitting diode unit 24 includes a micro-light-emitting diode grain 241, a carrier layer 242, and a magnetically permeable layer 243 (as shown in Figures 45 and 46).

[0187] In some embodiments, the carrier layer 242 is disposed on the magnetically conductive layer 243, and the micro-light-emitting diode (LED) grain 241 is disposed on the carrier layer 242. Both the carrier layer 242 and the magnetically conductive layer 243 are trapezoidal in shape, and the width of the bottom of the magnetically conductive layer 243 is smaller than the width of the bottom of each groove 210. Taking FIG45 as an example, in this embodiment, the micro-light-emitting diode (LED) grain 241 is disposed on the upper bottom of the carrier layer 242, and the carrier layer 242 is disposed on the upper bottom of the magnetically conductive layer 243. The width of the lower bottom of the carrier layer 242 is equal to the width of the upper bottom of the magnetically conductive layer 243, and the width of the lower bottom of the magnetically conductive layer 243 is smaller than the width of the bottom of each groove 210.

[0188] In some embodiments, the material of the carrier layer 242 is conductive and non-magnetic, such as, but not limited to, aluminum (Al), copper (Cu) and their alloys. In some embodiments, the material of the magnetic layer 243 is magnetic, such as, but not limited to, iron, cobalt, nickel, chromium, molybdenum and alloys containing at least two of the above materials.

[0189] In some embodiments, the material of the alignment tray 21 is a non-magnetic insulating material, such as, but not limited to, glass, silicone, epoxy, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene phthalate (PET), polyetherimide, silicon (Si), silicon dioxide (SiO2), gallium arsenide (GaAs), and silicon carbide (SiC). Here, the pre-alignment device 2 ensures that the magnetic force generated by each electromagnet 22 does not affect the alignment tray 21.

[0190] In some embodiments, when each micro-light-emitting diode unit 24 moves into each groove 210, the orientation of each micro-light-emitting diode unit 24 determines the magnitude of the attractive force F21. Taking FIG45 as an example, in this embodiment, the micro-light-emitting diode unit 24 is disposed in the groove 210 with the micro-light-emitting diode grain 241 facing upward. At this time, the magnetically conductive layer 243 directly contacts the bottom of the groove 210; taking FIG46 as another example, in this embodiment, the micro-light-emitting diode unit 24 is disposed in the groove 210 with the magnetically conductive layer 243 facing upward. At this time, the non-magnetically conductive micro-light-emitting diode grain 241 directly contacts the bottom of the groove 210.

[0191] In some embodiments, since the distance between the magnetically conductive layer 243 and the electromagnet 22 in the micro-LED unit 24 shown in FIG45 is smaller than the distance between the magnetically conductive layer 243 and the electromagnet 22 in the micro-LED unit 24 shown in FIG46, the attractive force F21 (i.e., magnetic attraction) experienced by the micro-LED unit 24 shown in FIG45 is greater than that experienced by the micro-LED unit 24 shown in FIG46. Therefore, in some embodiments, the user can adjust the value of the vibration force F22 generated by the vibrator 20 in the pre-alignment device 2 to be between the value of the attractive force F21 shown in FIG45 and the value of the attractive force F21 shown in FIG46, so that the micro-LED unit 24 experiences different forces when it moves into the groove 210 in different orientations.

[0192] Taking Figure 45 as an example, in this embodiment, when the micro-light-emitting diode unit 24 is disposed in the groove 210 with the micro-light-emitting diode grain 241 facing upward, the attractive force F21 received by the micro-light-emitting diode unit 24 is greater than the vibration force F22, so that the micro-light-emitting diode unit 24 is fixed in each groove 210 by the attractive force F21. Taking Figure 46 as an example, in this embodiment, when the micro-light-emitting diode unit 24 is disposed in the groove 210 with the magnetic conductive layer 243 facing upward, the attractive force F21 received by the micro-light-emitting diode unit 24 is less than the vibration force F22, so that the micro-light-emitting diode unit 24 is detached from the groove 210 by the vibration force F22. Therefore, when the pre-alignment device 2 completes the pre-alignment of multiple micro-light-emitting diode units 24, it means that all micro-light-emitting diode units 24 are fixed in the groove 210 with the micro-light-emitting diode grains 241 facing upwards, so that all micro-light-emitting diode units 24 are facing upwards.

[0193] In some embodiments, after step S22, when all micro-LED units 24 are fixed in their respective grooves 210, it indicates that the pre-alignment device 2 has pre-aligned all the micro-LED units 24. At this time, the pre-alignment device 2 first stops generating the vibration force F22 (step S23) so that the micro-LED units 24 are fixed in the grooves 210 only by the attraction force F21, thereby preventing the micro-LED units 24 from detaching from the grooves 210. Subsequently, the pre-alignment device 2 stops generating the attraction force F21 (step S24) so ​​that the micro-LED units 24 are no longer attracted by the attraction force F21 and can move. At this time, the user can continue to transfer the micro-LED units 24 in large quantities.

[0194] In some embodiments, the height of each micro-LED unit 24 is greater than the depth of each groove 210. In other words, when the micro-LED unit 24 is disposed in the groove 210, the micro-LED unit 24 protrudes from the top surface of the groove 210 (as shown in Figure 45 or Figure 46). Therefore, during the pre-alignment process performed by the pre-alignment device 2, when each micro-LED unit 24 is not fixed in the groove 210, each micro-LED unit 24 can be easily detached from the groove 210 without being blocked by the wall of the groove 210. Furthermore, when the pre-alignment device 2 has completed the pre-alignment process and the user begins to transfer the micro-LED units 24 in large quantities, the micro-LED units 24 can be easily moved without being stuck in the groove 210.

[0195] Please refer to Figures 41 and 47. As shown in Figure 41, in some embodiments, the shape of each groove 210 can be trapezoidal, and the width of the bottom of each groove 210 is smaller than the width of the top surface of each groove 210. In other words, the bottom of each groove 210 corresponds to the upper base of the trapezoid, and the top surface of each groove 210 corresponds to the lower base of the trapezoid. Here, when the micro-light-emitting diode unit 24 moves into the groove 210 and the attractive force F21 is greater than the vibration force F22, the micro-light-emitting diode unit 24 can be stably fixed in the groove 210. Furthermore, the trapezoidal shape ensures that the micro-light-emitting diode unit 24, which is not yet fixed in the groove 210, can easily detach from the groove 210 during vibration.

[0196] As shown in Figure 47, in some embodiments, each groove 210 can also be rectangular. In this case, when the micro-light-emitting diode unit 24 moves into the groove 210 and the attractive force F21 is greater than the vibration force F22, the micro-light-emitting diode unit 24 can be stably fixed in the groove 210. Furthermore, the rectangular shape ensures that the micro-light-emitting diode unit 24, already fixed in the groove 210, will not easily detach from the groove 210 during vibration.

[0197] According to any embodiment, the pre-alignment device and pre-alignment method can arrange scattered micro-light-emitting diode units on the same surface and neatly, enabling mass transfer technology to accurately and effectively move a large number of micro-light-emitting diode units. Furthermore, regardless of whether the micro-light-emitting diode units are magnetically conductive, the pre-alignment method can generate a corresponding attractive force (e.g., but not limited to magnetic attraction or vacuum attraction) to fix the micro-light-emitting diode units in the grooves of the alignment disk.

[0198] Referring again to FIG1, in some embodiments, the pixel structure 50 includes a substrate 500, a plurality of vertical diode dies 520, flip-chip diode dies 530, and an upper wiring layer 540. In some embodiments, the pixel structure 50 may face the problem of lacking a suitable method to keep the plurality of vertical diode dies 520 or flip-chip diode dies 530 neat and unskewed after being detached from the PDMS film, causing a bottleneck in the manufacturing process of the pixel structure 50. In some embodiments, the alignment apparatus and alignment method of the following embodiments can be used to transfer the vertical diode dies 520 or flip-chip diode dies 530. However, this disclosure is not limited thereto. Under different design considerations or application scenarios, other structures, processes or procedures may be used to process the vertical diode dies 520 or flip-chip diode dies 530 disclosed in this disclosure.

[0199] Referring to Figures 48 to 50, an aligning device 1 includes a support disk 10 and an aligning disk 11. The support disk 10 includes a plurality of grooves 100, each groove 100 extending along a first direction and the plurality of grooves 100 spaced apart along a second direction, and the first direction is orthogonal to the second direction. In other words, the first direction is perpendicular to the second direction. Taking Figure 49 as an example, in this embodiment, the support disk 10 includes 6 grooves 100, the first direction corresponding to the Z direction and the second direction corresponding to the X direction. Here, each of the 6 grooves 100 extends along the Z direction, and the 6 grooves 100 are spaced apart along the X direction.

[0200] The array tray 11 is disposed on the support tray 10. The array tray 11 includes multiple columns RX, and the multiple columns RX are spaced apart along the second direction and individually aligned with multiple grooves 100. Each column RX is provided with multiple recesses 110, and the bottom of each recess 110 includes a through hole 111. The multiple recesses 110 in each column RX are spaced apart along the first direction. Taking FIG50 as an example, in this embodiment, the array tray 11 includes 6 columns R11~R16, and each column R11 / R12 / R13 / R14 / R15 / R16 includes 6 recesses 110. The multiple columns R11~R16 are spaced apart along the X direction (i.e., the second direction) and individually aligned with multiple grooves 100. The 6 recesses 110 in each column R11 / R12 / R13 / R14 / R15 / R16 are spaced apart along the Z direction (i.e., the first direction). Herein, the array 11 includes 36 grooves 110, and the 36 grooves 110 are arranged in an array at intervals on the array 11.

[0201] Please refer to Figures 48 to 53. The following description of the arrangement method of multiple micro-light-emitting diode units 12 will be based on the arrangement device 1 shown in Figure 48 as an example, but this is not intended to limit the device, hardware component or software component that performs the arrangement method. When the user starts to arrange multiple micro-light-emitting diode units 12, the user operates a moving mechanism (not shown) to move the multiple micro-light-emitting diode units 12 that have been pre-arranged on a carrier plate 13 to a position vertically above the arrangement disk 11 (step S10). It should be noted that "multiple micro-light-emitting diode units 12 that have been pre-arranged" means that the multiple micro-light-emitting diode units 12 on the carrier plate 13 have been pre-arranged into another array, and the other array corresponds to the array formed by the multiple recesses 110 arranged at intervals. Therefore, when multiple micro-light-emitting diode units 12 are moved to a position vertically above the array disk 11, each micro-light-emitting diode unit 12 is located vertically above each groove 110 on the array disk 11 (as shown in Figure 52).

[0202] In some embodiments, the moving mechanism may be a device with the function of two-dimensional movement of an object, such as, but not limited to, a robotic arm. In some embodiments, the carrier plate 13 includes a substrate layer 131, a thin film layer 132, and a plurality of bumps 133. The thin film layer 132 is disposed on the lower surface of the substrate layer 131, and the plurality of bumps 133 are disposed on the lower surface of the thin film layer 132 (as shown in FIG52). Here, the user can attach a plurality of micro-light-emitting diode units 12 through the plurality of bumps 133 on the carrier plate 13, thereby moving the plurality of micro-light-emitting diode units 12.

[0203] In some embodiments, the material of the substrate layer 131 can be a light-transmitting insulating material, such as, but not limited to, glass, silicone, epoxy, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene phthalate (PET), and polyetherimide. In other embodiments, the material of the substrate layer 131 can also be an opaque insulating material, such as, but not limited to, silicon (Si), silicon dioxide (SiO2), gallium arsenide (GaAs), and silicon carbide (SiC). Furthermore, in some embodiments, the material of the thin film layer 132 and the material of the plurality of bumps 133 can be a flexible material with adhesion, such as, but not limited to, polydimethylsiloxane (PDMS) or polysiloxane.

[0204] After step S10, the aligning device 1 generates an attractive force F11 along the extension direction of the through hole 111 to move each micro-light-emitting diode unit 12 from the carrier plate 13 to the bottom of each groove 110 (step S11). In some embodiments, the aligning device 1 further includes a vacuum machine 14 and a controller 15. The vacuum machine 14 is coupled to a plurality of grooves 100 on the support plate 10, and the controller 15 is electrically connected to the vacuum machine 14. In some embodiments, the aligning device 1 can control the vacuum machine 14 to evacuate the plurality of grooves 100 through the controller 15, thereby generating a vacuum suction force (i.e., attractive force F11) along the extension direction of each through hole 111 to exert force on each micro-light-emitting diode unit 12 (as shown in FIG52). Here, each micro-light-emitting diode unit 12 is disengaged from each protrusion 133 on the carrier plate 13 under the influence of the attractive force F11, and then moves to the bottom of each groove 110 (as shown in FIG53).

[0205] In some embodiments, the controller 15 may be a hardware component with control functions that is independent of the vacuum machine 14, such as, but not limited to, a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a microcontroller unit (MCU). In other embodiments, the controller 15 may also be a circuit module with control functions integrated into the vacuum machine 14.

[0206] Please refer to Figures 48 to 57. As shown in Figure 54, in some embodiments, the aligning device 1 can further perform a lighting test on the multiple micro-light-emitting diode units 12 to check whether the multiple micro-light-emitting diode units 12 are functioning normally. Here, in this embodiment, the aligning disk 11 of the aligning device 1 includes a conductive film 16, and the conductive film 16 is disposed on the wall surface of each groove 110 (as shown in Figure 55).

[0207] In some embodiments, after step S11, the aligning device 1 first stops generating the attractive force F11 (step S12). Subsequently, the user can operate the aforementioned moving mechanism to place a transparent cover plate TC1 above the aligning tray 11 (step S13). A conductive film 134 is also formed on the lower surface of the transparent cover plate TC1. Therefore, in this embodiment, when the transparent cover plate TC1 is placed above the aligning tray 11 such that the conductive film 134 of the transparent cover plate TC1 is directly connected to multiple micro-light-emitting diode units 12 (as shown in FIG56), the conductive film 134 of the transparent cover plate TC1 and the conductive film 16 of the aligning tray 11 can serve as two terminals (i.e., N-pole and P-pole) of the micro-light-emitting diode unit 12.

[0208] In some embodiments, the user can electrically connect one of the conductive film 134 of the transparent cover plate TC1 and the conductive film 16 of the array tray 11 to an external power source, and ground the other of the conductive film 134 of the transparent cover plate TC1 and the conductive film 16 of the array tray 11. Here, after step S13, the user can control the external power source to energize the multiple micro-light-emitting diode units 12 through the conductive film 134 of the transparent cover plate TC1 and the conductive film 16 of the array tray 11 (step S14), thereby performing a lighting test on the multiple micro-light-emitting diode units 12.

[0209] In some embodiments, after the lighting test of multiple micro-LED units 12 is completed (i.e., after step S14), the user operates the moving mechanism to remove the transparent cover plate TC1 (step S15). Subsequently, the user operates the moving mechanism to remove the damaged micro-LED unit 12 (step S16). Taking FIG57 as an example, in this embodiment, another carrier plate 13' is coupled to the moving mechanism (not shown), and the other carrier plate 13' includes the aforementioned substrate layer 131, thin film layer 132, and a single bump 133. Therefore, when performing the step of removing the damaged micro-LED unit 12 (i.e., step S16), the moving mechanism can only remove one damaged micro-LED unit 12 at a time.

[0210] Please refer to Figures 48 to 52 and Figures 58 to 60. As shown in Figure 59, in some embodiments, the aligning device 1 further includes a tilting mechanism 17. The tilting mechanism 17 is disposed on the lower surface of the support disk 10 and electrically connected to the controller 15, and the controller 15 is used to control the tilting mechanism 17. Here, after each micro-light-emitting diode unit 12 has been disposed in each groove 110 (i.e., after step S11), the aligning device 1 can control the vacuum machine 14 to stop generating the attractive force F11 (i.e., vacuum suction) through the controller 15 (step S12). Subsequently, the aligning device 1 can control the tilting mechanism 17 to tilt through the controller 15, so that the aligning disk 11 tilts accordingly, so that each micro-light-emitting diode unit 12 aligns with one wall of each groove 110 (step S17). Taking Figure 60 as an example, in this embodiment, the tilting mechanism 17 tilts in a clockwise direction. Here, the right half of the entire array 11 is tilted downwards, so that each micro-light-emitting diode unit 12 is aligned with the right side wall of each groove 110.

[0211] It should be noted that the tilting mechanism 17 is not limited to tilting in a clockwise direction. In some other embodiments, the tilting mechanism 17 may also tilt in a counterclockwise direction, so that the left half of the entire array 11 tilts downward, thereby aligning each micro-light-emitting diode unit 12 with the left side wall of each groove 110 (not shown).

[0212] Please refer to Figures 48 to 52 and Figures 61 to 63. As shown in Figure 62, in some embodiments, the aligning device 1 further includes a vibrator 18. The vibrator 18 is disposed on the lower surface of the support disk 10 and electrically connected to the controller 15, and the controller 15 is used to control the vibrator 18. Here, after each micro-light-emitting diode unit 12 has been disposed in each groove 110 (i.e., after step S11), the aligning device 1 can control the vacuum machine 14 to stop generating the attractive force F11 (i.e., vacuum suction) through the controller 15 (step S12). Subsequently, the aligning device 1 can control the vibrator 18 to generate a vibration force F12 to cause the aligning disk 11 to vibrate (step S18). In response to the vibration of the aligning disk 11, each micro-light-emitting diode unit 12 is aligned with one wall of each groove 110. Taking Figure 63 as an example, in this embodiment, the vibrator 18 generates a vibration force F12 in the X direction to cause the entire array of disks 11 to vibrate in the X direction. Here, a frictional force (not shown) in the opposite direction to the X direction is generated between each micro-LED unit 12 and the bottom of each groove 110, causing each micro-LED unit 12 to be displaced to the left by the frictional force, thereby aligning each micro-LED unit 12 with the left side wall of each groove 110.

[0213] It should be noted that the vibrator 18 is not limited to generating a vibration force F12 in the X direction. In some other embodiments, the vibrator 18 may also generate a vibration force F12 in the opposite direction to the X direction, so that a frictional force in the X direction is generated between each micro-light-emitting diode unit 12 and the bottom of each groove 110, thereby causing each micro-light-emitting diode unit 12 to be displaced to the right and aligned with the right side wall of each groove 110 (not shown).

[0214] In some embodiments, the support disk 10 is a non-conductive rigid material, such as, but not limited to, glass, silicon (Si), silicon dioxide (SiO2), gallium arsenide (GaAs), and silicon carbide (SiC). Furthermore, in some embodiments, the array disk 11 is an insulating material, such as, but not limited to, silicone, epoxy, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), SU8 photoresist, acrylic resin, polyethylene phthalate (PET), and polyetherimide. Here, thanks to the properties of the material of the support disk 10, the sidewalls surrounding each groove 100 in the support disk 10 can support the array disk 11, thereby ensuring that the array disk 11 is not deformed by the force of attraction F11 (e.g., but not limited to vacuum suction) or vibration F12.

[0215] According to any embodiment, the aligning device and method can remove the pre-aligned multiple micro-light-emitting diode units from the film and place each micro-light-emitting diode unit in a groove of the aligning disk. Furthermore, the aligning device and method can align each micro-light-emitting diode unit with one wall of each groove using a tilting mechanism or a vibrating machine to achieve a neat arrangement of the multiple micro-light-emitting diode units, thereby improving the accuracy and efficiency of subsequent mass transfer of multiple micro-light-emitting diode units.

[0216] Although this disclosure has been clearly disclosed according to the different embodiments described above, the embodiments are not intended to limit this disclosure. Any modifications, substitutions or omissions made by those skilled in the art relative to the above embodiments without departing from the spirit and scope of this disclosure shall still fall within the scope of the technology protected by this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope of the patent application. [Simplified Explanation of the Diagram]

[0077] [Figure 1] is a cross-sectional view of a pixel structure according to some embodiments. [Figure 2A] is a schematic diagram of the layered structure of a vertical diode grain according to some embodiments. [Figure 2B] is a schematic diagram of the layered structure of a flip-chip diode grain according to some embodiments. [Figure 3A] is a schematic diagram of the configuration of vertical diode grains according to some embodiments. [Figure 3B] is a schematic diagram of the configuration of flip-chip diode grains according to some embodiments. [Figures 4A-4D] are top views of pixel structures according to different embodiments. [Figure 5] is a top view of a panel structure according to some embodiments. [Figure 6] is a flowchart of a pixel structure repair method according to a first embodiment. [Figures 7A-7H] are process diagrams of a pixel structure repair method according to a first embodiment. [Figure 8] is a flowchart of a pixel structure repair method according to a second embodiment. [Figures 9A-9C] are process diagrams of a pixel structure repair method according to a second embodiment. [Figure 10] is a flowchart of a pixel structure repair method according to a third embodiment. [Figure 11] is a schematic diagram of the pixel structure repair method according to the third embodiment. [Figure 12] is a top plan view of the hybrid micro-light-emitting diode structure according to the fourth embodiment. [Figure 13] is a cross-sectional view of the hybrid micro-light-emitting diode structure in Figure 12 along section line 2-2. [Figure 14] is a top plan view of the hybrid micro-light-emitting diode structure according to the fifth embodiment. [Figure 15] is an operation flowchart of one embodiment of the hybrid micro-light-emitting diode structure in Figure 12. [Figure 16] is an operation flowchart of one embodiment of the following step S42 in Figure 15. [Figure 17] is a cross-sectional view of the hybrid micro-light-emitting diode structure in Figure 12 along section line 2-2. [Figure 18] is a schematic diagram of multiple diode grains with different grain heights according to some embodiments. [Figure 19] is a flowchart of a method for manufacturing diode grains according to some embodiments. [Figures 20A to 20K] are schematic diagrams of a diode die manufacturing method according to some embodiments. [Figure 21] is a schematic diagram of a diode die according to some embodiments. [Figure 22] is a schematic diagram comparing the heights of multiple semi-finished substrates according to some embodiments. [Figure 23] is a flowchart of a diode die manufacturing method according to other embodiments. [Figures 24A to 24B] are schematic diagrams of a diode die manufacturing method according to other embodiments. [Figure 25] is a schematic diagram of a panel structure according to some embodiments. [Figure 26] is a side plan view of a vertical micro-light-emitting diode unit according to a sixth embodiment. [Figure 27] is a side plan view of an embodiment of the first backplate in Figure 26. [Figure 28] is a side plan view of an embodiment of the second backplate in Figure 26. [Figure 29] is a partially exploded view of the vertical micro-light-emitting diode unit in Figure 26. [Figure 30] is a top plan view of an embodiment of the first backplate in Figure 26.[Figure 31] is a top plan view of an embodiment of the second backplate in Figure 26. [Figure 32] is an operational flowchart of an embodiment of the vertical micro-light-emitting diode unit in Figure 26. [Figure 33] is a side plan view of the vertical micro-light-emitting diode unit according to the seventh embodiment. [Figure 34] is a side plan view of a vertical micro-light-emitting diode structure according to some embodiments. [Figure 35] is a side plan view of an embodiment of the first backplate in Figure 34. [Figure 36] is a side plan view of an embodiment of the second backplate in Figure 34. [Figure 37] is a partially exploded view of the vertical micro-light-emitting diode unit in Figure 34. [Figure 38] is a top plan view of an embodiment of the first backplate in Figure 34. [Figure 39] is a top plan view of an embodiment of the second backplate in Figure 34. [Figure 40] is an operational flowchart of an embodiment of the vertical micro-light-emitting diode structure in Figure 34. [Figure 41] is a side schematic diagram of a pre-alignment device according to the eighth embodiment. [Figure 42] is a top view of the pre-alignment device in Figure 41. [Figure 43] is an operation flowchart of the pre-alignment device according to some embodiments. [Figure 44] is an operation diagram of the pre-alignment device in Figure 41. [Figure 45] is a partial enlarged view of the pre-alignment device according to the eighth embodiment in Figure 44. [Figure 46] is a partial enlarged view of the pre-alignment device according to the ninth embodiment in Figure 44. [Figure 47] is a side view of the pre-alignment device according to the ninth embodiment. [Figure 48] is a side view of the alignment device according to the tenth embodiment. [Figure 49] is a top view of one embodiment of the support tray in Figure 48. [Figure 50] is a top view of one embodiment of the alignment tray in Figure 48. [Figure 51] is an operation flowchart of one embodiment of the alignment device in Figure 48. [Figure 52] is a schematic diagram of a first exemplary state of the alignment device in Figure 48. [Figure 53] is a schematic diagram of a first exemplary state of the alignment device in Figure 48. [Figure 54] is a flowchart of the operation of the successive step S11 in Figure 51. [Figure 55] is a side view of the aligning device according to the eleventh embodiment. [Figure 56] is a schematic diagram of the first exemplary state of the aligning device in Figure 55. [Figure 57] is a schematic diagram of the second exemplary state of the aligning device in Figure 55. [Figure 58] is a flowchart of the operation of the successive step S11 in Figure 51. [Figure 59] is a block diagram of the aligning device according to the twelfth embodiment. [Figure 60] is a side view of the aligning device in Figure 48. [Figure 61] is a flowchart of the operation of the successive step S11 in Figure 51. [Figure 62] is a block diagram of the aligning device according to the thirteenth embodiment. [Figure 63] is a side view of the aligning device in Figure 62.

Claims

1. A pixel structure, characterized in that the pixel structure comprises: a substrate having a lower wiring layer, the lower wiring layer comprising a plurality of first wirings and a second wiring, the first wirings belonging to a first polarity and the second wiring belonging to a second polarity; a plurality of vertical diode dies disposed on the substrate and respectively coupled to the first wirings; a flip-chip diode die disposed on the substrate and coupled to one of the first wirings and the second wiring; and an upper wiring layer disposed on the plurality of vertical diode dies and the flip-chip diode die, the upper wiring layer comprising a plurality of third wirings respectively coupled to the vertical diode dies and the third wirings belonging to the second polarity.

2. The pixel structure as claimed in claim 1, characterized in that the pixel structure further comprises a plurality of blocks and a light-transmitting filling layer, the plurality of blocks defining a plurality of receiving sites, the plurality of vertical diode grains and the flip-chip diode grains being respectively located within the plurality of receiving sites, the light-transmitting filling layer covering the flip-chip diode grains, and the top surface of the light-transmitting filling layer being substantially coplanar with the top surfaces of the blocks.

3. The pixel structure as described in claim 1, characterized in that the plurality of vertical diodes include at least one ineffective vertical diode and at least one effective vertical diode, and the color category of the light beam corresponding to the flip-chip diode is different from the color category of the light beam corresponding to the at least one effective vertical diode.

4. The pixel structure as claimed in claim 1, characterized in that the pixel structure further comprises multiple first light conversion material layers, respectively covering each of the vertical diode grains.

5. The pixel structure as claimed in claim 1, characterized in that the pixel structure further includes a second light conversion material layer covering the flip-chip diode grain.

6. The pixel structure as described in claim 1, characterized in that the pixel structure further comprises a vertical diode die unit, comprising: a first backplate comprising: another substrate; an upper wiring layer disposed on the other substrate; a first contact pad disposed on the upper wiring layer; and a transparent electrode layer disposed on the upper wiring layer and the first contact pad; and a second backplate comprising: the substrate; a lower wiring layer disposed on the substrate; a eutectic metal layer disposed on the lower wiring layer; an alloy layer disposed on the eutectic metal layer; one of the vertical diode dies disposed on the alloy layer; a second contact pad disposed on one of the vertical diode dies; and an isolation layer disposed on the substrate to surround one of the vertical diode dies; wherein... The first backplate is disposed on the second backplate to form a chamber. The projected areas of the first contact pad and the second contact pad along the normal direction of the first backplate at least partially overlap, and the transparent electrode layer connects the second contact pad and the isolation layer. When the first backplate is disposed on the second backplate, the isolation layer is deformed such that the thickness of the deformed isolation layer is equal to the sum of the thickness of the first contact pad, the thickness of the underlay layer, the thickness of the eutectic metal layer, the thickness of the alloy layer, the thickness of one of the vertical diode grains, and the thickness of the second contact pad.

7. The pixel structure as claimed in claim 6, characterized in that the isolation layer of the vertical diode die unit comprises an opaque material and a transparent material, wherein the opaque material surrounds one of its vertical diode dies and the second contact pad, and the transparent material surrounds the lower trace layer, the eutectic metal layer and the alloy layer.

8. The pixel structure as claimed in claim 1, characterized in that the plurality of vertical diode grains comprises: a first diode grain including a first electrode having a first electrode thickness; and a second diode grain including a second electrode having a second electrode thickness, the first electrode thickness being greater than the second electrode thickness, and the first diode grain and the second diode grain having substantially the same grain height.

9. The pixel structure as claimed in claim 8, wherein the first electrode is the bottom electrode of the first diode grain and the second electrode is the bottom electrode of the second diode grain.

10. A panel structure, characterized in that the panel structure comprises a plurality of pixel structures as described in claim 8, each comprising the first diode die and the second diode die, wherein the first electrode of the first electrode of the first diode die of each pixel structure has substantially the same thickness, and the second electrode of the second electrode of the second diode die of each pixel structure has substantially the same thickness.

11. A panel structure, characterized in that the panel structure comprises: a substrate having a lower wiring layer, the lower wiring layer including a plurality of first wirings and a plurality of second wirings, the first wirings belonging to a first polarity and the second wirings belonging to a second polarity; a first pixel structure having a plurality of first receiving sites, the first pixel structure comprising: a plurality of first vertical diode chips disposed on the substrate and respectively located within the plurality of first receiving sites, and respectively coupled to the plurality of first wirings; and a flip-chip diode chip disposed on the substrate and located within one of its first receiving sites, and coupled to one of its first receiving sites. The first pixel structure includes: a trace and a second trace; a second pixel structure having a plurality of second receiving sites, the second pixel structure comprising: a plurality of second vertical diode dies disposed on the substrate and respectively located within the second receiving sites, and respectively coupled to the first traces; a fill layer disposed on the substrate and located within one of the second receiving sites; and an upper trace layer disposed on the first pixel structure and the second pixel structure, the upper trace layer comprising a plurality of third traces respectively coupled to the first vertical diode dies and the second vertical diode dies, the third traces belonging to the second polarity.

12. A pixel structure repair method, characterized in that the pixel structure repair method comprises: providing a substrate; forming a lower wiring layer on the substrate, the lower wiring layer comprising a first wiring and a second wiring, the first wiring belonging to a first polarity and the second wiring belonging to a second polarity; disposing a vertical diode die on the substrate and connecting it to the first wiring; and determining whether the vertical diode die is effective, so as to determine whether to dispose of a flip-chip diode die on the substrate.

13. The pixel structure repair method as described in claim 12, characterized in that the pixel structure repair method further includes, when it is determined that the vertical diode die is invalid, setting the flip-chip diode die on the substrate.

14. The pixel structure repair method as described in claim 12, characterized in that the pixel structure repair method further comprises: when it is determined that the vertical diode die is invalid, setting the flip-chip diode die on the substrate, wherein the flip-chip diode die is a short-wavelength light-emitting diode die; and coating a light conversion material layer on the flip-chip diode die.

15. The pixel structure repair method as described in claim 12, characterized in that the pixel structure repair method further comprises: forming a plurality of blocks on the substrate, the plurality of blocks defining a plurality of receiving sites; setting a plurality of vertical diode grains on the substrate and respectively located within the receiving sites; and when it is determined that the vertical diode grains are all effective, setting a filling layer within the remaining receiving sites, the remaining receiving sites not containing the vertical diode grains.

16. The pixel structure repair method as described in claim 12, characterized in that the pixel structure repair method further includes forming an upper wiring layer on the plurality of vertical diodes and the flip-chip diode, the upper wiring layer including a third wiring coupled to the vertical diode, the third wiring belonging to the second polarity.

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