Memory device and manufacturing method thereof

Abstract

A memory device applicable to high-capacity and / or high-performance 3D NAND flash memory. The memory device includes a substrate, a source line layer, a stacked structure, multiple partition walls, and multiple vertical channels. The source line layer is disposed above the substrate. The stacked structure includes multiple insulating layers and multiple conductive layers alternately stacked above the source line layer. The partition walls penetrate the stacked structure and divide the stacked structure into multiple blocks, wherein each partition wall includes a first portion adjacent to the source line layer and a second portion located on the first portion. The top of the first portion of the partition wall is larger than the bottom of its second portion. The multiple vertical channels penetrate the stacked structure and the source line layer in the multiple blocks.

Claims

1. A memory device, comprising: substrate; A source line layer is disposed above a substrate; a stacked structure includes multiple insulating layers and multiple conductive layers alternately stacked above the source line layer; multiple partition walls penetrate the stacked structure and divide the stacked structure into multiple blocks, wherein each partition wall includes a first portion near the source line layer and a second portion located on the first portion; and multiple vertical channels penetrate the stacked structure and the source line layer in the multiple blocks, wherein the top of the first portion is larger than the bottom of the second portion, wherein the stacked structure includes a lower portion near the source line layer and an upper portion located above the lower portion, and the interface between the upper portion and the lower portion is at the same level as the interface between the second portion and the first portion of each partition wall.

2. The memory device as claimed in claim 1, wherein the number of layers in the lower part is less than the number of layers in the upper part.

3. The memory device as claimed in claim 1, wherein the ratio of the height of the lower portion of the stacked structure to the height of the first portion of each partition wall is 2:3 to 5:

6.

4. The memory device as claimed in claim 1, wherein each of the partition walls includes a conductive trench contact window and an insulating gap wall disposed at the sidewall of the conductive trench contact window.

5. The memory device as claimed in claim 4, wherein the conductive trench contact window within the first portion has a gap.

6. The memory device as claimed in claim 4, wherein the conductive trench contact window is electrically connected to the source line layer.

7. The memory device as claimed in claim 1, wherein the cross-sectional shape of the first portion is an inverted trapezoid.

8. The memory device as claimed in claim 1, wherein the bottom of the first portion is larger than the bottom of the second portion.

9. The memory device as claimed in claim 1, wherein the plurality of partition walls comprises: Two first partition walls, each of which is a continuous line extending along a first direction; and a second partition wall disposed between the two first partition walls, wherein the second partition wall includes a plurality of sub-partition walls extending along the first direction.

10. A method for manufacturing a memory device, comprising: A lower semiconductor layer is formed above the substrate; A dielectric stack is formed on the lower semiconductor layer; An upper semiconductor layer is formed on the dielectric stack; A first stacked structure is formed on the upper semiconductor layer, wherein the first stacked structure includes a plurality of alternately stacked insulating layers and a plurality of sacrificial layers; a first trench is formed in the first stacked structure until the upper semiconductor layer is exposed; the exposed surface of the upper semiconductor layer is oxidized to form an oxide film; the first trench is filled with a sacrificial material; a second stacked structure is formed on the first stacked structure and the sacrificial material in the first trench; a plurality of vertical channels are formed through the second stacked structure, the first stacked structure, the upper semiconductor layer, the dielectric stack, and the lower semiconductor layer; a second trench is formed in the second stacked structure on the first trench until the sacrificial material is exposed, wherein the width of the top of the first trench is greater than the width of the bottom of the second trench; And remove the sacrificial material.

11. The method of manufacturing a memory device as claimed in claim 10, wherein the sacrificial material is a metallic material, and the ratio of the height of the sacrificial material to the height of the upper semiconductor layer is 1:1 to 2:

1.

12. The method of manufacturing a memory device as claimed in claim 10, wherein the sacrificial material is polycrystalline silicon or carbon material, and the ratio of the height of the sacrificial material to the height of the upper semiconductor layer is 2:1 to 5:

1.

13. A method of manufacturing a memory device as claimed in claim 10, wherein the second stacked structure comprises a plurality of insulating layers and a plurality of sacrificial layers stacked alternately.

14. The method of manufacturing a memory device as claimed in claim 10, wherein the thickness of the oxide film is from 10 angstroms to 300 angstroms.

15. A method of manufacturing a memory device as claimed in claim 10, further comprising, after removing the sacrificial material: Remove the oxide film to expose part of the upper semiconductor layer; etch the upper semiconductor layer until the dielectric stack is exposed; A protective gap wall is formed on the inner sidewalls of the second trench and the first trench; the dielectric stack is removed to form a source layer space; and the source layer space is filled with a conductive material.

16. A method of manufacturing a memory device as claimed in claim 15, wherein the sidewalls of each of the vertical channels are exposed during the removal of the dielectric stack.

17. The method of manufacturing a memory device as claimed in claim 15, further comprising, after filling the source layer space with the conductive material: Remove the protective gap wall; And in the process of replacing the metal gate, the multiple sacrificial layers are replaced with metal gates.

18. The method of manufacturing a memory device as claimed in claim 17, wherein after the replacement metal gate process, it further includes: An insulating gap wall is formed on the sidewalls of the second trench and the first trench; Conductive trench contact windows are formed in the second trench and the first trench.

19. A method of manufacturing a memory device as claimed in claim 18, wherein the material of the conductive trench contact window comprises the same material as the conductive material.

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