Contact structure and method for forming the same

Abstract

A contact structure according to the present disclosure includes: a device layer above a substrate; a dielectric structure above the device layer; a first etch-stop layer above the dielectric structure; a through-hole extending through the dielectric structure and the device layer and including a top portion of the through-hole rising above the first etch-stop layer; a guard ring structure above the first etch-stop layer and surrounding the top portion of the through-hole; a protective layer disposed above the guard ring structure; a second etch-stop layer conformally disposed above a top surface of the first etch-stop layer, a sidewall of the guard ring structure, a sidewall of the protective layer, and a top surface of the protective layer; and a dielectric layer of the second etch-stop layer.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generation after generation of ICs, each smaller and more complex than the last. In the evolution of ICs, functional density (i.e., the number of interconnects per chip area) has generally increased, while geometry (i.e., the smallest component (or wiring) that can be produced using the manufacturing process) has decreased. This scaling down process typically provides benefits by increasing production efficiency and reducing associated costs.

[0003] Through-substrate vias (TSVs) are commonly used in 3DICs because they route electrical signals from one side of the IC's silicon substrate to the other. The formation of TSVs can stress the surrounding structure, leading to delamination and damage. Protective structures have been developed to reduce, absorb, or isolate the stress generated by TSVs. [Summary of the Invention]

[0004] None

Implementation Method

[0006] This disclosure is generally relating to integrated circuit devices, and more specifically to the interconnection structure of integrated circuit devices.

[0007] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these elements and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0008] For ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature and another, as shown in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein will be interpreted accordingly.

[0009] Furthermore, when using terms such as "about" or "approximately" to describe a number or range of numbers, the term is intended to encompass a reasonable range of numbers within the scope of variations inherent in manufacturing as understood by those skilled in the art. For example, a number or range of numbers encompasses a reasonable range including the described number, such as within + / - 10% of the described number, based on known manufacturing tolerances associated with features having number-related characteristics in manufacturing. For instance, a material layer with a thickness of "about 5 nm" may encompass a size range from 4.25 nm to 5.75 nm, where those skilled in the art know that the manufacturing tolerance associated with the deposited material layer is + / - 15%. Additionally, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0010] Interconnect structures electrically couple various components (e.g., transistors, resistors, capacitors, and / or inductors) fabricated on a substrate, enabling the components to operate in a manner specified by design requirements. Interconnect structures comprise a combination of dielectric and conductive layers that provide electrical signal routing. The conductive layers include vias and contact features providing vertical connections, and conductive lines providing horizontal connections. In some embodiments, the interconnect structure may have five (5) to twenty (20) levels of metal layers (or metallization layers) that are vertically interconnected vias or contact features. During IC device operation, the interconnect structure routes signals and / or distributes signals (e.g., clock signals, voltage signals, and / or ground signals) to the components of the IC device. The interconnect structure is formed in the back-end-of-the-line (BEOL) process, typically after the front-end-of-the-line (FEOL) process forms active devices such as transistors on the substrate, and the middle-end-of-the-line (MEOL) process forms the source / drain contacts and gate contacts.

[0011] In some embodiments, it is desirable to provide vertical interconnects extending through interconnect structures and / or substrates to facilitate various device structures, such as CMOS image sensors (CIS), three-dimensional integrated circuits (3DIC), systems of integrated chips (SoIC), systems on chips (SoC), wafers, neuromorphic computing circuit designs, artificial intelligence (AI) systems, MEMS devices, radio frequency (RF) devices, wafer-on-wafer (WoW) devices, etc. Such vertical interconnects may be referred to as through-silicon vias (TSVs) or through substrate vias (TSVs) because the vertical interconnects pass through all or part of the semiconductor substrate. The term "through substrate via" in this disclosure broadly encompasses via structures that provide direct signal routing from the front side of the substrate to the back side of the substrate, and vice versa. During the fabrication and operation of structures including through substrate vias, the through substrate vias are subject to mechanical stresses caused by temperature variations. If mechanical stress is not absorbed or distributed, it may affect the electrical characteristics of substrate perforations and the lifespan of semiconductor devices.

[0012] This disclosure provides a method for forming a protective ring structure surrounding a portion of a substrate through-hole. The protective ring structure includes one or more films with different coefficients of thermal expansion, and the one or more films can absorb and distribute stress applied to the substrate through-hole. By controlling the thickness and composition of each film in the protective ring structure, the protective ring structure can be customized according to a specific substrate through-hole design and application. The protective ring structure disclosed herein shows promising results in reducing mechanical stress on substrate through-holes and improving their electrical properties, which can lead to more efficient and durable semiconductor devices.

[0013] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. For this purpose, Figure 1 is a flowchart illustrating a method 100 for forming an apparatus structure from a work-in-progress (WIP) structure 200 (shown in Figures 2 through 21) and through-hole structures passing through the apparatus structure, according to various aspects of this disclosure. Method 100 is merely an example and is not intended to limit this disclosure to the content explicitly illustrated in Method 100. Additional steps may be provided before, during, and after Method 100, and some described steps may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. Method 100 is described below with reference to Figures 2 through 21, which are partial cross-sectional views of the WIP structure 200 at different manufacturing stages according to various embodiments of Method 100. Since the WIP structure 200 will be manufactured as an apparatus structure, it may be referred to herein as an apparatus structure, depending on the context. For the avoidance of doubt, the X, Y, and Z directions in Figures 2 through 21 are perpendicular to each other. Throughout this disclosure, unless otherwise explicitly stated, the same reference numerals denote the same features.

[0014] The device structures shown in the figures of this disclosure are simplified, and not all features of the device structures are shown or described in detail. The device structures shown in the figures may be IC chips, system-on-chip (SoC), or a portion thereof. The chip may contain various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0015] Referring to Figures 1 and 2 through 4, method 100 includes block 102, wherein a first etch stop layer (ESL) layer 204, a first dielectric layer 206, a second etch stop layer 208, and a second dielectric layer 210 are deposited on a substrate 201. Referring to Figure 2, the substrate 201 is part of a WIP structure 200, which further includes a device layer 202 above the substrate 201 and a lower interconnect structure 203 above the device layer 202. In one embodiment, the substrate 201 comprises silicon (Si). Alternatively or additionally, substrate 201 may comprise another elemental semiconductor, such as germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Alternatively, substrate 201 may be a semiconductor-on-insulator (SOI) substrate, such as a silicon germanium-on-insulator (SGOI) substrate or a germanium-on-insulator (GeOI) substrate. The SOI substrate may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. Depending on the design requirements of the device architecture, substrate 201 may comprise various doped regions (not shown). In some embodiments, substrate 201 may include p-type doped regions (e.g., p-type wells) and n-type doped regions (e.g., n-type wells). The p-type doped regions may be doped with p-type dopants such as boron (e.g., BF2), indium, other p-type dopants, or combinations thereof. The n-type doped regions may be doped with n-type dopants such as phosphorus (P), arsenic (As), other n-type dopants, or combinations thereof. In some embodiments, substrate 201 includes doped regions formed from combinations of p-type and n-type dopants. Various doped regions may be formed directly on and / or in substrate 201, for example, by providing p-well structures, n-well structures, dual-well structures, protrusion structures, or combinations thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes may be performed to form the various doped regions.

[0016] Device layer 202 includes transistors 2020 and middle-end-of-the-line (MEOL) contact structures. Each of the transistors 2020 may be a planar transistor or a multi-gate transistor, such as a fin-like FET (FinFET) or a gate-all-around (GAA) transistor. The FinFET includes a fin-shaped active region and a gate structure surrounding the fin-shaped active region. The channel region of the GAA transistor is formed from various shapes of nanostructures, such as nanowires, nanorods, or nanosheets. The GAA transistor includes a gate structure surrounding each of a plurality of nanostructures extending between two epitaxial source / drain electrodes. The plurality of nanostructures may be formed from a substrate 201 or from an epitaxial layer formed on the substrate 201, which may be a silicon (Si) substrate. In the latter case, the epitaxial layer may contain germanium (Ge) or silicon germanium (SiGe). Although transistor 2020 is shown as a GAA transistor in Figure 3 and subsequent figures, it should be understood that transistor 2020 may also be a planar device or a FinFET.

[0017] Although not explicitly shown, the gate structure of transistor 2020 includes an interface layer interfacing with the nanostructure, a gate dielectric layer above the interface layer, and a gate electrode layer above the gate dielectric layer. The intermediate layer may contain a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may contain a high-k dielectric material, such as hafnium oxide. Alternatively, the gate dielectric layer may comprise other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The gate dielectric layer can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation and / or other suitable methods.

[0018] The gate electrode layer of the gate structure may comprise a single layer or alternatively a multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a padding layer, a wetting layer, an adhesive layer, a metal alloy, or a combination of metal silicides. For example, the gate electrode layer may comprise titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof.

[0019] Epitaxial source / drain features of the transistor 2020 can be deposited using vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. When the epitaxial source / drain features are n-type, they may comprise silicon (Si) doped with an n-type dopant (such as phosphorus (P) or arsenic (As)). When the epitaxial source / drain features are p-type, they may comprise silicon germanium (SiGe) doped with a p-type dopant (such as boron (B) or boron difluoride (BF2)). In some alternative embodiments not explicitly shown in the figures, the epitaxial source / drain features may comprise multiple layers. In one example, the epitaxial source / drain feature may comprise a lightly doped first epitaxial layer interfaced with the nanostructure, a heavily doped second epitaxial layer above the lightly doped first epitaxial layer, and a cap epitaxial layer disposed above the heavily doped second epitaxial layer. The first epitaxial layer has a lower doping concentration or a lower germanium content (when germanium is present) than the second epitaxial layer to reduce lattice mismatch defects. The second epitaxial layer has the highest doping concentration or the highest germanium content (when germanium is present) to reduce resistance and increase strain on the channel. The cap epitaxial layer may have a lower doping concentration and germanium content (when germanium is present) than the second epitaxial layer to increase etch resistance.

[0020] The MEOL structure in device layer 202 may include an interlayer dielectric (ILD) layer and source / drain contacts. The source / drain contacts extend through the ILD layer to be physically and electrically coupled to epitaxial source / drain features. In some embodiments, the ILD layer may comprise: silicon oxide; tetraethylorthosilicate (TEOS) oxide; un-doped silicate glass (USG); or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), and / or other suitable dielectric materials. The ILD layer may be deposited using PECVD, FCVD, spin coating, or suitable deposition techniques. In some embodiments, the ILD layer may be annealed after deposition to improve its integrity. The source / drain contacts may comprise ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu). In one embodiment, the source / drain contacts comprise cobalt (Co). The source / drain contacts may be deposited using CVD, PVD, or suitable methods. Although not shown in the figures, a contact etch stop layer (CESL) may be deposited prior to the deposition of the ILD layer, such that the CESL is positioned between the ILD layer and the epitaxial source / drain features. The CESL may comprise silicon nitride, silicon carbonitride, or silicon oxynitride, and may be deposited using CVD, ALD, or suitable methods. In some embodiments not explicitly shown, the source / drain contacts may include a barrier layer for interfacing with the ILD layer. Such a barrier layer may comprise a metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, cobalt nitride, or nickel nitride. Additionally, to reduce contact resistance, a silicon feature can be placed between the source / drain contact and the epitaxial source / drain feature. The silicon feature may include titanium silicon.

[0021] As shown in Figure 2, device layer 202 includes a via formation region 2022 that does not contain transistor 2020 and MEOL structure. That is, since the via formation region 2022 in device layer 202 is formed along transistor 2020 and MEOL structure, via formation region 2032 includes an interlayer dielectric (ILD) layer and at least one etch stop layer (ESL). Since via formation region 2030 does not contain transistor 2020 and metal gate structure, forming a via opening through via formation region 2022 does not involve etching through metal features and does not generate unwanted metal debris.

[0022] The lower interconnect structure 203 may be the lower portion of an interconnect structure that includes more layers of metallization. In some embodiments, the lower interconnect structure 203 may include the first three (3) to first six (6) metallization layers closest to the device layer 202. The number of layers in the lower interconnect structure 203 defines the final through-hole penetration of the interconnect structure. After the through-hole is formed, additional layers of metallization are formed above the lower interconnect structure 203. These additional layers of metallization may be collectively referred to as the upper interconnect structure. In some embodiments, the number of metallization layers in the lower interconnect structure 203 is selected such that the metallization layer immediately above the lower interconnect structure is much larger and thicker than the topmost metallization layer in the lower interconnect structure 203. This ensures that the through-hole falls on a mechanically stronger metallization layer.

[0023] Each of the metallization layers in the lower interconnect structure 203 includes an etch stop layer (ESL), an intermetallic dielectric (IMD) layer disposed on the etch stop layer, and a plurality of vertically extending vias and horizontal metal lines disposed in the IMD layer and the etch stop layer. The etch stop layer and the IMD layer may be interleaved, or the IMD layer and the etch stop layer may be interleaved. The etch stop layers may share the same composition and may contain silicon nitride or silicon oxynitride. The IMD layer can share the same composition and may include: silicon oxide; tetraethyl orthosilicate (TEOS) oxide; undoped silicate glass (USG); or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Examples of low-k dielectric materials include carbon-doped silica oxide, xerogel, aerogel, amorphous fluorinated carbon, benzocyclobutene (BCB), or polyimide. The vias and metal lines in the lower interconnect structure 203 may comprise titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), and / or other suitable materials. In one embodiment, the vias and metal lines may comprise copper (Cu). In some embodiments, to prevent electromigration from the metal material or oxygen diffusion from dielectric features into the metal material, the vias and metal lines may each comprise a barrier layer for interfacing with the etch stop layer and the IMD layer. The barrier layer may comprise titanium nitride (TiN), tantalum nitride (TaN), or cobalt nitride (CoN). As shown in Figure 2, the lower interconnect structure 203 includes a via formation region 2030 that does not contain vias and metal lines. That is, since the via formation region 2030 is formed together with the vias and metal lines, the via formation region 2030 includes the etch stop layer of all IMD layers and metallization layers. Since the via forming region 2030 does not contain any metal features, forming a via opening through the via forming region 2030 does not involve etching through the metal features and will not generate unwanted metal debris.

[0024] In order to clearly illustrate the formation of the protective ring structure, the area of ​​the through hole forming region 2032 in Figure 2 is enlarged and shown in Figure 3 and subsequent figures (such as Figures 4 to 17).

[0025] As shown in Figures 3 and 4, at block 102, a first etch-stop layer 204 is deposited on the top surface of the lower interconnect structure 203, including the via formation region 2030. The first etch-stop layer 204 may comprise a dielectric material having silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon (C), aluminum (Al), or combinations thereof. In some embodiments, the first etch-stop layer 204 may comprise silicon carbonitride, aluminum oxide, or aluminum nitride. The first etch-stop layer 204 may be deposited using plasma-enhanced chemical vapor deposition (PECVD) or CVD. In some cases, the first etch-stop layer 204 may have a thickness between about 90 Å and about 150 Å. A first dielectric layer 206 is deposited above the first etch-stop layer 204. The composition of the first dielectric layer 206 differs from the composition of the first etch-stop layer 204. In some embodiments, the first dielectric layer 206 may comprise silicon oxide and may be deposited using CVD, spin coating, or flowable CVD (FCVD). In one embodiment, CVD deposition of the first dielectric layer 206 is used to ensure its structural integrity. The thickness of the first dielectric layer 206 can vary considerably depending on the design of the guard ring structure and the thickness of the metallization layer housing the guard ring structure. In some cases, the thickness of the first dielectric layer 206 may be between about 10 Å and about 500 Å.

[0026] At block 102, a second etch-stop layer 208 is deposited over the first dielectric layer 206, as shown in Figure 4. The second etch-stop layer 208 acts as a chemical mechanical polishing (CMP) stop layer. In a subsequent CMP planarization step, the second etch-stop layer 208 slows down the polishing speed to provide a signal to the CMP tool to stop the CMP process. In some embodiments, the second etch-stop layer 208 may comprise a dielectric material having silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon (C), aluminum (Al), or combinations thereof. In some embodiments, the second etch-stop layer 208 may comprise silicon carbonitride, silicon nitride, silicon carbide, or silicon carbonitride oxide. The second etch-stop layer 208 can be deposited using PECVD or CVD. At block 102, a second dielectric layer 210 is deposited over the second etch-stop layer 208. The second dielectric layer 210 acts as a sacrificial layer to provide the depth of material that is ground away during subsequent CMP planarization steps. To provide a uniform planarization rate, PECVD or CVD is used instead of spin coating or FCVD to form the second dielectric layer 210. In some embodiments, the second dielectric layer 210 may comprise silicon oxide. The second dielectric layer 210 is thicker than the first dielectric layer 206. In some embodiments, the second dielectric layer 210 may have a thickness between 200 nm and 500 nm.

[0027] Referring to Figures 1 and 5, method 100 includes block 104 in which a via opening 211 is formed through the second dielectric layer 210, the second etch-stop layer 208, the first dielectric layer 206, and the first etch-stop layer 204. To form the via opening 211, a masking layer is formed over the second dielectric layer 210. The masking layer may comprise a photoresist, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, or titanium nitride. In one embodiment, the masking layer may be a photoresist layer with a thickness between about 5 µm and about 15 µm. The photoresist layer has a composition different from that of the etch-stop layer, the ILD layer, and the IMD layer, which allows selective etching of the etch-stop layer, the ILD layer, the IMD layer, and the substrate 201. In this embodiment, spin coating or FCVD can be used to deposit the masking layer. Next, the deposited mask layer undergoes a pre-exposure baking process, exposure to radiation reflected or transmitted through the photomask, a post-exposure baking process, and a development process to form a patterned mask layer. This patterned mask layer is then used as an etching mask to etch the etch stop layer, ILD layer, IMD layer, and substrate 201. The etching process here can be a dry etching process (e.g., reactive ion etching (RIE) process). In some cases, the dry etching process can be implemented using oxygen-containing gases (e.g., O2), fluorine-containing gases (e.g., SF6 or NF3), chlorine-containing gases (e.g., Cl2 and / or BCl3), bromine-containing gases (e.g., HBr), iodine-containing gases, other suitable gases, and / or plasma, and / or combinations thereof. Etching terminates at block 104 when the depth of the via opening 211 into the substrate 201 is between 2 µm and about 150 µm (e.g., between 10 µm and about 60 µm). In some embodiments, the through-hole opening 211 is substantially circular in a top view (i.e., viewed along the Z direction), and the diameter D is between about 2 µm and about 12 µm. The diameter D defines the shape and size of the perforation formed in the through-hole opening 211.

[0028] Referring to Figures 1 and 6, method 100 includes block 106, wherein a metal filler layer 212 is formed over a via opening 211. At block 106, a barrier layer 213 and a metal filler layer 212 are deposited over the via opening 211. In some embodiments, the barrier layer 213 may comprise tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), or combinations thereof, and the metal filler layer 212 may comprise copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), ruthenium (Ru), or combinations thereof. In one embodiment, the barrier layer 213 comprises titanium nitride (TiN), and the metal filler layer 212 comprises copper (Cu). At block 106, the barrier layer 213 is first deposited over the via opening 211 using PVD, CVD, MOCVD, ALD, or combinations thereof. The metal filler layer 212 is then deposited using electroplating, PVD, CVD, electroless plating, or a suitable method. In one embodiment, electroplating is used to deposit the metal filler layer 212. In this embodiment, a seed layer can be deposited over the barrier layer 213 using PVD or a suitable process. Then, electroplating can be used to deposit the metal filler layer 212 over the seed layer. In embodiments using electroplating, the seed layer may comprise copper (Cu), titanium (Ti), or a combination thereof, and the metal filler may comprise copper (Cu). As shown in Figure 6, at block 106, the barrier layer 213 is deposited over the via opening 211 to directly contact the following: the sidewall of the substrate 201 (not shown in Figure 6, but shown in Figures 18-21), the sidewall of the device layer 202 (not shown in Figure 6, but shown in Figures 18-21), the sidewall of the via formation region 2030 of the lower interconnect structure 203, the sidewall of the first etch-stop layer 204, the sidewall of the first dielectric layer 206, the sidewall of the second etch-stop layer 208, and the sidewall of the second dielectric layer 210. The barrier layer 213 separates the metal filler layer 212 from the following: the substrate 201, the sidewall of the device layer 202, the sidewall of the via formation region 2030 of the lower interconnect structure 203, the sidewall of the first etch stop layer 204, the sidewall of the first dielectric layer 206, the sidewall of the second etch stop layer 208, and the sidewall of the second dielectric layer 210.

[0029] Referring to Figures 1 and 7 through 9, method 100 includes block 108, wherein a metal filler layer 212 and a second dielectric layer 210 are planarized to form a via 2120. After a barrier layer 213 and a metal filler layer 212 are deposited over the second dielectric layer 210 and into the via opening 211, a planarization process, such as a CMP process, can be performed to remove excess metal filler layer 212, second dielectric layer 210, and second etch stop layer 208. The additional thickness of the metal filler layer 212 helps ensure the surface flatness of the WIP structure 200. In some embodiments shown in Figure 7, after planarization at block 108, a via 2120 comprising a barrier layer 213 and a metal filler layer 212 is formed. In some embodiments, the CMP process removes the dielectric layer and metal filler layer 212 at a uniform rate, and the top surfaces of the via 2120 and the first dielectric layer 206 are substantially coplanar, as shown in Figure 7. In some alternative embodiments, the metal filler layer 212 may be removed at a faster or slower rate than the surrounding dielectric layer. Referring first to Figure 8, which illustrates an alternative embodiment where the CMP process removes the metal filler layer 212 at a faster rate, Figure 8 thus illustrates a recessed via 2120R. As the name suggests, the recessed via 2120R includes a top recess or concave top surface below the first dielectric layer 206. As will be described below, the top recess may affect the cross-sectional profile of the guard ring structure. Next, referring to Figure 9, which illustrates another alternative embodiment where the CMP process removes the metal filler layer 212 at a slower rate, Figure 9 thus illustrates a protruding via 2120P. As the name suggests, the protruding via 2120P includes a top protrusion or convex top surface above the first dielectric layer 206. As will be described below, the top protrusion may affect the cross-sectional profile of the guard ring structure.

[0030] Referring to Figures 1 and 10, method 100 includes block 110, wherein a protective layer 214 is deposited over a first dielectric layer 206 and a via 2120. As shown in Figure 10, at block 110, the protective layer 214 is deposited on the top surface of the via 2120 (or the recessed via 2120R shown in Figure 8 or the protruding via 2020P shown in Figure 9) and the first dielectric layer 206. The protective layer 214 may comprise a dielectric material having silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon (C), aluminum (Al), or combinations thereof. In some embodiments, the protective layer 214 may comprise silicon carbonitride, aluminum oxide, or aluminum nitride. PECVD or CVD can be used to deposit the protective layer 214. Since the protective layer 214 will be etched in a subsequent etching process, the thickness of the protective layer 214 is greater than the thickness of the first etch-stop layer 204. The ratio of the thickness of the protective layer 214 to the thickness of the first etch-stop layer 204 can be between approximately 1.1 and approximately 10. This ratio is not insignificant. When the ratio is less than 1.1, the mechanical strength of the protective layer 214 after the patterning process may be insufficient to cover the via 2120. When the ratio is greater than 10, the protective layer 214 may be too thick to interfere with the formation of metal contact features in the metallization layer directly above the via 2120. In some cases, the thickness of the protective layer 214 can be between approximately 100 Å and approximately 500 Å.

[0031] Referring to Figures 1 and 11, method 100 includes block 112, wherein a patterned mask 215 is formed over a protective layer 214. To form the patterned mask 215, a photoresist layer is deposited over the protective layer 214 using spin coating. The deposited photoresist layer may undergo a pre-exposure baking process, exposure to radiation reflected or transmitted through the photomask, a post-exposure baking process, and a development process to form the patterned mask 215. As shown in Figure 11, the patterned mask 215 serves as an etching mask to pattern the first dielectric layer 206 and the protective layer 214. The shape and size of the patterned mask 215 determine the shape and size of the outline of the protective ring structure 2140 to be formed. As will be described below, in a top view, the patterned mask 215 may have a circular shape, an elliptical shape, a racetrack shape, a rectangular shape, a square shape, or even a triangular shape. In all embodiments, the vertical projection area of ​​the patterned mask 215 completely encloses the vertical projection area of ​​the perforation 2120.

[0032] Referring to Figures 1 and 12, method 100 includes block 114, in which a protective layer 214 and a first dielectric layer 206 are etched. A patterned mask 215 is then applied as an etching mask to the protective layer 214 and the first dielectric layer 206. The etching of the protective layer 214 and the first dielectric layer 206 may include a dry etching process, a wet etching process, or a combination thereof. In some cases, different etching processes or different etching chemicals may be used to etch the protective layer 214 and the first dielectric layer 206. After patterning the protective layer 214 and the first dielectric layer 206, residual patterned mask 215 may be removed by ashing, stripping, or selective etching. As shown in Figure 12, the via 2120 includes a top portion rising a first height H1 from the top surface of the lower interconnect structure 203. The patterned first dielectric layer 206 surrounds the sidewalls of the top portion of the via 2120. A patterned protective layer 214 covers the top surface of the first dielectric layer 206 and the through-hole 2120. In some embodiments, the patterned protective layer 214 and the patterned first dielectric layer 206 include tapered sidewalls that taper upwards. In some cases, the first height H1 is between about 10 Å and about 500 Å.

[0033] Referring to Figures 1 and 13, method 100 includes block 116, wherein a third etch-stop layer 216 is deposited over a patterned first dielectric layer 206, a patterned protective layer 214, and a first etch-stop layer 204. As shown in Figure 13, at block 116, the third etch-stop layer 216 is conformally deposited on the top surface of the protective layer 214 and the first etch-stop layer 204, and on the sidewalls of the first dielectric layer 206 and the protective layer 214. The third etch-stop layer 216 may comprise a dielectric material having silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon (C), aluminum (Al), or combinations thereof. In some embodiments, the third etch-stop layer 216 may comprise silicon carbonitride, aluminum oxide, or aluminum nitride. PECVD or CVD can be used to deposit the third etch-stop layer 216. In some cases, the third etch-stop layer 216 may have a thickness between about 50 Å and about 200 Å. When the operation at block 116 is completed, a guard ring structure 2140 is essentially formed. The guard ring structure 2140 includes a first etch stop layer 204, a first dielectric layer 206, a protective layer 214, and a third etch stop layer 216.

[0034] Referring to Figures 1 and 14 through 16, method 100 includes block 118, wherein a third dielectric layer 218 is deposited over a third etch-stop layer 216. The third dielectric layer 218 may share the same composition as the IMD layer in the underlying interconnect structure 203. In some embodiments, the third dielectric layer 218 may comprise: silicon oxide; tetraethylorthosilicate (TEOS) oxide; un-doped silicate glass (USG); or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), low-k dielectric material, other suitable dielectric materials, or combinations thereof. Examples of low-k dielectric materials include carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, benzocyclobutene (BCB), or polyimide.

[0035] Figure 14 illustrates an embodiment in which planarization at block 108 removes the metal filler layer 212 and surrounding dielectric material at substantially the same rate. Therefore, the top surfaces of the via 2120 and the first dielectric layer 206 in the guard ring structure 2140 are substantially coplanar. The protective layer 214 in the guard ring structure 2140 acts as a cap above the top surface of the via 2120. In this embodiment, the top portion of the via 2120 rises a first height H1 from the first etch-stop layer 204, the first height H1 being between approximately 10 Å and approximately 500 Å. The guard ring structure 2140, comprising the first etch-stop layer 204, the first dielectric layer 206, the protective layer 214, and the third etch-stop layer 216, rises a second height H2 from the top surface of the lower interconnect structure 203, the second height H2 being between approximately 110 Å and approximately 1000 Å. When viewed along the vertical direction (i.e., the Z-direction), the perforation 2120 is substantially circular, with a diameter D between approximately 2 µm and approximately 12 µm. While the sidewalls of the protective ring structure 2140 may be narrower, the widest portion of the protective ring structure 2140, or the width of its base, has a width W between approximately 2.2 µm and approximately 13 µm. Measured from the sidewalls of the perforation 2120, the protective ring structure 2140 has a sidewall thickness S, which may be between approximately 10 nm and approximately 1000 nm. The ratio of the sidewall thickness S to the diameter D may be between approximately 0.01 and approximately 0.5. This ratio is not insignificant. When the ratio is less than 0.01, the protective ring structure 2140 may not have sufficient thickness to reduce the stress applied to or exerted by the perforation 2120. When the ratio is greater than 0.5, the protective ring structure 2140 may occupy excessive area with limited marginal benefits.

[0036] Figure 15 illustrates an embodiment where planarization at block 108 removes the metal filler layer 212 at a faster rate. Therefore, in the guard ring structure 2140, the recessed top surface of the recessed via 2120R is lower than the first dielectric layer 206. The protective layer 214 in the guard ring structure 2140 above the top surface of the recessed via 2120R also includes a recessed profile. In this embodiment, the top portion of the recessed via 2120R rises a third height H3 from the top surface of the lower interconnect structure 203, which is less than the thickness of the first dielectric layer 206. The guard ring structure 2140, comprising the first etch stop layer 204, the first dielectric layer 206, the protective layer 214, and the third etch stop layer 216, rises a fourth height H4 from the top surface of the lower interconnect structure 203, which is between approximately 110 Å and approximately 1000 Å. When viewed along the vertical direction (i.e., the Z-direction), the recessed perforation 2120R is substantially circular, with a diameter D between approximately 2 µm and approximately 12 µm. While the sidewalls of the protective ring structure 2140 may be narrower, the widest portion of the protective ring structure 2140, or the width of its base, has a width W between approximately 2.2 µm and approximately 13 µm. Measured from the sidewalls of the perforation 2120, the protective ring structure 2140 has a sidewall thickness S, which may be between approximately 10 nm and approximately 1000 nm. The ratio of the sidewall thickness S to the diameter D may be between approximately 0.01 and approximately 0.5. This ratio is not insignificant. When the ratio is less than 0.01, the protective ring structure 2140 may not have sufficient thickness to reduce the stress applied to or by the recessed perforation 2120R. When the ratio is greater than 0.5, the protective ring structure 2140 may occupy excessive area with limited marginal benefits.

[0037] Figure 16 illustrates an embodiment in which planarization at block 108 removes the dielectric material around the metal filler layer 212 at a faster rate. Therefore, the convex top surface of the protruding via 2120P is higher than the first dielectric layer 206 in the guard ring structure 2140. The guard layer 214 in the guard ring structure 2140 above the top surface of the protruding via 2120P also includes a convex profile. In this embodiment, the top portion of the protruding via 2120P rises a fifth height H5 from the top surface of the lower interconnect structure 203, which is greater than the thickness of the first dielectric layer 206. The guard ring structure 2140, comprising the first etch stop layer 204, the first dielectric layer 206, the guard layer 214, and the third etch stop layer 216, rises a sixth height H6 from the first etch stop layer 204, which is greater than the second height H2 or the fourth height H4. When viewed along the vertical direction (i.e., the Z-direction), the protruding perforation 2120P is substantially circular, with a diameter D between approximately 2 µm and approximately 12 µm. While the sidewalls of the protective ring structure 2140 may be narrower, the widest portion of the protective ring structure 2140, or the width of its base, has a width W between approximately 2.2 µm and approximately 13 µm. Measured from the sidewalls of the perforation 2120, the protective ring structure 2140 has a sidewall thickness S, which may be between approximately 10 nm and approximately 1000 nm. The ratio of the sidewall thickness S to the diameter D may be between approximately 0.01 and approximately 0.5. This ratio is not insignificant. When the ratio is less than 0.01, the protective ring structure 2140 may not have sufficient thickness to reduce the stress applied to or exerted by the protruding perforation 2120P. When the ratio is greater than 0.5, the protective ring structure 2140 may occupy excessive area with limited marginal benefits.

[0038] Briefly referring to Figure 21, Figure 21 illustrates different top view outlines of the protective ring structure 2140 that is perpendicularly overlapped with the perforation 2120. Outline (A) in Figure 21 includes an elliptical protective ring structure 2140 (shown as the outline of the first dielectric layer 206, as it represents the maximum outline of the protective ring structure), which encloses and overlaps the perforation 2120, which is circular in shape and has a diameter designated as diameter D. The elliptical protective ring structure 2140 includes a major axis A1 and a minor axis A2. To ensure that the protective ring structure 2140 completely encloses the perforation 2120, the minor axis A2 is larger than the diameter D by a margin between 2% and 100%. Outline (B) in Figure 21 includes a circular protective ring structure 2140 (shown as the outline of the first dielectric layer 206, as it represents the maximum outline of the protective ring structure), which encloses and overlaps the through-hole 2120, which is circular in shape and has a diameter labeled as diameter D. The circular protective ring structure 2140 includes a protective ring diameter GD. To ensure that the protective ring structure 2140 completely encloses the through-hole 2120, the protective ring diameter GD is larger than the diameter D by a margin between 2% and 100%. Outline (C) in Figure 21 includes a triangular protective ring structure 2140 (shown as the outline of the first dielectric layer 206, as it represents the maximum outline of the protective ring structure), which encloses and overlaps the through-hole 2120, which is circular in shape and has a diameter labeled as diameter D. To ensure that the guard ring structure 2140 completely encloses the through-hole 2120, the shortest distance between the sides of the triangular guard ring is between approximately 10 nm and 1000 nm. The outline (D) in Figure 21 includes a rectangular guard ring structure 2140 (shown as the outline of the first dielectric layer 206, as it represents the maximum outline of the guard ring structure), which encloses and overlaps the through-hole 2120, which is circular in shape and has a diameter denoted as diameter D. The rectangular guard ring structure 2140 includes a first edge dimension E1 and a second edge dimension E2. To ensure that the guard ring structure 2140 completely encloses the through-hole 2120, the shorter of the first edge dimension E1 and the second edge dimension E2 is larger than the diameter D by a margin between 2% and 100%. When the first edge dimension E1 and the second edge dimension E2 are the same, the guard ring structure 2140 has a square top view outline. The outline (E) in Figure 21 includes a racetrack-shaped protective ring structure 2140 (shown as the outline of the first dielectric layer 206, as it represents the maximum outline of the protective ring structure), which encloses and overlaps a through-hole 2120, which is circular in shape and has a diameter indicated as D. The racetrack-shaped protective ring structure 2140 includes an intermediate rectangle sandwiched between two semicircles. The intermediate rectangle has a non-zero width E3 and a height equal to twice the outer diameter R of the two semicircles.To ensure that the protective ring structure 2140 completely encloses the perforation 2120, the non-zero width E3 is not zero, and the outer diameter R is twice the diameter D with a margin between 2% and 100%.

[0039] When the stress applied by or on the perforation 2120 is uniform in all directions, profile (B) or square profile (D) can be used because such profiles substantially distribute stress uniformly in all directions. When the stress applied by or on the perforation 2120 is stronger in one direction than in others, profile (A), rectangular profile (D), or profile (E) can be used such that the major axis or the direction of the larger dimension is aligned with the direction of stress for better stress bearing or distribution. Profile (C) is used when the design or geometry of the surrounding structure only allows for the triangular protective ring structure 2140.

[0040] Referring to Figures 1 and 17 through 20, method 100 includes block 120 in which conductive features are formed to couple to the top surface of via 2120. The conductive features may have different configurations, some of which are illustrated as examples in Figures 17 through 20. Referring first to Figure 17. The metallization layer in the lower interconnect structure 203 and the via 2120 are coupled upward to the upper interconnect structure 240. The upper interconnect structure 240 may include two (2) to seventeen (17) levels of metallization layers. After depositing the third etch-stop layer 216 and the third dielectric layer 218, first vias 220 are formed, which extend through the third dielectric layer 218, the third etch-stop layer 216 and the guard layer 214, and interface with and couple to the vias. Metal lines 222 (or metal islands) are formed above the first vias 220. Metal line 222 and first via 220 may include a barrier layer and a metal filler layer, the barrier layer separating the metal layer from the surrounding dielectric layer. The barrier layer may include titanium nitride (TiN), and the metal filler layer may include copper (Cu). Generally, the first via 220 has a smaller height outside the via formation region than the second via 219 because the top portion of via 2120 rises above the first etch-stop layer 204. After a planarization step to remove excess material, a fourth etch-stop layer 224 is deposited above metal line 222. After forming another dielectric layer above the fourth etch-stop layer 224, a third via 228 is formed. The third via 228 extends through the fourth etch-stop layer 224 to couple to metal line 222. Since the dimensions of the first via 220 and the third via 228 are measured in nanometers, while the diameter of the through-hole 2120 is measured in micrometers, these vias appear in an array to interface with the through-hole 2120. The array of the first via 220 may contain more vias than the array of the third via 228 to provide mechanical strength and reduce resistance. In some embodiments, the array of the first via 220 may contain 10 to 90 vias, and the array of the third via 228 may contain 2 to 50 vias.

[0041] In the configuration shown in Figure 18, the metal line 222 is omitted, and a fourth through hole 2200 with a height greater than that of the first through hole 220 can be formed to interface with the through hole 2120. The fourth through holes 2200 are also formed in an array. Unlike the configuration shown in Figure 17, the number of fourth through holes 2200 is the same as the number of third through holes 228, because each of the third through holes 228 is formed above one of the fourth through holes 2200.

[0042] In the configuration shown in Figure 19, after depositing the third dielectric layer 218, the third etch-stop layer 216 on the top surface of the guard layer 214 is removed during the planarization process. The fourth etch-stop layer 224 is deposited directly on the guard layer 214. It should be noted that the third etch-stop layer 216 still exists along the sidewall of the first dielectric layer 206. The third via 228 extends through the fourth etch-stop layer 224 and the guard layer 214 to be electrically and physically coupled to the via 2120. Since the bottom surface of the fourth etch-stop layer 224 directly interfaces with the guard layer 214, it can be said that there is no third dielectric layer 218 between the fourth etch-stop layer 224 and the guard layer 214 along the Z direction.

[0043] In the configuration shown in Figure 20, the first via 220 is omitted, and a metal pad 2220 is formed extending through the third dielectric layer 218, the third etch-stop layer 216, and the protective layer 214 to couple to the top surface of the via 2120. The metal pad 2220 may substantially overlap the vertically projected area of ​​the via 2120. In some embodiments, the metal pad 2220 may be circular in top view and have a pad diameter PD. The ratio of the pad diameter PD to the diameter D of the via 2120 may be between 0.9 and about 1.1. That is, the difference between the pad diameter PD and the diameter D of the via 2120 is equal to or less than 10% of the diameter D. The third via 228 extends through the fourth etch-stop layer 224 to couple to the metal pad 2220.

[0044] In subsequent processing, the substrate 201 may undergo a polishing process, a CMP process, or a combination thereof until the vias 2120 are exposed. The exposed vias 2120 can be used for electrical coupling to other structures, such as integrated circuit (IC) dies, interposers, or package substrates.

[0045] In an exemplary sample, this disclosure relates to a method. The method includes: receiving a work-in-progress (WIP) structure, the device structure including a substrate, a device layer above the substrate, and a plurality of interconnect layers above the device layer and including via formation regions; depositing a first etch stop layer (ESL) above the plurality of interconnect layers; depositing a first dielectric layer above the first etch stop layer; depositing a second etch stop layer above the first dielectric layer; depositing a second dielectric layer above the second etch stop layer; forming a via opening through a depth of one of the second dielectric layer, the second etch stop layer, the first dielectric layer, the first etch stop layer, the via formation regions, the device layer, and the substrate; depositing a metal fill layer above the second dielectric layer and the via opening; planarizing the metal fill layer to form a via structure and exposing the first dielectric layer; depositing a protective layer above the via structure and the exposed first dielectric layer; patterning the protective layer and the first dielectric layer to form a protective structure surrounding a portion of the via structure that rises above the first etch stop layer; and depositing a third dielectric layer above the protective structure and the first etch stop layer.

[0046] In some embodiments, the method further includes depositing a third etch stop layer over the protective structure and the first etch stop layer before depositing the third dielectric layer. In some embodiments, depositing the third etch stop layer includes conformally depositing the third etch stop layer over the top surface of the first etch stop layer, the sidewalls of the first dielectric layer, the sidewalls of the protective layer, and the top surface of the protective layer. In some embodiments, the first etch stop layer comprises silicon carbonitride, aluminum nitride, or aluminum oxide. In some embodiments, the first dielectric layer comprises silicon oxide. In some embodiments, the protective layer comprises silicon carbonitride, aluminum nitride, or aluminum oxide. In some embodiments, a first thickness of the first etch stop layer is less than a second thickness of the protective layer. In some cases, the ratio of the second thickness to the first thickness is between about 1.1 and about 10. In some embodiments, the first dielectric layer has a thickness between about 10 Å and about 500 Å. In some cases, the via formation region comprises a plurality of intermetallic dielectric layers and does not contain conductive features.

[0047] In another exemplary embodiment, this disclosure relates to a contact structure. The contact structure includes: a device layer above a substrate; a dielectric structure above the device layer; a first etch-stop layer above the dielectric structure; a through-hole extending through the dielectric structure and the device layer, wherein the top portion of the through-hole rises above the first etch-stop layer; a guard ring structure above the first etch-stop layer and surrounding the top portion of the through-hole; a protective layer disposed above the guard ring structure; a second etch-stop layer conformally disposed above the top surface of the first etch-stop layer, the sidewalls of the guard ring structure, the sidewalls of the protective layer, and the top surface of the protective layer; and a dielectric layer of the second etch-stop layer.

[0048] In some embodiments, the perforation is substantially a loop and includes a diameter in a top view. In some embodiments, the guard ring structure includes a thickness measured from the sidewall of the perforation, and the thickness-to-diameter ratio is between about 0.01 and about 0.5. In some embodiments, the guard ring structure includes a circular shape, a rectangular shape, an elliptical shape, or a racetrack shape in a top view. In some embodiments, a first thickness of the first etch stop layer is less than a second thickness of the guard layer. In some embodiments, the ratio of the second thickness to the first thickness is between about 1.1 and about 10.

[0049] In another exemplary embodiment, this disclosure relates to a contact structure. The contact structure includes: a device layer above a substrate; a dielectric structure above the device layer; a first etch-stop layer above the dielectric structure; a through-hole extending through the dielectric structure and the device layer, wherein a top portion of the through-hole extends through the first etch-stop layer; a guard ring structure above the first etch-stop layer and surrounding the top portion of the through-hole; a protective layer disposed above the guard ring structure; a second etch-stop layer conformally disposed above the top surface of the first etch-stop layer, the sidewalls of the guard ring structure, the sidewalls of the protective layer, and the top surface of the protective layer; and a dielectric layer of the second etch-stop layer. The top portion includes a height measured from the top surface of the dielectric structure. This height is between about 5 Å and about 15 Å. The through-hole is substantially a loop in top view and includes a diameter between about 2 µm and about 12 µm.

[0050] In some embodiments, the first etch-stop layer, the protective layer, and the second etch-stop layer comprise silicon carbonitride, aluminum nitride, or aluminum oxide. In some embodiments, the protective ring structure comprises silicon oxide. In some embodiments, the contact structure further comprises a metal line extending through the dielectric layer, the second etch-stop layer, and the protective layer to interface with the top surface of the via. In some embodiments, the metal line comprises a width, and the ratio of the diameter of the via to the width of the metal line is between about 0.9 and about 1.1.

[0051] The foregoing summary outlines features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various modifications, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0005] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to industry standard practice, the various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of various features may be increased or decreased arbitrarily for clarity of discussion. Figure 1 is a flowchart illustrating an embodiment of a method for forming substrate through-holes through an integrated circuit (IC) device structure according to various aspects of this disclosure. Figures 2 through 20 are partial cross-sectional views of work-in-progress (WIP) structures of various aspects of this disclosure undergoing the operation of the method shown in Figure 1. Figure 21 is a partial perspective top view of the through-hole and guard ring structure of various aspects of this disclosure. [Biomaterial Storage]

[0053] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method for manufacturing a contact structure, comprising the following steps: receiving a device structure, the device structure comprising: a substrate; a device layer above the substrate; and a plurality of interconnect layers above the device layer and including a via forming region; depositing a first etch-stop layer above the interconnect layers; depositing a first dielectric layer above the first etch-stop layer; depositing a second etch-stop layer above the first dielectric layer; depositing a second dielectric layer above the second etch-stop layer; forming a via opening through a depth of one of the second dielectric layer, the second etch-stop layer, the first dielectric layer, the first etch-stop layer, the via forming region, the device layer, and the substrate; depositing a metal filler layer above the second dielectric layer and the via opening; planarizing the metal filler layer to form a via structure and exposing the first dielectric layer; and depositing a protective layer above the via structure and the exposed first dielectric layer. The protective layer and the first dielectric layer are patterned to form a protective structure surrounding a portion of the via structure that rises above the first etch stop layer; and a third dielectric layer is deposited over the protective structure and the first etch stop layer.

2. The method as described in claim 1 further includes the following steps: depositing a third etch stop layer over the protective structure and the first etch stop layer before depositing the third dielectric layer.

3. The method as described in claim 2, wherein the step of depositing the third etch stop layer includes the following steps: conformally depositing the third etch stop layer above a top surface of the first etch stop layer, a plurality of sidewalls of the first dielectric layer, a plurality of sidewalls of the protective layer, and a top surface of the protective layer.

4. The method as described in claim 1, wherein the via forming region comprises a plurality of intermetallic dielectric layers and does not contain a plurality of conductive features.

5. A contact structure, comprising: A device layer, situated above a substrate; A dielectric structure is located above the device layer; a first etch-stop layer is located above the dielectric structure; a through-hole extends through the dielectric structure and the device layer, wherein a top portion of one of the through-holes rises above the first etch-stop layer; a guard ring structure includes the first etch-stop layer, a dielectric layer, a guard layer, and a second etch-stop layer, the guard ring structure surrounding the top portion of the through-hole and the first etch-stop layer being located below the guard ring structure; the guard layer is disposed above the guard ring structure; the second etch-stop layer is conformally disposed above a top surface of the first etch-stop layer, a plurality of sidewalls of the guard ring structure, a plurality of sidewalls of the guard layer, and a top surface of the guard layer; and the dielectric layer is located above the first etch-stop layer.

6. The contact structure as claimed in claim 5, wherein the perforation is substantially a loop in a top view and includes a diameter, wherein the protective ring structure includes a thickness measured from one sidewall of the perforation, wherein the ratio of the thickness to one of the diameters is between about 0.01 and about 0.

5.

7. The contact structure as described in claim 5, wherein the first thickness of one of the first etch-stop layers is less than the second thickness of one of the protective layers.

8. A contact structure, comprising: A device layer, situated above a substrate; A dielectric structure is located above the device layer; a first etch-stop layer is located above the dielectric structure; a through-hole extends through the dielectric structure and the device layer, wherein a top portion of the through-hole extends through the first etch-stop layer; a guard ring structure includes the first etch-stop layer, a dielectric layer, a guard layer, and a second etch-stop layer, the guard ring structure surrounding the top portion of the through-hole and the first etch-stop layer being located below the guard ring structure; the guard layer is disposed above the guard ring structure; the second etch-stop layer is conformally disposed above a top surface of the first etch-stop layer, a plurality of sidewalls of the guard ring structure, a plurality of sidewalls of the guard layer, and a top surface of the guard layer; and the dielectric layer is located above the first etch-stop layer, wherein the top portion includes a height measured from a top surface of the dielectric structure, wherein the height is between about 5 Å and about 15 Å, and wherein the through-hole is substantially a loop in a top view and includes a diameter between about 2 µm and about 12 µm.

9. The contact structure as described in claim 8, further comprising: A metal line extends through the dielectric layer, the second etch-stop layer, and the protective layer to interface with one of the top surfaces of the via.

10. The contact structure as claimed in claim 9, wherein the metal wire includes a width, and wherein the ratio of the diameter of the perforation to the width of the metal wire is between about 0.9 and about 1.1.

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