Non-volatile memory and method for trimming threshold voltage of string selection cell thereof

TWI937836BActive Publication Date: 2026-09-01MACRONIX INTERNATIONAL CO LTD
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Patent Information

Application Number
TW114117656
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-05-12
Publication Date
2026-09-01
Estimated Expiration
2045-05-11

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Abstract

This invention provides a critical voltage adjustment method for a non-volatile memory and its string select cells, applicable to high-capacity and high-performance three-dimensional NAND flash memory. A control circuit adjusts the critical voltages of multiple string select cells within a memory cell string, making the critical voltages of these string select cells different from each other. When adjusting the critical voltage of the first string select cell, a first programmed voltage is provided to the gate of the first string select cell to program the first string select cell. When adjusting the critical voltage of the second string select cell, a second programmed voltage, different from the first programmed voltage, is provided to the gate of the second string select cell to program the second string select cell.
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Claims

1. A non-volatile memory, comprising: A memory cell array includes multiple memory cells, wherein each of a plurality of word lines is coupled to a corresponding memory cell in each of the memory cells, each of a plurality of bit lines is coupled to an upper end of each of the memory cells in a corresponding row of the memory cell array, and each of a plurality of common source lines is coupled to a lower end of each of the memory cells in a corresponding column of the memory cell array. A current memory cell includes multiple string select cells, multiple memory cells, and a ground select switch. The string select cells of the current memory cell are connected between the memory cells of the current memory cell and the upper end of the current memory cell, and the ground select switch of the current memory cell is connected in series between the memory cells of the current memory cell and the lower end of the current memory cell; and a control circuit is coupled to the memory cell array, wherein... The control circuit performs a critical voltage adjustment on the string select cells of the current memory cell string so that the critical voltages of the string select cells of the current memory cell string differ from each other; and during a first programming period of performing the critical voltage adjustment on a first string select cell of the current memory cell string, the control circuit connects the memory cells of the current memory cell string to the ground selection switch, the control circuit provides a non-suppressed voltage to a current common source line connected to the current memory cell string among the common source lines, the control circuit provides a suppressed voltage to the other common source lines among the common source lines besides the current common source line, and the control circuit provides a first programming voltage to the The control circuit programs the gate of the first string select cell to program the first string select cell; and during a second programming of the critical voltage adjustment of a second string select cell among the string select cells of the current memory cell string, the control circuit turns on the memory cells of the current memory cell string and the ground selection switch, the control circuit provides the non-suppressed voltage to the current common source line among the common source lines connected to the current memory cell string, the control circuit provides the suppressed voltage to the other common source lines among the common source lines besides the current common source line, and the control circuit provides a second programming voltage different from the first programming voltage to the gate of the second string select cell to program the second string select cell.

2. The non-volatile memory as claimed in claim 1, wherein during a pre-conduction period prior to the first programming period, the control circuit turns on the first string select cell, the second string select cell, the memory cells and the ground select switch of the current memory cell string, the control circuit provides the non-suppressed voltage to the current common source line, and the control circuit provides the suppressed voltage to the other common source lines among the common source lines besides the current common source line.

3. The non-volatile memory as claimed in claim 1, wherein the current memory cell string further includes a terminal switch cell connected in series between the string select cells of the current memory cell string and the upper end of the current memory cell string, and the control circuit shuts off the terminal switch cell during the first programming of the first string select cell of the current memory cell string for the critical voltage adjustment.

4. The non-volatile memory as claimed in claim 3, wherein during the first programming of the critical voltage adjustment of the first string of select cells of the current memory cell string, the control circuit pulls up the voltage of a current bit line connected to the current memory cell string to turn off the terminal switch cell.

5. The non-volatile memory as claimed in claim 1, wherein the suppression voltage is greater than or equal to 5 volts, the non-suppression voltage is 0 volts, and the first programmed voltage and the second programmed voltage are two voltages between 16 volts and 26 volts.

6. A method for adjusting the critical voltage of a series selector cell, comprising: A threshold voltage adjustment is applied to multiple string select cells of a current memory string in a memory string array, such that the threshold voltages of the string select cells of the current memory string differ from each other. Each of multiple word lines is coupled to a corresponding memory cell in each of the multiple memory strings in the memory string array; each of multiple bit lines is coupled to an upper end of each of the memory strings in a corresponding row of the memory string array; and each of multiple common source lines is coupled to a lower end of each of the memory strings in a corresponding column of the memory string array. The current memory string further includes multiple memory cells and a ground selection switch. The string select cells of the current memory string are connected between the memory cells and the upper end of the current memory string, and the ground selection switch of the current memory string is connected in series between the memory cells and the lower end of the current memory string. The threshold voltage is applied to a first string select cell among the string select cells of the current memory string. During a first programming phase of the trimming, the memory cells of the current memory cell string and the ground selection switch are turned on, a non-suppressed voltage is provided to a current common source line connected to the current memory cell string among the common source lines, a suppressed voltage is provided to the other common source lines among the common source lines besides the current common source line, and a first programming voltage is provided to a gate of the first string select cell to program the first string select cell; and during a second programming phase of the threshold voltage trimming of a second string select cell among the string select cells of the current memory cell string, the memory cells of the current memory cell string and the ground selection switch are turned on, the non-suppressed voltage is provided to the current common source line connected to the current memory cell string among the common source lines, the suppressed voltage is provided to the other common source lines among the common source lines besides the current common source line, and a second programming voltage different from the first programming voltage is provided to a gate of the second string select cell to program the second string select cell.

7. The critical voltage adjustment method as described in claim 6 further includes: During a pre-conduction period prior to the first programming period, the first string select cell, the second string select cell, the memory cells, and the ground select switch of the current memory cell string are turned on, providing the non-suppressed voltage to the current common source line and providing the suppressed voltage to the other common source lines among the common source lines besides the current common source line.

8. The critical voltage adjustment method as claimed in claim 6, wherein the current memory cell string further includes an end switch cell connected between the string select cells of the current memory cell string and the upper end of the current memory cell string, and the critical voltage adjustment method further includes: During the first programming of the first string of selected cells of the current memory cell string, the terminal switch cell is turned off.

9. The critical voltage adjustment method as described in claim 8 further includes: During the first programming of the critical voltage adjustment of the first string of selected cells of the current memory cell string, the voltage of a current bit line connected to the current memory cell string is increased to turn off the terminal switch cell.

10. The critical voltage adjustment method as claimed in claim 6, wherein the suppression voltage is greater than or equal to 5 volts, the non-suppression voltage is 0 volts, and the first programmed voltage and the second programmed voltage are two voltages between 16 volts and 26 volts.

Citation Information

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