Semiconductor structure and manufacturing method of semiconductor structure

Abstract

This disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a substrate, an epitaxial layer, a diode string, a gate structure, and a source structure. The epitaxial layer is located above the substrate. The epitaxial layer has a doped region. The doped region extends from the top of the epitaxial layer toward the substrate. The diode string is located above the epitaxial layer. The gate structure is at least partially surrounded by the doped region and extends toward the substrate into the epitaxial layer. The gate structure includes a first polysilicon structure, a gate oxide layer, an insulating layer, and a second polysilicon structure. The gate oxide layer surrounds the polysilicon structure. The insulating layer is located above the first polysilicon structure and the gate oxide layer and extends between the doped region and the diode string. The second polysilicon structure is located above the first polysilicon structure and the gate oxide layer and is surrounded by the insulating layer. The source structure is adjacent to the doped region and the second polysilicon structure and is electrically coupled to the diode string via a first conductive plug.

Claims

1. A semiconductor structure comprising: a substrate; an epitaxial layer over the substrate, wherein the epitaxial layer has a doped region extending from the top of the epitaxial layer toward the substrate; A diode string, above the epitaxial layer, includes: A plurality of first doped regions having a first conductivity type, wherein a first conductive plug is adjacent to a first end of the plurality of first doped regions; The device comprises: a plurality of second doped regions having a second conductivity type, wherein the plurality of first doped regions and the plurality of second doped regions are alternately arranged; a gate structure, at least partially surrounded by the doped regions and extending into the epitaxial layer into the substrate, comprising: a first polysilicon structure; a gate oxide layer surrounding the polysilicon structure; an insulating layer above the first polysilicon structure and the gate oxide layer, extending between the doped regions and the diode string; a second polysilicon structure above the first polysilicon structure and the gate oxide layer and surrounded by the insulating layer, wherein the second polysilicon structure has the same doping concentration as the plurality of second doped regions; and a source structure adjacent to the doped regions and the second polysilicon structure, and electrically coupled to the diode string through a first conductive plug.

2. The semiconductor structure of claim 1, wherein the doped region comprises: a first lightly doped region; a second lightly doped region above the first lightly doped region; and a heavily doped region disposed on the first lightly doped region and surrounded by the second lightly doped region, wherein the source structure is adjacent to the second lightly doped region and the heavily doped region, and the doping concentration of the second lightly doped region is less than the doping concentration of the heavily doped region and greater than the doping concentration of the first lightly doped region.

3. The semiconductor structure as claimed in claim 2, wherein the second lightly doped region and the heavily doped region are electrically connected to a source electrode and together serve as the source structure.

4. The semiconductor structure of claim 1, wherein the gate structure further includes a thermal oxide layer, wherein the thermal oxide layer includes: a bottom portion above the first polysilicon structure; and a sidewall portion extending between the doped region and the insulating layer.

5. The semiconductor structure as claimed in claim 4, wherein the thickness of the insulating layer is greater than the thickness of the thermal oxide layer.

6. The semiconductor structure as claimed in claim 4, wherein the thickness of the bottom portion is greater than the thickness of the sidewall portion.

7. The semiconductor structure as claimed in claim 4, wherein the bottom portion does not contact the sidewall portion.

8. The semiconductor structure as claimed in claim 1, wherein the interface between each first doped region and the second doped region forms a PN junction.

9. The semiconductor structure as claimed in claim 1, wherein the second polysilicon structure has the second conductivity type.

10. The semiconductor structure as claimed in claim 1, wherein the plurality of second doped regions are composed of polysilicon.

11. The semiconductor structure as claimed in claim 1 further comprises: a gate electrode, electrically coupled to the first polysilicon structure above the diode string, and electrically coupled to a second end of the plurality of first doped regions via a second conductive plug.

12. The semiconductor structure of claim 1 further comprises: an intercalation oxide layer on the insulating layer, surrounding the source structure and the diode string, and covering the diode string.

13. The semiconductor structure of claim 1, wherein the thickness of the insulating layer on the first polysilicon structure is less than the thickness of the portion of the insulating layer extending between the doped region and the diode string.

14. The semiconductor structure of claim 13, wherein the thickness of the portion of the insulating layer extending between the doped region and the diode string is between approximately 300 angstroms and approximately 10,000 angstroms.

15. The semiconductor structure of claim 1, wherein the source structure comprises: a first conductive plug; a source electrode; a metal layer disposed on both sides of the source electrode; and a barrier metal layer surrounding the source electrode, the metal layer and the first conductive plug, and adjacent to the doped region, the second polysilicon structure and the diode string.

16. The semiconductor structure of claim 15, wherein the first conductive plug has the same material as the metal layer.

17. The semiconductor structure as claimed in claim 1, wherein the second polycrystalline silicon structure has a rectangular profile in a cross-sectional view.

18. The semiconductor structure of claim 1, wherein the second polycrystalline silicon structure has a triangular profile in a cross-sectional view.

19. The semiconductor structure of claim 1, wherein, in a cross-sectional view, the second polycrystalline silicon structure has arcuate sidewalls adjacent to the insulating layer.

20. A method of manufacturing a semiconductor structure, comprising: providing a substrate having an epitaxial layer thereon, wherein the epitaxial layer has a first lightly doped region extending from the top of the epitaxial layer toward the substrate; forming a trench extending from the top surface of the first lightly doped region toward the substrate beyond the first lightly doped region into the epitaxial layer; forming a gate oxide layer surrounding a first polysilicon structure in the trench; forming an insulating layer over the first polysilicon structure and the gate oxide layer, and extending to the top surface of the first lightly doped region; forming a polysilicon layer over the insulating layer, wherein the polysilicon layer fills the remaining space of the trench; A portion of the polycrystalline silicon layer is removed to simultaneously form a second polycrystalline silicon structure in the trench and a third polycrystalline silicon structure on the top surface of the first lightly doped region; a portion of the third polycrystalline silicon structure is converted into a plurality of first doped regions having a first conductivity type, while the remaining portion of the third polycrystalline silicon structure is a plurality of second doped regions having a second conductivity type, wherein the plurality of first doped regions and the plurality of second doped regions are alternately arranged to form a diode string, and the second polycrystalline silicon structure and the plurality of second doped regions have the same doping concentration; an interlayer oxide layer is formed on the insulating layer and the second polycrystalline silicon structure, surrounding and covering the diode string; And to form a source electrode that passes through the interlayer oxide layer and is adjacent to and electrically coupled to the second polycrystalline silicon structure.

21. The manufacturing method of claim 20, wherein the step of converting a portion of the third polycrystalline silicon structure into the plurality of first doped regions having the first conductivity type includes performing an ion implantation process, wherein the step of performing the ion implantation process further converts a first portion of the first lightly doped region into a second lightly doped region, wherein the doping concentration of the second lightly doped region is greater than the doping concentration of the first lightly doped region.

22. The manufacturing method of claim 21 further comprises: converting a second portion of the first lightly doped region into a heavily doped region, wherein the heavily doped region is surrounded by the second lightly doped region, and the top surface of the heavily doped region is coplanar with the top surface of the second lightly doped region.

23. The manufacturing method of claim 22, wherein the doping concentration of the heavily doped region is greater than the doping concentration of the second lightly doped region, wherein the second lightly doped region has the first conductivity type, and the heavily doped region and the first lightly doped region have the second conductivity type.

24. The manufacturing method as claimed in claim 22, wherein the source electrode is adjacent to the second lightly doped region and the heavily doped region.

25. The manufacturing method of claim 20 further comprises: forming a gate electrode over the interlayer oxide layer, wherein the source electrode is electrically coupled to a first end of the plurality of first doped regions, and the gate electrode is electrically coupled to a second end of the plurality of first doped regions.

26. The manufacturing method of claim 20, wherein the step of removing a portion of the polycrystalline silicon layer includes performing an anisotropic etching process, wherein performing the anisotropic etching process further removes a portion of the insulating layer.

27. The manufacturing method as claimed in claim 26, wherein after performing the anisotropic etching process, the thickness of the insulating layer under the third polysilicon structure is greater than the thickness of the insulating layer not covered by the third polysilicon structure.

28. The manufacturing method of claim 20 further comprises: performing a thermal oxidation process prior to forming the insulating layer to form a thermal oxide layer on the first polycrystalline silicon structure and on the first lightly doped region.

29. The manufacturing method of claim 28, wherein the step of performing the thermal oxidation process includes: consuming a portion of the first polycrystalline silicon structure to form a bottom portion of the thermal oxide layer; and consuming a portion of the first lightly doped region to form a sidewall portion of the thermal oxide layer.

30. The manufacturing method of claim 29, wherein the bottom portion does not contact the sidewall portion, and the insulating layer is at least partially not covered by the thermal oxidation layer.

31. The manufacturing method as claimed in claim 28, wherein the insulating layer is formed in a manner different from the thermal oxidation process.

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