Method of and device for generating layout diagram

Abstract

One embodiment of the method involves generating a via layout pattern for a semiconductor device layout plan prior to applying Optical Proximity Correction (OPC) processing. The method includes obtaining an initial layout plan comprising a first layout pattern indicating a first conductive structure, a second layout pattern indicating a second conductive structure, and an initial via layout pattern indicating electrical coupling between the first and second conductive structures. The method further includes deriving a first predicted pattern based on the first layout pattern, deriving a second predicted pattern based on the second layout pattern, and determining a modified via layout pattern indicating the via structures based on the first and second predicted patterns. The modified via layout pattern has a curved shape prior to applying Optical Proximity Correction (OPC).

Claims

1. A photomask for a layer of a semiconductor element based on the layout plan of the semiconductor element, comprising: substrate; The via masking pattern structure above the substrate corresponds to a via layout pattern included in the via layout diagram of the layout plan and indicates the via structure of the semiconductor element. The via structure connects a first conductive structure below the via structure and a second conductive structure above the via structure. The via layout pattern has a curved shape before the application of the optical proximity correction (OPC) process. The first conductive structure corresponds to a first predicted pattern that can be derived from a first layout pattern included in the first metallization layout diagram of the layout plan. The second conductive structure corresponds to a second predicted pattern that can be derived from a second layout pattern included in the second metallization layout diagram of the layout plan. The first predicted pattern and the second predicted pattern overlap each other and define an overlap region. The via layout pattern is located within the overlap region before the application of the optical proximity correction process.

2. The photomask as described in claim 1, wherein: The via layout pattern has an elliptical shape before the optical proximity correction process is applied.

3. The photomask as described in claim 1, wherein: The via layout pattern has a free shape before the optical proximity correction process is applied, and the free shape corresponds to having an irregular profile, asymmetry, or both.

4. The photomask as described in claim 1, further comprising: A set of dummy mask pattern structures above the substrate, the set of dummy mask pattern structures corresponding to a set of dummy layout patterns included in the via layout diagram of the layout plan, and each of the set of dummy layout patterns having a corresponding free shape.

5. A method for generating a via layout pattern of semiconductor devices prior to applying an optical proximity correction (OPC) process, comprising: The process involves obtaining an initial layout plan including: a first layout pattern included in a first metallization layout diagram and indicating a first conductive structure; a second layout pattern included in a second metallization layout diagram and indicating a second conductive structure; and an initial via layout pattern included in an initial via layout diagram and indicating the electrical coupling between the first and second conductive structures; deriving a first predicted pattern based on the first layout pattern; deriving a second predicted pattern based on the second layout pattern; determining a modified via layout pattern based on the first and second predicted patterns, the modified via layout pattern indicating a via structure of the semiconductor element, the via structure connecting a first conductive structure below the via structure and a second conductive structure above the via structure; and saving the via layout plan to a memory element of a process element, the via layout plan corresponding to replacing the initial via layout pattern in the initial via layout diagram with the modified via layout pattern, wherein the modified via layout pattern has a curved shape before applying the optical proximity correction process, wherein: the first and second predicted patterns overlap each other and define an overlap region, and the modified via layout pattern is located within the overlap region.

6. The method as described in request item 5, wherein: The determination of the modified via layout pattern includes determining the freeform profile of the modified via layout pattern based on reducing the difference between the freeform profile and the region profile of the overlapping area.

7. The method as described in request item 5, wherein: The modified through-hole layout pattern has an elliptical shape.

8. The method as described in request item 5, wherein: The modified through-hole layout pattern has a free shape, which corresponds to having an irregular profile, asymmetry, or both.

9. A process element for generating a via layout pattern of a semiconductor element prior to the application of an optical proximity correction (OPC) process, comprising: Memory components; The processing circuitry, coupled to the memory element, is configured to: obtain an initial layout plan including: a first layout pattern included in a first metallization layout diagram and indicating a first conductive structure; a second layout pattern included in a second metallization layout diagram and indicating a second conductive structure; and an initial via layout pattern included in an initial via layout diagram and indicating electrical coupling between the first conductive structure and the second conductive structure; derive a first predicted pattern based on the first layout pattern; derive a second predicted pattern based on the second layout pattern; determine a modified via layout pattern based on the first predicted pattern and the second predicted pattern, the modified via layout pattern indicating a via structure of the semiconductor element, the via structure connecting the first conductive structure below the via structure and the second conductive structure above the via structure; and save the via layout plan to the memory element, the via layout plan corresponding to replacing the initial via layout pattern in the initial via layout diagram with the modified via layout pattern, wherein the modified via layout pattern has a curved shape before the application of the optical proximity correction process, wherein: The first predicted pattern and the second predicted pattern overlap each other and define an overlapping region, and the modified via layout pattern is located within the overlapping region.

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