Integrated circuit, fabricating method thereof, and fabricating method of read-only memory transistor array on metallization stack of integrated circuit

Abstract

In a method for manufacturing integrated circuits, a plurality of logic circuit devices are formed in and / or on a semiconductor substrate. A metallization stack is formed on the semiconductor substrate. The metallization stack includes a plurality of patterned metal layers embedded in a dielectric material and a plurality of vias. A read-only memory (ROM) transistor array is formed on the metallization stack. The ROM transistor array is electrically connected to the vias of the metallization stack. The ROM transistor array may include a plurality of transistor channels, a plurality of source lines, and a plurality of drain lines, the transistor channels, source lines, and drain lines being formed from an amorphous silicon layer deposited at a temperature of 450°C or lower. The ROM transistor array manufacturing steps performed after the deposition of the amorphous silicon layer may also be performed at a temperature of 450°C or lower.

Claims

1. A method for manufacturing an integrated circuit, the method comprising: A plurality of logic circuit devices are formed in or on a semiconductor substrate; a metallization stack is formed on the semiconductor substrate, the metallization stack including a plurality of patterned metal layers and a plurality of vias embedded in a dielectric material; and a read-only memory transistor array is formed to contact the metallization stack, the read-only memory transistor array being electrically connected to the vias of the metallization stack, wherein an area of ​​the read-only memory transistor array at least partially overlaps an area of ​​the logic circuit devices.

2. The method as described in claim 1, wherein forming the read-only memory transistor array comprises: An amorphous silicon layer is disposed on the metallization stack; the amorphous silicon layer is doped to form a plurality of source lines and a plurality of drain lines of the read-only memory transistor array; a gate dielectric layer is disposed on the amorphous silicon layer; and a plurality of gate lines of the read-only memory transistor array are formed on the gate dielectric layer.

3. The method as described in claim 1, wherein forming the read-only memory transistor array includes storing data in the read-only memory transistor array by implanting a dopant to modify a plurality of threshold voltages of a plurality of pre-selected read-only memory transistors of the read-only memory transistor array.

4. The method as described in claim 1, wherein forming the read-only memory transistor array includes: The plurality of gate lines forming the read-only memory transistor array are on the metallization stack; A gate dielectric layer is provided on the gate lines; an amorphous silicon layer is provided on the metallization stack; and the amorphous silicon layer is doped to form a plurality of source lines and a plurality of drain lines of the read-only memory transistor array.

5. The method as described in claim 1, wherein the occupied area of ​​the read-only memory transistor array is equal to or entirely within the occupied area of ​​the logic circuit devices.

6. A method for manufacturing a read-only memory transistor array on a metallization stack of an integrated circuit, the method comprising: An amorphous silicon layer is disposed on the metallization stack; the amorphous silicon layer is doped to form a plurality of source lines and a plurality of drain lines of the read-only memory transistor array; a gate dielectric layer is disposed on the amorphous silicon layer, wherein the disposal of the gate dielectric layer is performed at a temperature of 450°C or lower; a polycrystalline silicon layer is disposed on the gate dielectric layer; and the polycrystalline silicon layer is processed to form a plurality of polycrystalline silicon gate lines of the read-only memory transistor array.

7. The method as described in claim 6, wherein the setting of the amorphous silicon layer and the setting and processing of the polycrystalline silicon layer are performed at a temperature of 450°C or lower.

8. The method as described in claim 6, further comprising: A dielectric layer is deposited on the polycrystalline silicon layer; And to form one or more metal connections in and / or on the dielectric layer to electrically connect the polysilicon gate lines of the read-only memory transistor array to the metallized stack.

9. An integrated circuit, comprising: A plurality of logic circuit devices are disposed in and / or on a semiconductor substrate; a metallization stack is disposed on the logic circuit devices, the metallization stack including a plurality of patterned metal layers and a plurality of vias embedded in a dielectric material; and a read-only memory transistor array contacts the metallization stack, the metallization stack being disposed between the read-only memory transistor array and the logic circuit devices, and the metallization stack being electrically connected to the read-only memory transistor array and the logic circuit devices.

10. The integrated circuit as described in claim 9, further comprising: A dielectric layer is disposed on the read-only memory transistor array, the dielectric layer includes at least one electrical path, the at least one electrical path is also electrically connected to the read-only memory transistor array and the logic circuit devices.

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