Semiconductor memory devices

Abstract

A suitable semiconductor memory device is provided. The semiconductor memory device includes: a plurality of first wirings, a plurality of second wirings, a first insulating member and a second insulating member disposed therebetween, a plurality of first semiconductor layers, a plurality of first gate electrodes electrically connected to the plurality of first wirings and facing the plurality of first semiconductor layers, a plurality of second semiconductor layers, a plurality of second gate electrodes electrically connected to the plurality of second wirings and facing the plurality of second semiconductor layers, a plurality of third semiconductor layers electrically connected to the plurality of second semiconductor layers, a plurality of third gate electrodes electrically connected to the plurality of first semiconductor layers and facing the plurality of third semiconductor layers, and a through-hole wiring electrically connected to the plurality of third semiconductor layers. In a specific cross-section, one end of the through-hole wiring is positioned between the sides corresponding to the first and second insulating members, while the other end is not positioned between these positions.

Claims

1. A semiconductor memory device comprising: a plurality of first wirings arranged side-by-side in a first direction and extending in a second direction intersecting the first direction; and a plurality of second wirings arranged side-by-side in the first direction and extending in the second direction, and arranged side-by-side with the plurality of first wirings in a third direction intersecting the first and second directions; and a first insulating member and a second insulating member disposed between the plurality of first wirings and the plurality of second wirings, arranged side-by-side in the second direction, and extending in the first direction... Extending in the aforementioned third direction; and a plurality of first semiconductor layers, disposed between the aforementioned first insulating member and the aforementioned second insulating member, arranged side-by-side in the aforementioned first direction, and extending in the aforementioned third direction; and a plurality of first gate electrodes, arranged side-by-side in the aforementioned first direction, and electrically connected to the aforementioned plurality of first wirings, and facing the aforementioned plurality of first semiconductor layers; and a first via wiring, extending in the aforementioned first direction, and electrically connected to the aforementioned plurality of first semiconductor layers; and A plurality of second semiconductor layers are disposed between the aforementioned first insulating member and the aforementioned second insulating member, arranged side-by-side in the aforementioned first direction, and extending in the aforementioned third direction; and a plurality of second gate electrodes are arranged side-by-side in the aforementioned first direction, and are electrically connected to the aforementioned plurality of second wirings, and are opposite to the aforementioned plurality of second semiconductor layers; and second via wirings extend in the aforementioned first direction and are electrically connected to the aforementioned plurality of second semiconductor layers; and a plurality of third semiconductor layers are disposed Between the aforementioned plurality of first semiconductor layers and the aforementioned plurality of second semiconductor layers, arranged side-by-side in the aforementioned first direction and extending in the aforementioned third direction, and respectively electrically connected to the aforementioned plurality of second semiconductor layers; and a plurality of third gate electrodes, arranged side-by-side in the aforementioned first direction and respectively electrically connected to the aforementioned plurality of first semiconductor layers, and facing the aforementioned plurality of third semiconductor layers; and a third via wiring, extending in the aforementioned first direction and electrically connected to the aforementioned plurality of third semiconductor layers. At a specific cross-section extending in the aforementioned second and third directions, the end of the aforementioned third through-hole wiring on one side in the aforementioned second direction is located between the first position in the aforementioned second direction corresponding to the side of the aforementioned second insulating member (as described above) and the second position in the aforementioned second direction corresponding to the side of the aforementioned first insulating member (as described above). The end of the aforementioned third through-hole wiring on the other side in the aforementioned second direction is not located between the first position and the second position.

2. The semiconductor memory device as described in claim 1, wherein, At the aforementioned specific cross-section, the side of one of the aforementioned plurality of third gate electrodes in the aforementioned second direction has a curved portion formed along a portion of the outer peripheral surface of the aforementioned third through-hole wiring.

3. The semiconductor memory device as described in claim 2, wherein, At the aforementioned specific cross-section, the side of the third gate electrode of the aforementioned plurality of third gate electrodes on the other side of the aforementioned second direction has a straight portion formed along the aforementioned second insulating member.

4. The semiconductor memory device as described in claim 1, wherein, At the aforementioned specific cross-section, the side surface of the aforementioned first insulating member on the side of the aforementioned second insulating member has: a straight first portion disposed at the aforementioned first position and extending in the aforementioned third direction; and a curved second portion continuous with the aforementioned first portion and formed along a portion of the outer peripheral surface of the aforementioned third through-hole wiring.

5. The semiconductor memory device as described in claim 4, wherein, At the aforementioned specific cross-section, the side of the aforementioned second insulating member on the side of the aforementioned first insulating member is disposed at the aforementioned second position and has a straight third portion extending in the aforementioned third direction.

6. The semiconductor memory device as described in claim 1, wherein, In the aforementioned specific cross-section, the end of the first through-hole wiring on one side in the aforementioned second direction is disposed between the aforementioned first position and the aforementioned second position, while the end of the first through-hole wiring on the other side in the aforementioned second direction is not disposed between the aforementioned first position and the aforementioned second position.

7. The semiconductor memory device as described in claim 6, wherein, At the aforementioned specific cross-section, the side surface of the aforementioned first insulating member or the aforementioned second insulating member has a curved portion formed along a portion of the outer peripheral surface of the aforementioned first through-hole wiring.

8. The semiconductor memory device as described in claim 1, wherein, In the aforementioned specific cross-section, the end of the aforementioned second through-hole wiring on one side in the aforementioned second direction is located between the aforementioned first position and the aforementioned second position, while the end of the aforementioned second through-hole wiring on the other side in the aforementioned second direction is not located between the aforementioned first position and the aforementioned second position.

9. The semiconductor memory device as described in claim 8, wherein, At the aforementioned specific cross-section, the side surface of the aforementioned first insulating member or the aforementioned second insulating member has a curved portion formed along a portion of the outer peripheral surface of the aforementioned second through-hole wiring.

10. The semiconductor memory device as described in claim 1, wherein, At the aforementioned specific cross-section, the aforementioned first insulating member is cut off in the aforementioned third direction via the aforementioned third through-hole wiring.

11. The semiconductor memory device as described in claim 1, wherein, The system includes: a fourth via wiring, which is disposed on the opposite side of the aforementioned third via wiring in the aforementioned second direction relative to the aforementioned plurality of third semiconductor layers, extends in the aforementioned first direction, and is electrically connected to the aforementioned plurality of third semiconductor layers. In the aforementioned specific cross-section, the end of the aforementioned fourth via wiring on one side in the aforementioned second direction is disposed between the aforementioned first position and the aforementioned second position, and the end of the aforementioned fourth via wiring on the other side in the aforementioned second direction is not disposed between the aforementioned first position and the aforementioned second position.

12. The semiconductor memory device as described in claim 11, wherein, At the aforementioned specific cross-section, the side surface of one of the aforementioned plurality of third gate electrodes in the aforementioned second direction has a curved portion formed along a portion of the outer peripheral surface of the aforementioned third through-hole wiring, and the side surface of the other of the aforementioned plurality of third gate electrodes in the aforementioned second direction has a curved portion formed along another portion of the outer peripheral surface of the aforementioned fourth through-hole wiring.

13. The semiconductor memory device as described in claim 1, wherein, The aforementioned plurality of third semiconductor layers are respectively facing one side and the other side of the aforementioned plurality of third gate electrodes in the aforementioned first direction.

14. The semiconductor memory device as described in claim 13, wherein, The system comprises: a plurality of fourth gate electrodes arranged side by side in the aforementioned first direction and electrically connected to the aforementioned plurality of third gate electrodes, and facing the aforementioned plurality of second semiconductor layers; the aforementioned plurality of second semiconductor layers facing one side and the other side of the aforementioned plurality of fourth gate electrodes in the aforementioned first direction; and the aforementioned plurality of second gate electrodes facing one side and the other side of the aforementioned plurality of second semiconductor layers in the aforementioned first direction.

15. The semiconductor memory device as described in claim 1, wherein, The aforementioned plurality of third gate electrodes are respectively facing one side and the other side of the aforementioned plurality of third semiconductor layers in the aforementioned first direction.

16. The semiconductor memory device as described in claim 15, wherein, The system comprises: a plurality of fifth gate electrodes arranged side by side in the aforementioned first direction and electrically connected to the aforementioned plurality of third gate electrodes, and facing the aforementioned plurality of second semiconductor layers; the aforementioned plurality of fifth gate electrodes facing one side and the other side of the aforementioned plurality of second semiconductor layers in the aforementioned first direction; and the aforementioned plurality of second gate electrodes facing one side and the other side of the aforementioned plurality of fifth gate electrodes in the aforementioned first direction.

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