Driving circuit and driving method thereof

Abstract

A driving circuit includes an upper-bridge transistor, a first lower-bridge transistor, a second lower-bridge transistor, and a control circuit. The upper-bridge transistor is coupled between an input voltage and a switching node. The first lower-bridge transistor is coupled between the switching node and a ground terminal. The second lower-bridge transistor is coupled between the switching node and a ground terminal. The control circuit periodically and individually turns on the upper-bridge transistor and the first lower-bridge transistor. After the first lower-bridge transistor is turned off, the control circuit continuously turns on the second lower-bridge transistor until the upper-bridge transistor is turned on, to eliminate the reverse recovery charge of the first lower-bridge transistor.

Description

[Technical Field]

[0001] The present invention relates to a driving circuit and a driving method thereof, and more particularly to a half-bridge driving circuit and a driving method thereof that excludes the reverse recovery charge of the lower bridge transistor. [Previous Technology]

[0002] Figure 1 is a schematic diagram of the power conversion circuit. As shown in Figure 1, the power conversion circuit 100 is a synchronous buck converter. When the upper bridge transistor QH is turned on, the charging current IC generated by the input voltage VIN flows through the upper bridge transistor QH, inductor L, and load LD to the ground terminal, where the output capacitor CO is used to maintain the output voltage VO. When the upper bridge transistor QH is turned off and the lower bridge transistor QL is turned on, the discharge current ID flows from the ground terminal through the lower bridge transistor QL, inductor L, and load LD. When the lower bridge transistor QL is turned off, the discharge current ID flows through the parasitic diode DP of the lower bridge transistor QL, causing a large number of minority carriers to accumulate at the drain and base terminals of the lower bridge transistor QL, forming a stored charge. When the upper bridge transistor QH is turned on again, the minority carriers accumulated at the drain and base terminals of the lower bridge transistor QL must be removed, and the removal of the accumulated minority carriers is called the reverse recovery charge.

[0003] In switching power conversion circuits, the reverse recovery charge of the switching elements has always been a major efficiency hazard. Since the reverse recovery charge cannot be reduced through circuitry, it has been largely ignored. However, with the increasing operating frequency of power conversion circuits, the impact of reverse recovery charge on efficiency has become increasingly severe, and it has long been a problem that must be addressed. [Summary of the Invention]

[0004] The present invention provides a driving circuit and driving method for eliminating reverse recovery charge of the lower bridge transistor. By dividing the lower bridge transistor into a first lower bridge transistor and a second lower bridge transistor, and delaying the turn-off of the second lower bridge transistor with a smaller size, it helps to eliminate the reverse recovery charge accumulated on the drain terminal of the lower bridge transistor, thereby improving the power conversion efficiency.

[0005] This invention proposes a driving circuit, including an upper-bridge transistor, a first lower-bridge transistor, a second lower-bridge transistor, and a control circuit. The upper-bridge transistor is coupled between an input voltage and a switching node. The first lower-bridge transistor is coupled between the switching node and a ground terminal. The second lower-bridge transistor is coupled between the switching node and the ground terminal. The control circuit periodically and individually turns on the upper-bridge transistor and the first lower-bridge transistor. After the first lower-bridge transistor is turned off, the control circuit continuously turns on the second lower-bridge transistor until the upper-bridge transistor is turned on, so as to eliminate the reverse recovery charge of the first lower-bridge transistor.

[0006] According to some embodiments of the present invention, when the upper bridge transistor is turned on, the control circuit turns off the second lower bridge transistor based on the voltage of the switching node.

[0007] According to some embodiments of the present invention, when the first lower bridge transistor is turned off and a delay time is delayed, the control circuit turns off the second lower bridge transistor.

[0008] According to some embodiments of the present invention, the aforementioned delay time is determined by a resistor and the parasitic capacitance at the gate terminal of the second lower bridge transistor.

[0009] According to some embodiments of the present invention, the size of the second lower bridge transistor is smaller than the size of the first lower bridge transistor.

[0010] According to other embodiments of the present invention, the on-resistance of the second lower-bridge transistor is greater than the on-resistance of the first lower-bridge transistor.

[0011] According to some embodiments of the present invention, the control circuit further includes a discharge control circuit. The discharge control circuit includes a clamping transistor and a control transistor. The clamping transistor provides a control signal to a control node based on a clamping voltage. The control transistor couples the gate terminal of the second lower bridge transistor to the ground terminal based on the control signal.

[0012] According to some embodiments of the present invention, the clamping transistor is used to limit the voltage level of the control signal to the clamping voltage minus the threshold voltage of the clamping transistor, so as to prevent the control signal from being too high and burning out the control transistor. When the upper bridge transistor is turned on, the clamping transistor enables the control signal based on the voltage of the switching node. The enabled control signal turns on the control transistor, so that the control transistor couples the gate terminal of the second lower bridge transistor to the ground terminal, thereby turning off the second lower bridge transistor.

[0013] According to some embodiments of the present invention, the discharge control circuit further includes a delay capacitor, a discharge resistor, and a delay resistor. The delay capacitor is coupled between the gate terminal of the second lower-bridge transistor and the ground terminal. The discharge resistor is coupled between the gate terminal of the second lower-bridge transistor and the ground terminal. The delay resistor is coupled between the gate terminal of the first lower-bridge transistor and the gate terminal of the second lower-bridge transistor.

[0014] According to some embodiments of the present invention, the sum of the delay capacitor and the parasitic capacitance at the gate terminal of the second lower-bridge transistor, and the product of the delay resistor, are used to determine the delay time from the turn-off of the first lower-bridge transistor to the turn-off of the second lower-bridge transistor. When the control transistor is turned off, the discharge resistor is used to couple the gate terminal of the second lower-bridge transistor to the ground terminal and discharge the delay capacitor.

[0015] According to some embodiments of the present invention, the above-mentioned upper bridge transistor, the above-mentioned first lower bridge transistor and the above-mentioned second lower bridge transistor system form a half-bridge drive circuit.

[0016] The present invention further proposes a driving method for driving a half-bridge driving circuit. The driving method includes: in a first driving time, turning on a first lower bridge transistor and a second lower bridge transistor of the half-bridge driving circuit and turning off an upper bridge transistor of the half-bridge driving circuit; in a dead time after the first driving time, turning off the first lower bridge transistor and the upper bridge transistor, and continuously turning on the second lower bridge transistor to eliminate the reverse recovery charge of the first lower bridge transistor; and in a second driving time after the dead time, turning off the second lower bridge transistor and turning on the upper bridge transistor.

[0017] According to some embodiments of the present invention, the upper bridge transistor is coupled between an input voltage and a switching node, and the first lower bridge transistor and the second lower bridge transistor are coupled between the switching node and a ground terminal. The step of turning off the second lower bridge transistor and turning on the upper bridge transistor further includes: turning off the second lower bridge transistor in response to the voltage of the switching node rising to a threshold voltage.

[0018] According to some embodiments of the present invention, the step of turning off the second lower-bridge transistor and turning on the upper-bridge transistor further includes: receiving the voltage of the switching node using the source terminal of a clamping transistor to generate a control signal; receiving a clamping voltage using the gate terminal of the clamping transistor to limit the voltage level of the control signal; and turning off the second lower-bridge transistor based on the control signal. When the control signal is enabled, the second lower-bridge transistor is turned off.

[0019] According to some embodiments of the present invention, the step of turning off the second lower bridge transistor and turning on the upper bridge transistor further includes: providing the control signal to the gate terminal of a control transistor; when the control signal is enabled, using the control transistor to couple the gate terminal of the second lower bridge transistor to the ground terminal, thereby turning off the second lower bridge transistor; and when the control signal is disabled, turning off the control transistor.

[0020] According to some embodiments of the present invention, after the upper bridge transistor is turned on, the second lower bridge transistor is turned off.

[0021] According to some embodiments of the present invention, there is a delay time between the turn-off of the first lower-bridge transistor and the turn-off of the second lower-bridge transistor. The delay time is determined by a delay resistor and the parasitic capacitance at the gate terminal of the second lower-bridge transistor.

[0022] According to other embodiments of the present invention, a delay capacitor is coupled between the gate terminal of the second lower-bridge transistor and a ground terminal. The delay time is determined by the product of the parasitic capacitance of the gate terminal of the second lower-bridge transistor, the sum of the delay capacitor, and the delay resistance.

[0023] According to some embodiments of the present invention, the first lower-bridge transistor and the second lower-bridge transistor system form a transistor array. The second lower-bridge transistor system is associated with the first lower-bridge transistor.

[0024] According to some embodiments of the present invention, the on-resistance of the first lower bridge transistor is less than the on-resistance of the second lower bridge transistor.

Implementation Method

[0026] The following description is an embodiment of this disclosure. Its purpose is to illustrate the general principles of this disclosure and should not be regarded as a limitation of this disclosure. The scope of this disclosure shall be defined by the claims.

[0027] It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of this disclosure. The specific examples and arrangements of components described below are only used to briefly illustrate the spirit of this disclosure and are not intended to limit the scope of this disclosure. Furthermore, the same component symbols or words may be used repeatedly in multiple examples in the following description. However, the purpose of repetition is only to provide a simplified and clear explanation and is not intended to limit the relationship between the multiple embodiments and / or configurations discussed below.

[0028] Furthermore, the description in the following specification of a feature being connected to, coupled to, and / or formed on another feature may actually include multiple different embodiments, including the features being in direct contact, or including other additional features formed between the features, such that the features are not in direct contact.

[0029] Furthermore, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the arrangement of the diagram is flipped so that it is upside down, the element described as being on the "lower" side will become the element on the "higher" side.

[0030] It is understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or portions. Therefore, a first element, component, region, layer, and / or portion discussed below may be referred to as a second element, component, region, layer, and / or portion without departing from the teachings of some embodiments disclosed herein.

[0031] Some embodiments disclosed herein can be understood in conjunction with the accompanying drawings, which are also considered part of the description of the embodiments disclosed herein. It should be understood that the drawings of the embodiments disclosed herein are not drawn to scale with actual devices and components. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments disclosed herein. Furthermore, the structures and devices in the drawings are drawn schematically to clearly show the features of the embodiments disclosed herein.

[0032] Here, the terms "about," "approximately," and "roughly" generally mean within 20%, more preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantities given here are approximate quantities, that is, even without specific explanation of "about," "approximately," or "roughly," the meaning of "about," "approximately," or "roughly" may still be implied.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0034] In some embodiments disclosed herein, terms such as "connection" and "interconnection" used to refer to joining or connecting, unless otherwise defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, wherein other structures are disposed between the two structures. Furthermore, these terms regarding joining or connecting may also include situations where both structures are movable or both structures are fixed.

[0035] In the diagram, similar elements and / or features may have the same element symbol. Various elements of the same type may be distinguished by adding letters or numbers after the element symbol to differentiate similar elements and / or similar features.

[0036] Figure 2 shows a circuit diagram of a driving circuit according to an embodiment of the present invention. As shown in Figure 2, the driving circuit 200 includes an upper bridge transistor QH, a first lower bridge transistor QL1, a second lower bridge transistor QL2, and a control circuit 210. Compared with the power conversion circuit 100 in Figure 1, the lower bridge transistor QL in Figure 1 is replaced with the first lower bridge transistor QL1 and the second lower bridge transistor QL2.

[0037] According to some embodiments of the present invention, the first lower-bridge transistor QL1 and the second lower-bridge transistor QL2 form a transistor array, and the second lower-bridge transistor QL2 is associated with the first lower-bridge transistor QL1. Furthermore, the parasitic diode DP is a parasitic diode generated by the first lower-bridge transistor QL1 and the second lower-bridge transistor QL2. According to some embodiments of the present invention, the size of the first lower-bridge transistor QL1 is larger than the size of the second lower-bridge transistor QL2.

[0038] According to some embodiments of the present invention, the on-resistance of the first lower-bridge transistor QL1 is less than the on-resistance of the second lower-bridge transistor QL2. According to some embodiments of the present invention, the on-resistance of the second lower-bridge transistor QL2 is more than five times the on-resistance of the first lower-bridge transistor QL1. According to some embodiments of the present invention, the lower-bridge transistor QL in Figure 1 is divided into a first lower-bridge transistor QL1 and a second lower-bridge transistor QL2, and the size of the first lower-bridge transistor QL1 is larger than the size of the second lower-bridge transistor QL2. In other words, the lower-bridge transistor QL in Figure 1 is divided into a first lower-bridge transistor QL1 and a second lower-bridge transistor QL2, wherein the on-resistance of the second lower-bridge transistor QL2 is more than five times the on-resistance of the first lower-bridge transistor QL1.

[0039] According to some embodiments of the present invention, the size or on-resistance of the second lower bridge transistor QL2 is related to the reverse recovery charge, which will be described in detail below. The control circuit 210 includes a non-overlapping circuit 211 and a discharge control circuit 212. The non-overlapping circuit 211 generates a first signal S1 and a second signal S2 based on the upper bridge drive signal HS and the lower bridge drive signal LS, and includes a first inverter INV1, a first gate AND1, a second inverter INV2, and a second gate AND2.

[0040] According to one embodiment of the present invention, when both the first signal S1 and the second signal S2 are disabled and the upper bridge drive signal HS is enabled, the first inverter INV1 inverts the disabled second signal S2 to generate an enabled second inverted signal S2B. The first AND gate AND1 performs a logical AND operation on the enabled upper bridge drive signal HS and the enabled second inverted signal S2B to generate an enabled first signal S1, causing the upper bridge transistor QH to be turned on based on the enabled first signal S1. According to another embodiment of the present invention, when the upper bridge drive signal HS is disabled and the lower bridge drive signal LS is disabled (i.e., low voltage level), both the first signal S1 and the second signal S2 are disabled.

[0041] According to another embodiment of the present invention, when the upper bridge drive signal HS is in a disabled state and the lower bridge drive signal LS is in an enabled state, the second inverter INV2 inverts the disabled first signal S1 to generate an enabled first inverted signal S1B. The second AND gate AND2 performs a logical AND operation on the enabled first inverted signal S1B and the enabled lower bridge drive signal LS to generate an enabled second signal S2, causing the first lower bridge transistor QL1 to be turned on based on the enabled second signal S2. In other words, the non-overlapping circuit 211 is used to ensure that the upper bridge transistor QH and the first lower bridge transistor QL1 will not be turned on simultaneously.

[0042] The discharge control circuit 212 includes a delay resistor RDL, a delay capacitor CDL, a clamping transistor QCL, a control transistor QCNL, and a discharge resistor RDG. The delay resistor RDL is coupled between the gate terminals of the first lower-bridge transistor QL1 and the gate terminals of the second lower-bridge transistor QL2, and the delay capacitor CDL is coupled between the gate terminal of the second lower-bridge transistor QL2 and the ground terminal. The delay resistor RDL and the delay capacitor CDL are used to delay the second signal S2 to generate a second delayed signal S2D.

[0043] According to some embodiments of the present invention, the delay time from the turn-off of the first lower-bridge transistor QL1 to the turn-off of the second lower-bridge transistor QL2 is determined by the product of the delay capacitor CDL, the parasitic capacitance at the gate terminal of the second lower-bridge transistor QL2, and the delay resistor RDL. According to other embodiments of the present invention, the delay capacitor CDL may be omitted, and the delay time from the turn-off of the first lower-bridge transistor QL1 to the turn-off of the second lower-bridge transistor QL2 may be determined solely by the product of the delay resistor RDL and the parasitic capacitance at the gate terminal of the second lower-bridge transistor QL2.

[0044] The clamping transistor QCL, based on the clamping voltage VCL, provides the voltage of the switching node SW to the control node NCNL to generate the control signal SCNL. The control transistor QCNL, based on the control signal SCNL, couples the second delay signal S2D ​​to the ground terminal, thereby turning off the second lower bridge transistor QL2.

[0045] The discharge resistor RDG is coupled between the gate terminal of the second lower-bridge transistor QL2 and the ground terminal, so as to continuously couple the gate terminal of the second lower-bridge transistor QL2 to the ground terminal when the control transistor QCNL is turned off. According to one embodiment of the present invention, when the control transistor QCNL is turned off, the discharge resistor RDG is used to discharge the delay capacitor CDL, thereby turning off the second lower-bridge transistor QL2.

[0046] According to some embodiments of the present invention, when the upper bridge transistor QH is turned on, the upper bridge transistor QH provides the input voltage VIN to the switching node SW, causing the voltage of the switching node SW to rise. The clamping transistor QCL generates a control signal SCNL based on the clamping voltage VCL and the voltage of the switching node SW. When the voltage of the switching node SW exceeds the threshold voltage of the control transistor QCNL, the control transistor QCNL turns on and couples the second delay signal S2D ​​to the ground terminal, thereby turning off the second lower bridge transistor QL2.

[0047] Furthermore, since the input voltage VIN directly driving the control transistor QCNL may cause the control transistor QCNL to burn out, the clamping voltage VCL is used to limit the voltage level of the control signal SCNL to below the clamping voltage VCL minus the threshold voltage of the clamping transistor QCL, thereby protecting the control transistor QCNL from burning out. According to some embodiments of the present invention, the upper bridge transistor QH, the first lower bridge transistor QL1, and the second lower bridge transistor QL2 in Figure 2 form a half-bridge drive circuit, and the discharge control circuit 212 is used to control the timing of the second lower bridge transistor QL2 being turned on and off.

[0048] Figure 3 shows a waveform diagram of a drive circuit according to one embodiment of the present invention. The following description of the waveform diagram 300 in Figure 3 will be provided in conjunction with the drive circuit 200 in Figure 2 for detailed explanation.

[0049] As shown in Figure 3, between the initial time point T0 and the first time point T1, both the second signal S2 and the second delayed signal S2D ​​are enabled, causing both the first lower bridge transistor QL1 and the second lower bridge transistor QL2 to be turned on. When the second signal S2 transitions from a high logic level to a low logic level at the first time point T1, the first lower bridge transistor QL1 is turned off, while the second lower bridge transistor QL2 remains on.

[0050] In other words, at the first time point T1, the first lower-bridge transistor QL1 is turned off. The delay resistor RDL, the delay capacitor CDL, and the parasitic capacitance at the gate terminal of the second lower-bridge transistor QL2 generate a delay time to keep the second lower-bridge transistor QL2 continuously conducting between the first time point T1 and the second time point T2, so as to eliminate the reverse recovery charge accumulated at the drain terminals of the first lower-bridge transistor QL1 and the second lower-bridge transistor QL2.

[0051] At the second time point T2, the upper bridge transistor QH is turned on, causing the voltage of the switching node SW to rise. As shown in Figure 2, when the upper bridge transistor QH is turned on, it provides the input voltage VIN to the switching node SW, causing the voltage of the switching node SW to rise. The rising voltage of the switching node SW is clamped by the clamping transistor QCL and the control transistor QCNL, pulling the second delay signal S2D ​​down to a low logic level, thereby turning off the second lower bridge transistor QL2. According to one embodiment of the present invention, when the voltage of the switching node SW exceeds the threshold voltage of the control transistor QCNL, the control transistor QCNL is turned on and the second delay signal S2D ​​is disabled, thereby turning off the second lower bridge transistor QL2.

[0052] As shown in Figure 3, when the second delayed signal S2D ​​switches to a low logic level at the third time point T3, the second lower bridge transistor QL2 is turned off. According to some embodiments of the present invention, the length from the second time point T2 to the third time point T3 is the delay time required for the upper bridge transistor QH to turn on until the voltage of the switching node SW rises and turns off the second lower bridge transistor QL2.

[0053] According to some embodiments of the present invention, the delay time generated by the delay resistor RDL, the delay capacitor CDL, and the parasitic capacitance at the gate terminal of the second lower-bridge transistor QL2 is not less than the length from the first time point T1 to the second time point T2. In the embodiment shown in Figure 3, the delay time TDLY generated by the delay resistor RDL, the delay capacitor CDL, and the parasitic capacitance at the gate terminal of the second lower-bridge transistor QL2 can be the length from the first time point T1 to the third time point T3.

[0054] According to other embodiments of the present invention, the delay time generated by the delay resistor RDL, the delay capacitor CDL, and the parasitic capacitance at the gate terminal of the second lower-bridge transistor QL2 may also exceed the length from the first time point T1 to the third time point T3. According to one embodiment of the present invention, the period between the first time point T1 and the second time point T2 is the dead time during which both the upper-bridge transistor QH and the first lower-bridge transistor QL1 are turned off. According to some embodiments of the present invention, the size or on-resistance of the second lower-bridge transistor QL2 is adjusted so that the reverse recovery charge can be completely eliminated between the first time point T1 and the second time point T2 (i.e., the dead time). In other words, the size or on-resistance of the second lower-bridge transistor QL2 is related to the reverse recovery charge.

[0055] According to one embodiment of the present invention, when the reverse recovery charge increases, the size of the second lower bridge transistor QL2 is increased to reduce the on-resistance of the second lower bridge transistor QL2, so that the reverse recovery charge accumulated at the drain terminals of the first lower bridge transistor QL1 and the second lower bridge transistor QL2 can be completely eliminated between the first time point T1 and the second time point T2.

[0056] According to another embodiment of the present invention, when the reverse recovery charge decreases, the size of the second lower bridge transistor QL2 is reduced to increase the on-resistance of the second lower bridge transistor QL2, so that not only is the reverse recovery charge completely eliminated between the first time point T1 and the second time point T2, but also the power loss caused by the simultaneous conduction of the upper bridge transistor QH and the second lower bridge transistor QL2 between the second time point T2 and the third time point T3 is reduced, thereby improving the power conversion efficiency.

[0057] Since the second lower bridge transistor QL2 continues to conduct after the first lower bridge transistor QL1 is turned off, it helps to eliminate the reverse recovery charge accumulated at the drain terminals (i.e., the switching node SW in Figure 2) of the first lower bridge transistor QL1 and the second lower bridge transistor QL2, thereby improving the power conversion efficiency.

[0058] Figure 4 shows a circuit diagram of a power conversion circuit according to one embodiment of the present invention. As shown in Figure 4, the power conversion circuit 400 includes a drive circuit 410, an inductor L, and an output capacitor CO. According to some embodiments of the present invention, the drive circuit 410 corresponds to the drive circuit 200 in Figure 2. The inductor L is coupled between the switching node SW and the output voltage VO, and the output capacitor CO is coupled between the output voltage VO and the ground terminal.

[0059] According to one embodiment of the present invention, the power conversion circuit 400 is a synchronous buck converter. In other words, the driving circuit 200 in Figure 2 can be used to drive the synchronous buck converter and can effectively eliminate the reverse recovery charge of the lower bridge transistor, thereby improving the power conversion efficiency.

[0060] Figure 5 shows a circuit diagram of a motor drive circuit according to another embodiment of the present invention. As shown in Figure 5, the motor drive circuit 500 includes a first drive circuit 510, a second drive circuit 520, a third drive circuit 530, and a motor 540. According to some embodiments of the present invention, the first drive circuit 510, the second drive circuit 520, and the third drive circuit 530 all correspond to the drive circuit 200 in Figure 2.

[0061] In Figure 5, only one of the first driving circuit 510, the second driving circuit 520 and the third driving circuit 530 is shown for illustration and explanation, including the upper bridge transistor QH, the first lower bridge transistor QL1, the second lower bridge transistor QL2 and the discharge control circuit 212. The first driving circuit 510, the second driving circuit 520 and the third driving circuit 530 may include or include the non-overlapping circuit 211.

[0062] As shown in Figure 5, the switching nodes SW of the first driving circuit 510, the second driving circuit 520, and the third driving circuit 530 respectively generate a first driving signal SA, a second driving signal SB, and a third driving signal SC to drive the motor 540. According to some embodiments of the present invention, since the second lower bridge driving transistor QL2 of the first driving circuit 510, the second driving circuit 520, and the third driving circuit 530 is used to eliminate the reverse recovery charge accumulated at the drain terminals of the first lower bridge transistor QL1 and the second lower bridge transistor QL2, the efficiency of the driving motor 540 will be greatly improved.

[0063] Figure 6 shows a flowchart of the driving method according to one embodiment of the present invention. The following description of flowchart 600 will be provided in conjunction with the driving circuit 200 in Figure 2 and the waveform diagram 300 in Figure 3 for detailed explanation. According to some embodiments of the present invention, the upper bridge transistor QH, the first lower bridge transistor QL1, and the second lower bridge transistor QL2 in Figure 2 form a half-bridge driving circuit. Therefore, the driving method 600 can also be considered as a driving method for driving the half-bridge driving circuit including the upper bridge transistor QH, the first lower bridge transistor QL1, and the second lower bridge transistor QL2.

[0064] First, during the first driving time, the first lower bridge transistor QL1 and the second lower bridge transistor QL2 of the half-bridge driving circuit are turned on, while the upper bridge transistor QH of the half-bridge driving circuit is turned off (step S610). In the embodiment of Figure 3, the first driving time is between the initial time point T0 and the first time point T1. During the dead time after the first driving time, the first lower bridge transistor QL1 and the upper bridge transistor QH are turned off, while the second lower bridge transistor QL1 is continuously turned on (step S620), thereby eliminating the reverse recovery charge accumulated at the drain terminals of the first lower bridge transistor QL1 and the second lower bridge transistor QL2. In the embodiment of Figure 3, the dead time is between the first time point T1 and the second time point T2.

[0065] During the second drive time after the dead time, the second lower bridge transistor QL2 is turned off and the upper bridge transistor QH is turned on (step S630). In the embodiment of Figure 3, the second drive time is after the third time point T3. According to some embodiments of the present invention, as shown in Figure 2, the second lower bridge transistor QL2 is turned off based on the rising voltage of the switching node SW. Therefore, between the second time point T2 and the third time point T3 in Figure 3, the upper bridge transistor QH and the second lower bridge transistor QL2 will be turned on simultaneously for a brief period of time, and after the third time point T3, only the upper bridge transistor QH is turned on while the first lower bridge transistor QL1 and the second lower bridge transistor QL2 are both turned off.

[0066] In the embodiments of Figures 2 and 3, the upper bridge transistor QH is turned on at the second time point T2, causing the voltage of the switching node SW to rise. The rising voltage of the switching node SW turns off the second lower bridge transistor QL2 at the third time point T3, and the second driving time begins. According to some embodiments of the present invention, the size or on-resistance of the second lower bridge transistor QL2 can be adjusted so that the reverse recovery charge can be completely eliminated from the first time point T1 to the second time point T2, and the power loss caused by the simultaneous conduction of the upper bridge transistor QH and the second lower bridge transistor QL2 between the second time point T2 and the third time point T3 can be controlled, so as to obtain the best power conversion efficiency.

[0067] The present invention provides a driving circuit and driving method for eliminating reverse recovery charge of the lower bridge transistor. By dividing the lower bridge transistor into a first lower bridge transistor and a second lower bridge transistor, and delaying the turn-off of the second lower bridge transistor with a smaller size, it helps to eliminate the reverse recovery charge accumulated on the drain terminal of the lower bridge transistor, thereby improving the power conversion efficiency.

[0068] Although the embodiments and advantages of this disclosure have been disclosed above, it should be understood that anyone skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of this specification. Anyone skilled in the art can understand from the disclosure of some embodiments of this disclosure the current or future development of processes, machines, manufacturing, material composition, apparatus, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claim claims and embodiments. [Simplified Explanation of the Diagram]

[0025] Figure 1 shows a schematic diagram of a power conversion circuit; Figure 2 shows a circuit diagram of a drive circuit according to one embodiment of the present invention; Figure 3 shows a waveform diagram of a drive circuit according to one embodiment of the present invention; Figure 4 shows a circuit diagram of a power conversion circuit according to one embodiment of the present invention; Figure 5 shows a circuit diagram of a motor drive circuit according to another embodiment of the present invention; and Figure 6 shows a flowchart of a drive method according to one embodiment of the present invention.

Claims

1. A driving circuit, comprising: An upper-bridge transistor is coupled between an input voltage and a switching node; A first lower bridge transistor is coupled between the switching node and a ground terminal; a second lower bridge transistor is coupled between the switching node and the ground terminal; and a control circuit periodically and individually turns on the upper bridge transistor and the first lower bridge transistor; wherein after the first lower bridge transistor is turned off, the control circuit continues to turn on the second lower bridge transistor until the upper bridge transistor is turned on, so as to eliminate the reverse recovery charge of the first lower bridge transistor.

2. The driving circuit of claim 1, wherein when the upper bridge transistor is turned on, the control circuit turns off the second lower bridge transistor based on the voltage of the switching node.

3. The driving circuit of claim 1, wherein when the first lower bridge transistor is turned off and after a delay of a certain time, the control circuit turns off the second lower bridge transistor.

4. The drive circuit of claim 3, wherein the aforementioned delay time is determined by a resistor and the parasitic capacitance at the gate terminal of the second lower bridge transistor.

5. The driving circuit of claim 1, wherein the size of the second lower bridge transistor is smaller than the size of the first lower bridge transistor.

6. The driving circuit of claim 1, wherein the on-resistance of the second lower bridge transistor is greater than the on-resistance of the first lower bridge transistor.

7. The drive circuit of claim 1, wherein the control circuit further includes: A discharge control circuit includes: a clamping transistor that provides a control signal to a control node based on a clamping voltage; and a control transistor that couples the gate of the second lower bridge transistor to the ground terminal based on the control signal.

8. The drive circuit of claim 7, wherein the clamping transistor is used to limit the voltage level of the control signal to the clamping voltage minus the threshold voltage of the clamping transistor, so as to prevent the control signal from being too high and burning out the control transistor; wherein when the upper bridge transistor is turned on, the clamping transistor enables the control signal based on the voltage of the switching node; wherein the enabled control signal turns on the control transistor, so that the control transistor couples the gate terminal of the second lower bridge transistor to the ground terminal, thereby turning off the second lower bridge transistor.

9. The drive circuit of claim 7, wherein the discharge control circuit further comprises: A delay capacitor is coupled between the gate terminal of the second lower-bridge transistor and the ground terminal; a discharge resistor is coupled between the gate terminal of the second lower-bridge transistor and the ground terminal; and a delay resistor is coupled between the gate terminal of the first lower-bridge transistor and the gate terminal of the second lower-bridge transistor.

10. The driving circuit of claim 9, wherein the sum of the delay capacitor and the parasitic capacitance at the gate terminal of the second lower bridge transistor and the product of the delay resistor are used to determine the delay time from the turn-off of the first lower bridge transistor to the turn-off of the second lower bridge transistor; wherein when the control transistor is turned off, the discharge resistor is used to couple the gate terminal of the second lower bridge transistor to the ground terminal and discharge the delay capacitor.

11. The driving circuit of claim 1, wherein the upper bridge transistor, the first lower bridge transistor, and the second lower bridge transistor system form a half-bridge driving circuit.

12. A driving method for driving a half-bridge driving circuit, wherein the driving method includes: During a first driving time, a first lower bridge transistor and a second lower bridge transistor of the aforementioned half-bridge driving circuit are turned on, and an upper bridge transistor of the aforementioned half-bridge driving circuit is turned off; during a dead time after the first driving time, the first lower bridge transistor and the aforementioned upper bridge transistor are turned off, and the second lower bridge transistor is continuously turned on to eliminate the reverse recovery charge of the first lower bridge transistor; and during a second driving time after the aforementioned dead time, the second lower bridge transistor is turned off and the aforementioned upper bridge transistor is turned on.

13. The driving method of claim 12, wherein the upper bridge transistor is coupled between an input voltage and a switching node, and the first lower bridge transistor and the second lower bridge transistor are coupled between the switching node and a ground terminal; wherein the step of turning off the second lower bridge transistor and turning on the upper bridge transistor further includes: In response to the voltage at the aforementioned switching node rising to a threshold voltage, the aforementioned second lower bridge transistor is turned off.

14. The driving method of claim 13, wherein the step of turning off the second lower bridge transistor and turning on the upper bridge transistor further includes: A control signal is generated by receiving the voltage of the switching node at the source terminal of a clamping transistor; a clamping voltage is received at the gate terminal of the clamping transistor to limit the voltage level of the control signal; and the second lower bridge transistor is turned off based on the control signal; wherein the second lower bridge transistor is turned off when the control signal is enabled.

15. The driving method of claim 14, wherein the step of turning off the second lower bridge transistor and turning on the upper bridge transistor further includes: The control signal is provided to the gate terminal of a control transistor; when the control signal is enabled, the gate terminal of the second lower bridge transistor is coupled to the ground terminal using the control transistor, thereby turning off the second lower bridge transistor; and when the control signal is disabled, the control transistor is turned off.

16. The driving method of claim 12, wherein after the upper bridge transistor is turned on, the second lower bridge transistor is turned off.

17. The driving method of claim 12, wherein there is a delay time between the turn-off of the first lower-bridge transistor and the turn-off of the second lower-bridge transistor; wherein the delay time is determined by a delay resistor and the parasitic capacitance at the gate terminal of the second lower-bridge transistor.

18. The driving method of claim 17, wherein a delay capacitor is coupled between the gate terminal of the second lower bridge transistor and a ground terminal; wherein the delay time is determined by the product of the parasitic capacitance of the gate terminal of the second lower bridge transistor, the sum of the delay capacitor, and the delay resistance.

19. The driving method of claim 12, wherein the first lower-bridge transistor and the second lower-bridge transistor system form a transistor array; wherein the second lower-bridge transistor system is associated with the first lower-bridge transistor.

20. The driving method of claim 12, wherein the on-resistance of the first lower-bridge transistor is less than the on-resistance of the second lower-bridge transistor.

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