Image sensor integrated chip
Patent Information
- Application Number
- TW114121990
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2025-06-12
- Publication Date
- 2026-09-01
- Estimated Expiration
- 2045-06-11
Smart Images
Figure TWG2TB001908877_001 
Figure TWG2TB001908877_002 
Figure TWG2TB001908877_003
Abstract
Claims
1. An image sensor integrated chip, comprising: A substrate includes a first surface and a second surface opposite to the first surface, wherein the substrate includes a pixel region extending from the second surface into the substrate; An image sensing element is disposed in the pixel area of the substrate; a first gate structure and a second gate structure are disposed on the first surface of the substrate and spaced apart from each other; a memory node is disposed between the first gate structure and the second gate structure and extends from the first surface of the substrate into the substrate; an insulating layer is embedded in the substrate and disposed between the memory node and the image sensing element. A device isolation structure extends from a first surface of the substrate into the substrate to define an active region in the substrate, wherein a first gate structure, a second gate structure, and the memory node are disposed in the active region, and the device isolation structure is in contact with the insulating layer; and a pixel isolation structure extends from a second surface of the substrate into the substrate to define a pixel region in the substrate, wherein the pixel isolation structure includes a portion in contact with the insulating layer and a portion not in contact with the insulating layer, wherein the image sensing element includes a first doped region extending from the second surface into the substrate and a second doped region extending from the first doped region toward the first gate structure, the first doped region including a first portion overlapping the insulating layer in a vertical direction perpendicular to the second surface and a second portion not overlapping the insulating layer in the vertical direction, the second doped region being between and spaced apart from the first gate structure and the second portion of the first doped region, the second doped region overlapping and spaced apart from the insulating layer in a horizontal direction horizontal to the second surface, and the doping concentration of the first doped region being less than the doping concentration of the second doped region.
2. The image sensor integrated wafer as claimed in claim 1, wherein the first portion of the first doped region is spaced apart from the insulating layer in the vertical direction.
3. The image sensor integrated wafer as claimed in claim 1, wherein the substrate includes a floating diffusion node between the second gate structure and the device isolation structure, and the floating diffusion node overlaps the insulating layer in a direction perpendicular to the first surface.
4. The image sensor integrated wafer as claimed in claim 3, wherein the first portion of the first doped region overlaps with the memory node and the floating diffusion node in the vertical direction.
5. The image sensor integrated chip as claimed in claim 3, wherein the first gate structure includes a vertical transfer gate (VTG) electrode, and the second gate structure includes a VTG electrode or a horizontal transfer gate electrode.
6. The image sensor integrated wafer as claimed in claim 1, wherein the insulating layer includes an oxide layer.
Citation Information
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