Pixel circuit for non-display area of display panel

TWI937891BActive Publication Date: 2026-09-01AU OPTRONICS CORP
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Patent Information

Application Number
TW114122113
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-06-12
Publication Date
2026-09-01
Estimated Expiration
2045-06-11

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    Figure TWG2TB001908879_003
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Abstract

A pixel circuit for a non-display area of ​​a display panel includes first, second, and third switching components, a latching circuit, and a pixel capacitor. The first switching component transmits a data voltage to a first node based on a gate signal. A first terminal of the second switching component is coupled to the first node, and its second terminal receives the voltage signal. A first terminal of the third switching component is coupled to the first node, and its second terminal is coupled to a third terminal of the second switching component, also receiving the voltage signal. A first terminal of the latching circuit is coupled to the first node, and its second terminal is coupled to both the second and third switching components. A first terminal of the pixel capacitor is coupled to a second terminal of the third switching component, and its second terminal is coupled to a common voltage. The terminals of the first switching component that receive the data voltage and the gate signal, as well as the terminal coupled to the first node, are all in an open-circuit state.
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Claims

1. A pixel circuit for a non-display area of ​​a display panel, the pixel circuit comprising: a first switching component for transmitting a data voltage to a first node based on at least one gate signal; a second switching component having a first terminal coupled to the first node and a second terminal receiving a voltage signal; a third switching component having a first terminal coupled to the first node, a second terminal coupled to a third terminal of the second switching component, and the third terminal receiving the voltage signal; a latching circuit having a first terminal coupled to the first node and a second terminal coupled to a fourth terminal of the second switching component and a fourth terminal of the third switching component; and a pixel capacitor having a first terminal coupled to the second terminal of the third switching component and a second terminal coupled to a common voltage; wherein... The first switching assembly is in an open-circuit state at one end receiving the data voltage, one end receiving the at least one gate signal, and one end coupled to the first node.

2. The pixel circuit as described in claim 1, wherein the common voltage and the voltage signal are in phase and at the same potential.

3. The pixel circuit as claimed in claim 1, wherein the at least one gate signal includes a first gate signal and a second gate signal, and the first gate signal is inverted relative to the second gate signal, the first switching assembly includes: a first switch having a first terminal configured to receive the data voltage, a second terminal coupled to the first node, and a control terminal configured to receive the first gate signal, wherein the first terminal, the second terminal, and the control terminal of the first switch are in an open-circuit state; and a second switch having a first terminal configured to receive the data voltage, a second terminal coupled to the first node, and a control terminal configured to receive the second gate signal, wherein the first terminal, the second terminal, and the control terminal of the second switch are in an open-circuit state.

4. The pixel circuit as claimed in claim 3, wherein the latching circuit comprises: a first inverter having its non-inverting terminal coupled to the first node and its inverting terminal coupled to the fourth terminal of the second switching assembly and the fourth terminal of the third switching assembly; and a second inverter having its non-inverting terminal coupled to the inverting terminal of the first inverter and its inverting terminal coupled to the first node.

5. The pixel circuit as claimed in claim 4, further comprising: a fourth switching assembly coupled between the inverting input of the second inverter and the first node, and comprising: a third switch having a first terminal coupled to the inverting input of the second inverter, a second terminal coupled to the first node, and a control terminal receiving the second gate signal, wherein the first terminal, the second terminal, and the control terminal of the third switch are in an open-circuit state; and a fourth switch having a first terminal coupled to the inverting input of the second inverter, a second terminal coupled to the first node, and a control terminal receiving the first gate signal, wherein the first terminal, the second terminal, and the control terminal of the fourth switch are in an open-circuit state.

6. The pixel circuit as claimed in claim 4, wherein the second switching assembly comprises: a fifth switch having a first terminal configured to receive the voltage signal, a second terminal coupled to the first terminal of the pixel capacitor, and a control terminal coupled to the first node; and a sixth switch having a first terminal configured to receive the voltage signal, a second terminal coupled to the first terminal of the pixel capacitor, and a control terminal coupled to the inverting terminal of the first inverter.

7. The pixel circuit as claimed in claim 4, wherein the third switching assembly comprises: a seventh switch having a first terminal configured to be coupled to the first terminal of the pixel capacitor, a second terminal receiving the voltage signal, and a control terminal coupled to the first node; and an eighth switch having a first terminal configured to be coupled to the first terminal of the pixel capacitor, a second terminal receiving the voltage signal, and a control terminal coupled to the inverting terminal of the first inverter.

8. A pixel circuit for a non-display area of ​​a display panel, the pixel circuit comprising: a first switch for transmitting a data voltage to a first node based on a gate signal; a second switch having a first terminal receiving a voltage signal and a control terminal coupled to the first node; a third switch having a first terminal coupled to a third terminal of the second switch and a second terminal receiving the voltage signal; a latching circuit having a first terminal coupled to the first node and a second terminal coupled to a control terminal of the third switch; and a pixel capacitor having a first terminal coupled to the first terminal of the third switch and a second terminal coupled to a common voltage; wherein... The first switch is in an open circuit state at one end receiving the data voltage, one end receiving the gate signal, and one end coupled to the first node.

9. The pixel circuit as claimed in claim 8, wherein the latching circuit comprises: a first inverter having its non-inverting terminal coupled to the first node and its inverting terminal coupled to the control terminal of the second switch; and a second inverter having its inverting terminal coupled to the non-inverting terminal of the first inverter and its non-inverting terminal coupled to the inverting terminal of the first inverter.

10. The pixel circuit as described in claim 8, wherein the common voltage and the voltage signal are in phase and at the same potential.

Citation Information

Patent Citations

  • Pixel circuit and method for driving the same

    TW201612886A

  • Composite Device And Driving Method Of Electronic Device

    US20220319463A1