Memory device

Abstract

The purpose of this invention is to improve the performance of memory devices. A memory device according to an embodiment includes a first bit line, a first select transistor, a second bit line, a serial line, a word line, a sense amplifier, and a driving circuit. One end of the first select transistor is connected to the first bit line. The second bit line is connected to the other end of the first select transistor. The serial line includes a second select transistor connected to the second bit line and a memory cell transistor. The word line is connected to the memory cell transistor. The sense amplifier is connected to the first bit line. The driving circuit is connected to either the first bit line or the second bit line. During a write operation, when the memory cell transistor is set to be unprogrammable, the sense amplifier applies a first voltage to the first bit line, and the driving circuit applies a second voltage higher than the first voltage to the second bit line.

Claims

1. A memory device comprising: a first bit line; a first select transistor, one end of which is connected to the first bit line; a second bit line, the other end of which is connected to the first select transistor; a string comprising a second select transistor connected to the second bit line and a memory cell transistor; a word line connected to the memory cell transistor; a sense amplifier connected to the first bit line; and a drive circuit connected to either the first bit line or the second bit line; wherein, during a write operation, when the memory cell transistor is set to be unprogrammable, the sense amplifier applies a first voltage to the first bit line, and the drive circuit applies a second voltage higher than the first voltage to the second bit line; and during the write operation, the drive circuit applies the second voltage to the second bit line for a first time and then stops applying the second voltage to the second bit line.

2. A memory device comprising: a first bit line; a first select transistor, one end of which is connected to the first bit line; a second bit line, the other end of which is connected to the first select transistor; a string comprising a second select transistor connected to the second bit line and a memory cell transistor; a word line connected to the memory cell transistor; a sense amplifier connected to the first bit line; and a drive circuit connected to either the first bit line or the second bit line; wherein, during a write operation, when the memory cell transistor is set to be unprogrammable, the sense amplifier applies a first voltage to the first bit line, and the drive circuit applies a second voltage higher than the first voltage to the second bit line; wherein, during a write operation, when the memory cell transistor is set to be programmed, the sense amplifier applies a third voltage lower than the first voltage to the first bit line.

3. A memory device comprising: a first bit line; a first select transistor, one end of which is connected to the first bit line; a second bit line, the other end of which is connected to the first select transistor; a string comprising a second select transistor connected to the second bit line and a memory cell transistor; a word line connected to the memory cell transistor; a sense amplifier connected to the first bit line; a driving circuit connected to either the first bit line or the second bit line; a third bit line connected between the sense amplifier and the first bit line; and a third select transistor, one end of which is connected to the third bit line and the other end of which are respectively connected to the first bit line; wherein, during a write operation, when the memory cell transistor is set to be unprogrammable, the sense amplifier applies a first voltage to the first bit line, and the driving circuit applies a second voltage higher than the first voltage to the second bit line. The aforementioned driving circuit is connected to the aforementioned first bit line.

4. A memory device comprising: a first bit line; a first select transistor, one end of which is connected to the first bit line; a second bit line, connected to the other end of the first select transistor; a string comprising a second select transistor connected to the second bit line and a memory cell transistor; a word line connected to the memory cell transistor; a sense amplifier connected to the first bit line; a driving circuit connected to either the first bit line or the second bit line; a third bit line connected between the sense amplifier and the first bit line; a third select transistor of a first conductivity type, one end of which is connected to the third bit line and the first bit line, respectively; and a fourth bit line connected to the gate of the third select transistor. When the memory cell transistor is set to be unprogrammable during the write operation, the sense amplifier applies a first voltage to the first bit line, and the drive circuit applies a second voltage higher than the first voltage to the second bit line. The drive circuit includes a fourth select transistor of a second conductivity type different from the first conductivity type. One end of the fourth select transistor is connected to the first bit line, the other end is applied with the second voltage, and the gate is connected to the fourth bit line.

5. The memory device of claim 4 further includes a sequencer for performing the write operation, wherein when the memory cell transistor is set to be unprogrammable during the write operation, the sequencer applies a voltage of a first logic level to the fourth bit line, and when the memory cell transistor is set to be programmed, the sequencer applies a voltage of a second logic level different from the first logic level to the fourth bit line.

6. The memory device of claim 4 further includes an operation selection circuit, wherein during the write operation, the operation selection circuit applies a voltage of a first logic level to the fourth bit line when the output voltage of the sense amplifier is below the first voltage, and applies a voltage of a second logic level different from the first logic level to the fourth bit line when the output voltage is above the first voltage.

7. The memory device of claim 4, further comprising a first conductor layer, a first contact, and a second contact; the third select transistor comprising a first semiconductor layer of a third conductivity type, a first gate insulating film on the first semiconductor layer, and a first gate electrode on the first gate insulating film; the fourth select transistor comprising a second semiconductor layer, a second gate insulating film on the second semiconductor layer, and a second gate electrode on the second gate insulating film; the second semiconductor layer being disposed at the same height as the first semiconductor layer and being a fourth conductivity type different from the third conductivity type; the first conductor layer being disposed at a position higher than the first semiconductor layer; the first contact connecting the first conductor layer and the first gate electrode; and the second contact connecting the first conductor layer and the second gate electrode.

8. A memory device comprising: a substrate; a first bit line; a first select transistor, one end of which is connected to the first bit line; a second bit line, the other end of which is connected to the first select transistor; a string comprising a second select transistor connected to the second bit line and a memory cell transistor; a word line connected to the memory cell transistor; a sense amplifier connected to the first bit line; and a driving circuit connected to either the first bit line or the second bit line; wherein, during a write operation, when the memory cell transistor is set to be unprogrammable, the sense amplifier applies a first voltage to the first bit line, and the driving circuit applies a second voltage higher than the first voltage to the second bit line, the string comprising a third semiconductor layer having a portion extending along a first direction parallel to the surface of the substrate and functioning as a channel for the memory cell transistor.

9. The memory device of claim 8 further includes a first post, which extends along a second direction intersecting the first direction and functions as a character line, and the portion where the first post intersects with the third semiconductor layer functions as a memory cell transistor.

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