Semiconductor device and forming method thereof

TWI937907BActive Publication Date: 2026-09-01POWERX SEMICONDUCTOR CORPORATION
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Patent Information

Application Number
TW114123159
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-06-19
Publication Date
2026-09-01
Estimated Expiration
2045-06-18

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    Figure TWG2TB001908895_003
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Abstract

A semiconductor device includes a substrate, a conductive pad, a passivation layer, and conductive bumps. The conductive pad is on the substrate. The passivation layer is on the substrate and the conductive pad, and in a cross-sectional view, the passivation layer has a plurality of first portions and a plurality of second portions contacting the conductive pad, the first portions having a first height and the second portions having a second height greater than the first height. The conductive bumps cover the first portions and second portions of the passivation layer and penetrate the passivation layer to contact the conductive pad.
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Claims

1. A semiconductor device comprising: a substrate; a conductive pad on the substrate; a passivation layer on the substrate and the conductive pad, and in a cross-sectional view, the passivation layer having a plurality of first portions and a plurality of second portions contacting the conductive pad, the first portions having a first height and the second portions having a second height greater than the first height; and a conductive bump covering the first portions and the second portions of the passivation layer, the conductive bump penetrating the passivation layer to contact the conductive pad, wherein the conductive bump includes a pillar, a top surface of the pillar including a horizontal plane, and the pillar is on the first portions and the second portions of the passivation layer.

2. The semiconductor device as claimed in claim 1, wherein the conductive bump further comprises: a solder on the pillar, the top surface of the pillar further comprising a convex surface connecting the horizontal plane, the highest point of the convex surface being higher than the horizontal plane.

3. The semiconductor device as claimed in claim 1, wherein the second portions of the passivation layer are located at the center of the conductive pad, and the first portions of the passivation layer surround the second portions of the passivation layer.

4. The semiconductor device as claimed in claim 1, wherein, in the cross-sectional view, the widths of the first portions and the second portions of the passivation layer are equal.

5. The semiconductor device as claimed in claim 1, wherein the top surface of the pillar of the conductive bump further includes a plurality of protrusions, the highest point of which is above the horizontal plane and the protrusions are spaced apart from each other in the cross-sectional view, and the conductive bump further includes a solder on the pillar.

6. The semiconductor device as claimed in claim 5, wherein the conductive bump further comprises: an alloy layer between the pillar and the solder.

7. The semiconductor device as claimed in claim 5, wherein the first portions and the second portions of the passivation layer are arranged in an interleaved manner, and the second portions of the passivation layer are aligned with the protrusions.

8. A method of forming a semiconductor device, comprising: forming a conductive pad on a substrate; forming a passivation layer on the substrate and the conductive pad, wherein, in a cross-sectional view, the passivation layer has a plurality of first portions and a plurality of second portions contacting the conductive pad, the first portions having a first height and the second portions having a second height greater than the first height; after forming the passivation layer, forming a conductive bump on the conductive pad to cover the first portions and the second portions of the passivation layer; and attaching a metal frame to the conductive bump.

9. The method as described in claim 8, wherein the center of the conductive pad is not exposed by the passivation layer.

10. The method of claim 8, wherein forming the conductive bump on the conductive pad comprises: forming a pillar on the first and second portions of the passivation layer; and forming a solder on the pillar; wherein a top surface of the pillar includes a horizontal plane and a convex surface connecting the horizontal plane, the highest point of the convex surface being higher than the horizontal plane.

Citation Information

Patent Citations

  • Bump-on-leadframe semiconductor package with low thermal resistance

    TW201330184A

  • Copper pillar sidewall protection

    TW201730996A