Integrated device and method of manufacturing the same

Abstract

In some embodiments, this disclosure relates to an integrated device comprising: a first top electrode including a base portion extending on a substrate and having a first width in a first direction and a first height in a second direction perpendicular to the first direction; and a plurality of protrusions extending below the base portion and having a second width in the first direction and a second height in the second direction, wherein the first width is greater than the first height and the second height is greater than the second width; a first bottom electrode surrounding the first protrusion of the plurality of protrusions; a second bottom electrode surrounding the second protrusion of the plurality of protrusions; and a dielectric layer separating the first bottom electrode from the first top electrode and separating the second bottom electrode from the first top electrode.

Claims

1. An integrated device, comprising: A first top electrode includes: a base portion extending on a substrate, the base portion having a first width in a first direction and a first height in a second direction perpendicular to the first direction, wherein the first width is greater than the first height; and a plurality of protrusions extending below the base portion, the plurality of protrusions having a second width in the first direction and a second height in the second direction, wherein the second height is greater than the second width; a first bottom electrode surrounding a first protrusion among the plurality of protrusions in the first direction and in a third direction perpendicular to the first and second directions; a second bottom electrode surrounding a second protrusion among the plurality of protrusions in the first direction and in the third direction; and a dielectric layer separating the first bottom electrode from the first top electrode and separating the second bottom electrode from the first top electrode.

2. The integrated device as described in claim 1, further comprising: The first metal wire of the first metal wire layer extends below the first bottom electrode and is electrically coupled to the first bottom electrode; A second metal line of the first metal line layer extends below the second bottom electrode and is electrically coupled to the second bottom electrode, wherein the second metal line is electrically isolated from the first metal line through an interlayer dielectric; a third metal line of the second metal line layer electrically couples the first top electrode to a voltage rail; a first pixel circuit includes a first plurality of photodetectors, a first floating diffusion region, a first plurality of transfer transistors having a plurality of first source / drain regions coupled to the first plurality of photodetectors and a plurality of second source / drain regions coupled to the first floating diffusion region, a first source follower transistor, and a first column select transistor; a second pixel circuit includes a second plurality of photodetectors, a second floating diffusion region, a second plurality of transfer transistors having a plurality of third source / drain regions coupled to the second plurality of photodetectors and a plurality of fourth source / drain regions coupled to the second floating diffusion region, a second source follower transistor, and a second column select transistor; a first lateral overflow integrating capacitor transistor includes a fifth source / drain region coupled to the first metal line and a sixth source / drain region coupled to the first floating diffusion region; And a second lateral overflow integral capacitor transistor, including a seventh source / drain region coupled to the second metal line and an eighth source / drain region coupled to the second floating diffusion region.

3. The integrated device as described in claim 1, further comprising: The first metal wire of the first metal wire layer extends below the first bottom electrode and is electrically coupled to the first bottom electrode; The second metal wire of the first metal wire layer extends below the second bottom electrode and is electrically coupled to the second bottom electrode, wherein the second metal wire is electrically isolated from the first metal wire through an interlayer dielectric. The third metal wire of the second metal wire layer electrically couples the first top electrode to the voltage rail; And related dual-sampling circuitry, including: a comparator having a first input and a second input; a first sampling transistor having a first source / drain region coupled to the first metal line and the first input and a second source / drain region coupled to the output line; and a second sampling transistor having a third source / drain region coupled to the second metal line and the second input and a fourth source / drain region coupled to the output line.

4. The integrated device as claimed in claim 1 further includes a first metal wire extending below the first bottom electrode and the second bottom electrode and electrically coupling the first bottom electrode to the second bottom electrode.

5. The integrated device as described in claim 4, further comprising: The third bottom electrode, in the first direction, surrounds the third protrusion among the plurality of protrusions in the third direction; And a second metal wire of the first metal wire layer, extending below the third bottom electrode and electrically coupled to the third bottom electrode, wherein the second metal wire is electrically isolated from the first metal wire through an interlayer dielectric.

6. A method for forming an integrated device, comprising: An interconnect structure and an interlayer dielectric are formed on a substrate, wherein the interconnect structure includes a first metal wire layer; Multiple trenches are etched into the interlayer dielectric to expose a first metal line and a second metal line in the first metal line layer; a first conformal electrode layer is formed on the interlayer dielectric and within the multiple trenches; the first conformal electrode layer is etched to remove multiple upper surfaces extending between the multiple trenches, thereby forming a first bottom electrode on the first metal line and a second bottom electrode on the second metal line; a conformal dielectric layer is formed on the first bottom electrode and the second bottom electrode; A second conformal electrode layer is formed on the conformal dielectric layer; and the conformal dielectric layer and the second conformal electrode layer are etched such that the dielectric layer and the first top electrode are retained on the first bottom electrode and the second bottom electrode.

7. The method of claim 6, wherein etching the conformal dielectric layer and the second conformal electrode layer further removes a plurality of portions of the first conformal electrode layer remaining above the substrate, thereby forming a floating conductive ring around the first bottom electrode and the second bottom electrode.

8. The method of claim 6, wherein etching the first conformal electrode layer further comprises: A plurality of first photoresist plugs are formed between the inner sidewalls of the first conformal electrode layer; A masking layer is formed over the interlayer dielectric and surrounds the plurality of trenches, wherein the masking layer is spaced apart from the plurality of trenches in a first direction parallel to the surface of the substrate and in a second direction parallel to the surface of the substrate and perpendicular to the first direction; And perform an etching process to remove portions of the first conformal electrode layer and portions of the interlayer dielectric exposed by the mask layer and the plurality of first photoresist plugs, thereby separating the first bottom electrode, the second bottom electrode and the plurality of portions of the remaining first conformal electrode layer on the interlayer dielectric.

9. A method for forming an integrated device, comprising: An interlayer dielectric is formed on the substrate; Multiple trenches are etched into the interlayer dielectric; A first conformal electrode layer is formed on the interlayer dielectric and within the first plurality of trenches; the first conformal electrode layer is etched to remove a plurality of upper surfaces in the first conformal electrode layer, such that a first bottom electrode is retained in the first trench of the plurality of trenches, a second bottom electrode is retained in the second trench of the plurality of trenches and spaced apart from the first bottom electrode, and the overlying portion of the first conformal electrode layer is isolated from the first bottom electrode and the second bottom electrode; a conformal dielectric layer is formed on the first bottom electrode and the second bottom electrode; A second conformal electrode layer is formed on the conformal dielectric layer; and the conformal dielectric layer, the second conformal electrode layer, and the overlying portion of the first conformal electrode layer are etched, such that the dielectric layer and the first top electrode are held above the first bottom electrode, the second bottom electrode, and the first floating conductive ring.

10. The method of claim 9, wherein the second plurality of trenches are etched simultaneously with the first plurality of trenches, wherein etching the first conformal electrode layer further causes a third bottom electrode to be formed within a trench in the second plurality of trenches, and wherein the third bottom electrode is spaced apart from the first bottom electrode and the second bottom electrode through the overlying portion in the first conformal electrode layer.

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