Control device and detecting circuit

Abstract

A control device and a detection circuit are disclosed. The control device includes a detection circuit for detecting a power supply voltage to generate a power-on reset signal. The detection circuit includes a transistor string circuit, a resistor circuit, and an output circuit, wherein the resistor circuit and the transistor string circuit are coupled between the power supply voltage and ground. In response to the control device and memory array entering a deep power-saving mode from standby mode, the resistor circuit increases its resistance value according to the deep power-saving signal.

Claims

1. A control device for controlling a memory array, comprising: A first peripheral circuit group, coupled to the memory array, is configured to be driven together with the memory array by an operating voltage; The system also includes a second peripheral circuit group coupled to the memory array and the first peripheral circuit group, configured to be driven by a power supply voltage, comprising: a detection circuit that detects the power supply voltage and generates a power-on reset signal, the detection circuit including: a transistor string circuit; a resistor circuit connected in series with the transistor string circuit between the power supply voltage and a ground, wherein a voltage divider is generated at the common junction of the transistor string circuit and the resistor circuit, the resistor circuit responding to the control device and the memory array entering a deep power-saving mode from a standby mode by increasing the resistance value of the resistor circuit according to a deep power-saving signal; and an output circuit whose input is coupled to the common junction of the transistor string circuit and the resistor circuit, outputting the power-on reset signal according to the voltage divider.

2. The control device as claimed in claim 1, wherein the resistor circuit comprises: Multiple resistors are connected in series between the transistor string circuit and the ground. And a voltage divider regulating transistor coupled between one of the common contacts of the resistors and the ground, the control terminal of the voltage divider regulating transistor being controlled by the deep power saving signal to be turned on in the standby mode and turned off in the deep power saving mode.

3. The control device as claimed in claim 1, wherein the detection circuit further comprises: A pulse generation circuit, coupled to the input of the output circuit, responds to the control device and the memory array entering an initialization mode from the deep power-saving mode. Based on the deep power-saving signal, a first pulse signal is provided. The output circuit, based on the first pulse signal, switches the power-on reset signal from a first logic level to a second logic level during the pulse width of the first pulse signal, so as to control the control device and the memory array to enter the initialization mode.

4. The control device as claimed in claim 3, wherein the pulse generating circuit comprises: An inverter whose input receives the deep power-saving signal and generates an inverted signal based on the deep power-saving signal; A pulse generator, coupled to the output of the inverter, responds to the control device and the memory array entering the initialization mode from the deep power-saving mode, and provides a second pulse signal based on the inverted signal; and a bypass transistor, coupled between the input of the output circuit and the ground, the control terminal of the bypass transistor being coupled to the pulse generator, and being turned on during the pulse width of the second pulse signal when the control device and the memory array enter the initialization mode from the deep power-saving mode.

5. The control device as claimed in claim 1, wherein when the control device and the memory array enter a power-off mode from the standby mode, the detection circuit reacts to the power supply voltage being less than a first threshold voltage and switches the power-on reset signal from a first logic level to a second logic level; and when the control device and the memory array enter the power-off mode from the deep power-saving mode, the detection circuit reacts to the power supply voltage being less than a second threshold voltage and switches the power-on reset signal from the first logic level to the second logic level, wherein the first threshold voltage is greater than the second threshold voltage.

6. The control device as claimed in claim 1, wherein the output circuit includes: A Schmitt trigger whose input is coupled to the common junction of the transistor string circuit and the resistor circuit; And an inverter whose input is coupled to the output of the Schmitt trigger, the output of which is used to output the power-on reset signal.

7. A detection circuit adapted to detect a power supply voltage supplied to a control device and generate a power-on reset signal, the control device being adapted to control a memory array, the detection circuit comprising: A transistor string circuit; a resistor circuit connected in series with the transistor string circuit between the power supply voltage and a ground, wherein a voltage divider is generated at the common junction of the transistor string circuit and the resistor circuit, the resistor circuit responds to the control device and the memory array entering a deep power-saving mode from a standby mode by increasing the resistance value of the resistor circuit according to a deep power-saving signal; and an output circuit whose input terminal is coupled to the common junction of the transistor string circuit and the resistor circuit, and outputs the power-on reset signal according to the voltage divider.

8. The detection circuit as claimed in claim 7, wherein the resistor circuit comprises: Multiple resistors are connected in series between the transistor string circuit and the ground. And a voltage divider regulating transistor coupled between one of the common contacts of the resistors and the ground, the control terminal of the voltage divider regulating transistor being controlled by the deep power saving signal to be turned on in the standby mode and turned off in the deep power saving mode.

9. The detection circuit as described in claim 7, further comprising: A pulse generation circuit, coupled to the input of the output circuit, responds to the control device and the memory array entering an initialization mode from the deep power-saving mode. Based on the deep power-saving signal, a first pulse signal is provided. The output circuit, based on the first pulse signal, switches the power-on reset signal from a first logic level to a second logic level during the pulse width of the first pulse signal, so as to control the control device and the memory array to enter the initialization mode.

10. The detection circuit as claimed in claim 9, wherein the pulse generating circuit comprises: An inverter whose input receives the deep power-saving signal and generates an inverted signal based on the deep power-saving signal; A pulse generator, coupled to the output of the inverter, responds to the control device and the memory array entering an initialization mode from the deep power-saving mode, and provides a second pulse signal based on the inverted signal; and a bypass transistor, coupled between the input of the output circuit and the ground, the control terminal of the bypass transistor being coupled to the pulse generator, and being turned on during the pulse width of the second pulse signal when the control device and the memory array enter the initialization mode from the deep power-saving mode.

11. The detection circuit as claimed in claim 7, wherein when the control device and the memory array enter a power-off mode from the standby mode, the output circuit reacts to the power supply voltage being less than a first threshold voltage and switches the power-on reset signal from a first logic level to a second logic level; when the control device and the memory array enter the power-off mode from the deep power-saving mode, the output circuit reacts to the power supply voltage being less than a second threshold voltage and switches the power-on reset signal from the first logic level to the second logic level, wherein the first threshold voltage is greater than the second threshold voltage.

12. The detection circuit as claimed in claim 7, wherein the output circuit includes: A Schmitt trigger whose input is coupled to the common junction of the transistor string circuit and the resistor circuit; And an inverter whose input is coupled to the output of the Schmitt trigger, the output of which is used to output the power-on reset signal.

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