Fin field-effect transistor high voltage device and method of forming the same

TWI937937BActive Publication Date: 2026-09-01UNITED MICROELECTRONICS CORP
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Patent Information

Application Number
TW114125971
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-07-09
Publication Date
2026-09-01
Estimated Expiration
2045-07-08

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    Figure TWG2TB001908925_001
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    Figure TWG2TB001908925_002
  • Figure TWG2TB001908925_003
    Figure TWG2TB001908925_003
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Abstract

This invention provides a finned field-effect transistor (FET) high-voltage element and its formation method. The finned field-effect transistor high-voltage element includes a substrate, a diffusion blocking structure, a source epitaxial region, a drain epitaxial region, and a working gate structure. The diffusion blocking structure, the source epitaxial region, and the drain epitaxial region are located in the substrate, wherein the diffusion blocking structure is adjacent to the drain epitaxial region. The working gate structure is located above the diffusion blocking structure and adjacent to the drain epitaxial region and the source epitaxial region.
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Claims

1. A finned field-effect transistor high-voltage element, comprising: Base; A diffusion blocking structure, a source epitaxial region, and a drain epitaxial region are located in the substrate, wherein the diffusion blocking structure is adjacent to the drain epitaxial region; and a working gate structure is located above the diffusion blocking structure and adjacent to the drain epitaxial region and the source epitaxial region.

2. The finned field-effect transistor high-voltage device as claimed in claim 1, wherein the substrate comprises P-type doping.

3. The finned field-effect transistor high-voltage device as claimed in claim 1, wherein the drain epitaxial region comprises N+ type doping and wherein the source epitaxial region comprises N+ type doping.

4. The finned field-effect transistor high-voltage element as described in claim 1 further comprises: The source well region and the drain well region are located in the substrate, wherein the source epitaxial region is located in the source well region, and the drain epitaxial region and the diffusion blocking structure are located in the drain well region.

5. The finned field-effect transistor high-voltage element as claimed in claim 4, wherein the source well region comprises P-type doping and the drain well region comprises N-type doping.

6. The finned field-effect transistor high-voltage element as claimed in claim 1, wherein the diffusion blocking structure includes a single diffusion blocking structure.

7. The finned field-effect transistor high-voltage element as claimed in claim 1, wherein the working gate structure includes a working gate electrode and a gate insulating layer, wherein the gate insulating layer is located between the working gate electrode and the substrate.

8. The finned field-effect transistor high-voltage element as claimed in claim 1, wherein the operating gate structure completely covers the diffusion blocking structure.

9. The finned field-effect transistor high-voltage element as described in claim 1 further comprises: A dielectric layer is located on the source epitaxial region, the drain epitaxial region, and the working gate structure; A source contact plug located in the dielectric layer and on the source epitaxial region; and a drain contact plug located in the dielectric layer and on the drain epitaxial region.

10. The finned field-effect transistor high-voltage element as claimed in claim 1 further includes an epitaxial missing region located between the drain epitaxial region and the diffusion blocking structure.

11. A method for forming a finned field-effect transistor high-voltage element, comprising: Provide a base; A diffusion-blocking structure is formed in the substrate; A working gate structure is formed above the diffusion blocking structure; And the substrate in which the source epitaxial region and the drain epitaxial region are formed on opposite sides of the working gate structure, wherein the diffusion blocking structure is adjacent to the drain epitaxial region.

12. The method of forming a fin field-effect transistor high-voltage element as described in claim 11, wherein the substrate comprises P-type doping.

13. The method of forming a fin field-effect transistor high-voltage device as claimed in claim 11, wherein the drain epitaxial region comprises N+ type doping and wherein the source epitaxial region comprises N+ type doping.

14. The method for forming a finned field-effect transistor high-voltage element as described in claim 11, further comprising: A source well region and a drain well region are formed in the substrate, wherein the source epitaxial region is located in the source well region, and the drain epitaxial region and the diffusion blocking structure are located in the drain well region.

15. The method of forming a fin field-effect transistor high-voltage element as described in claim 14, wherein the source well region comprises P-type doping and the drain well region comprises N-type doping.

16. The method of forming a fin field-effect transistor high-voltage element as described in claim 11, wherein the diffusion blocking structure includes a single diffusion blocking structure.

17. The method of forming a fin field-effect transistor high-voltage element as claimed in claim 11, wherein the working gate structure includes a working gate electrode and a gate insulating layer, wherein the gate insulating layer is located between the working gate electrode and the substrate.

18. The method of forming a fin field-effect transistor high-voltage element as described in claim 11, wherein the operating gate structure completely covers the diffusion blocking structure.

19. The method for forming a finned field-effect transistor high-voltage element as described in claim 11, further comprising: A dielectric layer is formed on the source epitaxial region, the drain epitaxial region, and the working gate structure; A source contact plug is formed in the dielectric layer and located on the source epitaxial region; and a drain contact plug is formed in the dielectric layer and located on the drain epitaxial region.

20. The method of forming a finned field-effect transistor high-voltage element as claimed in claim 11, wherein during the formation of the drain epitaxial region, an epitaxial defect region is generated between the drain epitaxial region and the diffusion blocking structure.

Citation Information

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