Static random-access memory layout structure

Abstract

A static random access memory (SRAM) layout structure includes a substrate, a diffusion region extending along a first direction, and a gate structure extending along a second direction and traversing the diffusion region to form a plurality of transistors. These transistors include: first and second pull-up transistors (PU1, PU2), four pull-down transistors (PD11, PD12, PD21, PD22), and four access transistors (PG1, PG2, PG3, PG4). From a top view, the gate structure includes T-shaped first and second gate structures. The T-shaped first gate structure spans the first diffusion region, forming the first access transistor (PG1); the T-shaped second gate structure spans the second diffusion region, forming the second access transistor (PG2). The first and second diffusion regions are adjacent and parallel. Both the T-shaped first and second gate structures overlap with a first bulk contact doped region located between the first and second diffusion regions.

Claims

1. A static random access memory (SRAM) layout structure, comprising: a substrate; a plurality of diffusion regions disposed on the substrate, the plurality of diffusion regions including at least a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, and a sixth diffusion region extending along a first direction; and a plurality of gate structures disposed on the substrate, each of the plurality of gate structures extending along a second direction and traversing the plurality of diffusion regions, thereby forming a plurality of transistors, wherein the plurality of transistors includes a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a third pull-down transistor, a fourth pull-down transistor, a first access transistor, a second access transistor, a third access transistor, and a fourth access transistor; wherein, From a top-down view, the complex gate structure includes a T-shaped first gate structure and a T-shaped second gate structure. The T-shaped first gate structure spans the first diffusion region, and the T-shaped second gate structure spans the second diffusion region, forming the first access transistor and the second access transistor, respectively. The first diffusion region is adjacent to and parallel to the second diffusion region. The T-shaped first gate structure and the T-shaped second gate structure overlap with a first bulk contact doped region located between the first diffusion region and the second diffusion region. The first bulk contact doped region is adjacent to the first channel region of the first access transistor and the second channel region of the second access transistor.

2. The SRAM layout structure as described in claim 1, wherein, The T-shaped first gate structure is mirror-symmetrical to the T-shaped second gate structure relative to the first bulk contact doped region.

3. The SRAM layout structure as described in claim 2, wherein, The width of the T-shaped first gate structure and the T-shaped second gate structure in the first direction is greater than or equal to the width of the first bulk contact doped region.

4. The SRAM layout structure as described in claim 1, wherein, The first channel region of the first access transistor and the second channel region of the second access transistor are P-type channels, and the first bulk contact doped region is a P+ doped region.

5. The SRAM layout structure as described in claim 1, wherein, The plurality of gate structures further includes a third gate structure, which spans the first diffusion region and extends laterally into the second diffusion region, forming the first pull-down transistor and the second pull-down transistor, respectively, wherein, The first pull-down transistor is connected in series with the first access transistor, and the second pull-down transistor is connected in series with the second access transistor.

6. The SRAM layout structure as described in claim 5, wherein, The third gate structure partially overlaps with the second bulk contact doped region located between the first diffusion region and the second diffusion region.

7. The SRAM layout structure as described in claim 5, wherein, The third gate structure further includes a first protrusion that extends toward the T-shaped first gate structure; And a second protrusion that extends toward the T-shaped second gate structure.

8. The SRAM layout structure as described in claim 6, wherein, The second body contact doped region is adjacent to the first diffusion region and the second diffusion region.

9. The SRAM layout structure as described in claim 6, wherein, The second body contact doped region is adjacent to the third channel region of the first pull-down transistor and the fourth channel region of the second pull-down transistor.

10. The SRAM layout structure as described in claim 5, wherein, The third gate structure extends into the third diffusion region adjacent to the first diffusion region and crosses the third diffusion region to form the first pull-up transistor.

11. The SRAM layout structure as described in claim 10, wherein, The third gate structure partially overlaps with the third body contact doped region disposed between the first diffusion region and the third diffusion region.

12. The SRAM layout structure as described in claim 11, wherein, The third body contact doped region is adjacent to the third diffusion region and the fifth channel region of the first pull-up crystal.

13. The SRAM layout structure as described in claim 12, wherein, The third gate structure further includes a third protrusion that extends toward the second pull-up transistor.

14. The SRAM layout structure as described in claim 1, wherein, The substrate is a silicon-coated insulating substrate.

15. The SRAM layout structure as described in claim 1, wherein, The first pull-up transistor and the second pull-up transistor are PMOS transistors.

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