ESD protective structure for display panels and display panel and display device using the same

Abstract

An electrostatic discharge (ESD) protection structure for a display panel, and a display panel and display device using the same. The display panel includes a substrate, a pixel array, multiple scan lines, multiple data lines, and an ESD protection structure. The ESD protection structure is disposed in at least a portion of the bezel area and includes a first metal layer, a first insulating layer, a second metal layer, and a second insulating layer stacked together, wherein at least one of the first metal layer and the second metal layer has a perforated structure to form a discontinuous island-like structure in the cross-section of the ESD protection structure.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to an electrostatic protection structure for a display panel and a display panel and display device using the same. Prior Technology

[0002] In modern display technology, display devices play a crucial role. These devices are widely used in various equipment such as televisions, computer monitors, and smartphones. The display panel is the core component of the display device, responsible for generating the image visible to the user. Existing display panel technologies include liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs), and quantum dot displays (QLEDs). Among them, liquid crystal display technology relies on a backlight module to illuminate the display panel. The backlight module typically includes light-emitting diodes (LEDs) as the light source and a light guide plate to distribute the light evenly. In addition, the pixel array in the display panel is crucial for generating high-quality images. Each pixel contains red, green, and blue subpixels, which work together to produce rich and colorful images. However, while providing high resolution and high color accuracy, existing technologies often face challenges in energy efficiency and manufacturing costs.

[0003] The manufacturing process of display devices typically involves three stages: array fabrication, cell fabrication, and module integration. In the array fabrication stage, thin-film transistor arrays (also known as TFT array substrates or pixel array substrates) are formed on a glass substrate through steps such as cleaning, thin-film deposition, photolithography, etching, and metallization. Next, in the cell fabrication stage, the thin-film transistor array and color filters are combined and liquid crystal material is injected to encapsulate and form a display unit / panel. In the module integration stage, multiple display panels arranged on a mother substrate are segmented and assembled with corresponding driving circuits to form an independent display device.

[0004] In the array manufacturing process, processes such as film deposition, mask exposure, and etching are involved. High-speed airflow rubbing against the glass substrate easily generates static electricity. Furthermore, static electricity is also easily generated during the handling of the TFT array substrate by friction with the equipment, leading to electrostatic discharge (ESD). Static electricity is a ubiquitous phenomenon in nature; it is generated when two materials with different dielectric constants rub against each other. The release of static charge from an object, returning it to neutral (the sparks that sometimes occur when a human touches a doorknob are a form of electrostatic discharge), is called electrostatic discharge, or ESD. The effects of ESD significantly reduce the yield of display panels.

[0005] More specifically, the aforementioned electrostatic discharge (ESD) generates high temperatures, exceeding those of the metals used in the TFT array substrate manufacturing process. The temperature during ESD exceeds 3000°C, which is higher than the melting points of commonly used materials in TFT array substrate manufacturing (such as aluminum, copper, and molybdenum). Therefore, it causes ESD damage to the metal circuitry within the TFT array substrate. For example, when a large current flows instantaneously through the indium tin oxide (ITO) electrode, oxygen atoms escape, leaving indium tin and making it opaque. Additionally, a large instantaneous voltage breaking down the insulating layer can leave defects, leading to leakage between electrodes and making it impossible to accurately set the voltage. Although these defects only occur under large ESD voltages, even small ESD voltages can still damage the structure of the TFT array substrate.

[0006] In common motherboard designs, test circuit traces exist on the glass substrate of the motherboard, surrounding the display panel on the glass substrate. Each test circuit trace is connected to its corresponding display panel. During manufacturing, static electricity is generated due to friction between high-speed airflow and the glass substrate, or during glass substrate handling. This static charge can be dispersed across the entire glass substrate of the motherboard via the test circuit traces, thereby reducing damage to the circuitry on the display panel.

[0007] However, since the size of the mother glass substrate is fixed, when manufacturing small-sized display panels, those skilled in the art will try to design and place as many display panels as possible on a single glass substrate. In other words, the number of panels designed and placed on the glass substrate becomes a very important factor in display panel manufacturing. Therefore, in order to increase the utilization rate of the glass substrate, gaps are eliminated between display panels to maximize its utilization. However, in this design, there is no extra space to further configure the test circuit traces, which increases the risk of electrostatic discharge (ESD) damage during the display panel manufacturing process, leading to a loss of yield.

[0008] Currently, the electrostatic discharge (ESD) protection structure of the mother substrate mainly relies on test circuit traces to achieve ESD protection. However, this limits the number of display panels that can be configured on a single mother substrate. Specifically, the test circuit traces on the array substrate are very space-consuming. In the prior art, the distance between the side of one trace furthest from another trace and the side of another trace closest to another trace is 90-160 μm. Typically, the test circuit traces on an array substrate require at least 7 to 14 such spacings, and the test points on the array substrate also require more than 5000 μm of space. In other words, the test circuit trace space required for a single display panel on an array substrate must be at least 6120-7240 μm.

[0009] In addition, to further reduce the impact of static electricity, in some applications, display panels have an electrostatic discharge ring around their perimeter in the bezel area. This ring dissipates static electricity accumulated within the panel during manufacturing and improves the panel's electrostatic protection capability. However, during the assembly process, screen printing or diffusion processes are used to apply a frame adhesive, bonding the pixel array substrate and color filter substrate to their proper positions and sealing the two substrates. This prevents moisture and other substances from entering the liquid crystal cell, cuts off contact between the liquid crystal molecules and the external environment, prevents liquid crystal leakage, and ensures product reliability.

[0010] After the frame adhesive is applied to the bezel area of ​​the display panel, UV light scanning is used to improve the curing rate. However, the traditional electrostatic discharge ring design is relatively wide, which will block the UV light that assists in the curing of the frame adhesive over a large area, reducing the curing rate of the frame adhesive. This can lead to liquid leakage, moisture entering and corroding the panel, resulting in adverse consequences such as panel display problems.

[0011] Typically, test circuit traces are only included in array substrates when configuring large-sized display panels. When configuring a larger number of small-sized display panels on the array substrate, the test circuit traces are omitted. In such cases, the absence of test circuit traces on the array substrate means the display panels cannot avoid electrostatic discharge (ESD). Furthermore, as market demands for narrower panel bezels increase, the distance between the ESD ring and the cutting line decreases, potentially causing the cutting wheel to cut into the metal layer, resulting in poor conductivity of the ESD ring.

[0012] Therefore, for those skilled in the art, how to increase the number of display panels that can be configured on an array substrate while achieving electrostatic discharge protection is also an important issue in the field.

[0013] On the other hand, packaging technology is a crucial step in the manufacturing process of display devices, affecting their performance and reliability. The main goal of packaging technology is to effectively integrate the microelectronic components of the display screen onto the display panel. Among these, Chip-on-Glass (COG) packaging technology directly mounts the integrated driver circuitry (i.e., driver chip, or driver IC) of the display device onto a glass substrate, allowing the driver IC to directly output the voltage or signals required by the display module to each pixel. COG packaging technology is relatively mature, cost-effective, and has easily adjustable production capacity. However, because it requires the driver IC to be placed on the glass substrate, limitations such as IC size and wiring requirements make it difficult to achieve narrow bezel designs in COG-packaged display devices.

[0014] In COG packaging technology, integrating the scan driver onto the glass substrate is called GOP (Gate Driver on Panel) driving. In GOP-driven designs, the scan driver circuit (or scan drive circuit) is fabricated using the same process technology as the thin-film transistors (TFTs) in the pixel array, with only a few timing control signals provided by the external circuitry. This saves on integrated circuits related to the scan driver, reducing the manufacturing cost of the liquid crystal display. Furthermore, since GOP driving requires fewer timing control signals to operate, the space requirements for signal traces in the external circuitry can be optimized, thereby increasing the effective display area.

[0015] With technological advancements, Chip-on-Film (COF) packaging technology has emerged, which allows driver ICs to be directly packaged on flexible circuit boards and bent and positioned on the back of the display panel. Because the driver IC does not need to be placed on the glass substrate, the bezel area can be effectively reduced, making it easier to meet the demand for narrow bezels. However, while COF packaging technology can reduce bezel size, its technical barriers are high, its manufacturing costs are relatively high, and it also limits production capacity. Both of these technologies have limitations in achieving narrow bezel designs, making it difficult to simultaneously balance cost and performance.

[0016] For example, in COF-packaged display panel designs, the scan lines of the pixel array are typically connected to the driver chip via fan-out traces. The fan-out traces are generally laid out using either a single-layer or double-layer metal staggered arrangement. However, regardless of the chosen design, it's difficult to simultaneously meet the requirements for narrow bezel design and circuit corrosion resistance and reliability.

[0017] On the other hand, in GOP-packaged display panel designs, the scan line voltage is generated in the gate circuitry on the panel, rather than being provided by the integrated circuit, while the data line voltage is still directly provided by the driver chip. Because GOP packaging requires only a few pins of the driver chip to drive the gate circuitry on the panel to generate the scan line voltage signal, the use of integrated circuit chips can be reduced, allowing for optimization of the panel edge design. This offers a relatively significant advantage when designing small-sized models.

[0018] During the panel design process, from array to cell assembly, the pixel array and color filter are bonded together using sealant. Ultraviolet light is used during bonding to promote sealant curing and maintain reliable panel adhesion. However, in most current panels, the gate circuit design uses opaque metal on both sides, occupying a large edge area, resulting in very low ultraviolet light transmittance. This affects the sealant curing effect and consequently reduces panel reliability.

[0019] On the other hand, due to the increasing demands for resolution in the current market, the pixel size requirements in the pixel array design of display panels are becoming smaller and smaller. Although the pixel size is shrinking, the line width and spacing of the scan lines and data lines do not decrease with the pixel size. Therefore, the smaller the pixel, the smaller the overlap area between the pixel electrode and the common electrode. Under this specification constraint, general pixel designs often suffer from insufficient storage capacitor size, making it difficult to achieve the requirements of pixel voltage regulation and reduced leakage current.

[0020] Integrating touch functionality into a display device typically requires embedding the touch panel into the display panel using either an on-cell or in-cell method. On-cell touch display panels offer advantages such as simple structure, relatively low manufacturing cost, and higher production yield because the touch electrodes are simply attached to the existing display panel, eliminating the need for complex modifications to the panel's structure. However, in on-cell touch display panels, the relatively large distance between the touch sensing electrodes and the finger (usually separated by encapsulation glass or a color filter) results in weaker capacitive signals, affecting touch recognition sensitivity. Furthermore, since the touch electrodes are attached to the display panel, reducing the overall device thickness is difficult, hindering current trends towards thinner and lighter designs.

[0021] In-Cell touch display panels integrate touch electrodes directly into the display panel, coexisting with the pixel structure, thus reducing the overall panel thickness. However, because the touch electrodes coexist with the display pixel electrodes in In-Cell touch display panels, the display drive signal may affect the touch signal, generating noise interference. In typical designs, to avoid interference, precise design of the touch sensing timing is required, interleaving touch scanning and display refresh to prevent signal aliasing, making the display device's drive design more complex. Furthermore, in high refresh rate display panels (such as 120Hz, 240Hz), coordinating the touch and display scan cycles to ensure high-precision touch while avoiding display flicker is also a significant technical challenge. Summary of the Invention

[0022] One of the objectives of this application is to provide an electrostatic discharge (ESD) protection structure for a display panel and a display panel and display device using the same, in order to solve the above-mentioned problems, including but not limited to the impact of electrostatic discharge on the manufacturing yield of the display panel, the poor ESD protection effect and insufficient storage capacitance of small-sized display panels, the low reliability of the sealant curing process, the excessively complex drive design of the display driver panel leading to difficulty in reducing costs, and the difficulty in ensuring the surface flatness of the display panel during the manufacturing process.

[0023] This application provides a display panel comprising a substrate, a pixel array, multiple scan lines, multiple data lines, and an electrostatic discharge (ESD) protection structure. The substrate has a display area and a non-display area, wherein the non-display area includes a border region. The pixel array is disposed on the display area of ​​the substrate and has multiple pixel units arranged in an array. The multiple scan lines are formed on the substrate and electrically connect each column of pixel units in the pixel array. The multiple data lines are formed on the substrate and electrically connect each row of pixel units in the pixel array. The ESD protection structure is disposed in at least a portion of the border region and includes a first metal layer, a first insulating layer, a second metal layer, and a second insulating layer stacked together, wherein at least one of the first metal layer and the second metal layer has a perforated structure to form a discontinuous island-like structure in the cross-section of the ESD protection structure.

[0024] In some embodiments of this application, the display panel further includes a first fan-out transmission section and a second fan-out transmission section. The first fan-out transmission section is disposed on one side of the non-display area and has multiple fan-out traces, wherein the first fan-out metal layer is formed on the third insulating layer and electrically connected to the second end of the thin-film transistor, wherein the third metal layer has a first portion and a second portion. A fourth insulating layer covers the third metal layer. The common electrode has a grid structure and is formed on the fourth insulating layer, and has a first portion and a second portion. The orthographic projection areas of the first portion of the third metal layer and the first portion of the common electrode at least partially overlap. The orthographic projection areas of the second portion of the third metal layer, the second portion of the common electrode, and the nth scan line at least partially overlap.

[0025] In some embodiments of this application, the display panel further includes a scan driving circuit disposed on the non-display area and comprising a plurality of scan units for electrically connecting the plurality of scan lines. Each scan unit includes at least one holding capacitor, and the structure of the holding capacitor includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a third conductive layer, and a fourth conductive layer. The third conductive layer and the fourth conductive layer are light-transmitting conductive layers. The third conductive layer is disposed on the second insulating layer, and the fourth conductive layer is disposed on the first insulating layer and at least a portion of it is covered by the second insulating layer, wherein one end of the fourth conductive layer is connected to the second metal layer. At least a portion of the first metal layer has a through-hole formed to expose the at least a portion of the first metal layer from the first insulating layer and the second insulating layer. The third conductive layer connects to the at least a portion of the first metal layer exposed via the through-hole.

[0026] In some embodiments of this application, the display panel further includes a third metal layer, a plurality of light-emitting elements, a protective layer, and a fourth metal layer. The third metal layer is formed within the display area on the substrate and includes a plurality of first electrode regions and a plurality of second electrode regions, wherein the plurality of first electrode regions and the plurality of second electrode regions are electrically independent of each other and are alternately arranged on the substrate at intervals. Each light-emitting element includes a first electrode and a second electrode formed on opposite sides, the first electrode being electrically connected to a corresponding first electrode region. The protective layer fills between the plurality of light-emitting elements and covers at least a portion of the surface of each light-emitting element. The fourth metal layer is formed on the protective layer and includes a plurality of third electrode regions, wherein the plurality of third electrode regions are respectively formed on the plurality of light-emitting elements and electrically connected to the second electrode of the corresponding light-emitting element. Each pixel unit includes a display unit and a touch sensing unit; the display unit includes a corresponding light-emitting element and a first electrode region and a third electrode region electrically connected to the corresponding light-emitting element; and the touch sensing unit includes a second electrode region and a fourth electrode region adjacent to the display unit.

[0027] This application provides an electrostatic discharge (ESD) protection structure for a display panel, comprising a mother substrate and multiple display panels. The mother substrate includes multiple array blocks. The multiple display panels are sequentially arranged on the array blocks on the mother substrate, wherein each array block includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a first conductive layer. The first metal layer is formed on each array block in a manner surrounding at least two of the multiple display panels to form multiple first ESD lines on each array block. The first insulating layer covers the first metal layer, exposing at least a portion of the first metal layer. The second metal layer is formed on the first insulating layer in a manner surrounding at least two of the multiple display panels to form multiple second ESD lines on each array block corresponding to the multiple first ESD lines. The second insulating layer covers the second metal layer, exposing at least a portion of the second metal layer. A first conductive layer is formed in the bridging region, wherein at least a portion of the first conductive layer is connected to the first metal layer through a portion exposed by the first insulating layer, and at least another portion of the first conductive layer is connected to the second metal layer through a portion exposed by the second insulating layer, thereby enabling the plurality of first electrostatic discharge lines and the plurality of second electrostatic discharge lines to be electrically connected to each other in the bridging region.

[0028] This application provides a display panel comprising a substrate, a pixel array, multiple scan lines, a first fan-out transmission section, and a second fan-out transmission section. The substrate has a display area and a non-display area. The pixel array is disposed on the display area of ​​the substrate. Multiple scan lines are sequentially formed on the substrate and electrically connected to the pixel array. The first fan-out transmission section is disposed on one side of the non-display area and has multiple fan-out traces, wherein the multiple fan-out traces of the first fan-out transmission section are electrically connected to an odd number of the scan lines. The second fan-out transmission section is disposed on the opposite side of the non-display area relative to the first fan-out transmission section and has multiple fan-out traces, wherein the multiple fan-out traces of the second fan-out transmission section are electrically connected to an even number of the scan lines. The multiple scan lines include a first scan line group and a second scan line group. The multiple fan-out traces electrically connected to the first scan line group are formed on the substrate with a first trace structure, and the multiple fan-out traces electrically connected to the second scan line group are formed on the substrate with a second trace structure.

[0029] In some embodiments of this application, the display panel has a first metal layer, a first insulating layer, a second metal layer, and a second insulating layer sequentially formed on the substrate, and the plurality of scan lines are formed on the first metal layer. The first trace structure includes a single-layer metal trace structure formed on the first metal layer, and the second trace structure includes a double-layer metal trace structure formed by alternating arrangement of the first metal layer and the second metal layer.

[0030] In some embodiments of this application, the fan-out traces formed by the second metal layer are connected to the corresponding scan lines through a bridging structure.

[0031] In some embodiments of this application, the bridging structure includes a first via, a second via, and a conductive layer. The first via is formed on a portion of the second insulating layer covering the second metal layer. The second via is formed on portions of the first and second insulating layers covering the first metal layer. The conductive layer covers the second insulating layer, connects to the second metal layer through the first via, and connects to the first metal layer through the second via. The first metal layer and the second metal layer are electrically connected through the conductive layer.

[0032] This application provides a display panel comprising a substrate, a pixel array, multiple scan lines, and a scan driving circuit. The substrate has a display area and a non-display area. The pixel array is disposed on the display area of ​​the substrate. Multiple scan lines are sequentially formed on the substrate and electrically connected to the pixel array. The scan driving circuit includes multiple scan units for electrically connecting the multiple scan lines, wherein each scan unit includes at least one holding capacitor, and the structure of the holding capacitor includes a first metal layer, a second metal layer, a first insulating layer, a second insulating layer, a first light-transmitting conductive layer, and a second light-transmitting conductive layer. The first metal layer is formed on the substrate. The first insulating layer is disposed on the first metal layer. The second metal layer is disposed on the first insulating layer. The first light-transmitting conductive layer is disposed on the first insulating layer and one end is electrically connected to the second metal layer. The second insulating layer is disposed on the second metal layer and the first light-transmitting conductive layer. The second light-transmitting conductive layer is disposed on the second insulating layer. At least a portion of the first metal layer has through-holes formed to expose the at least a portion of the first metal layer from the first insulating layer and the second insulating layer. The second transparent conductive layer is electrically connected to at least a portion of the area exposed by the first metal layer via the via.

[0033] In some embodiments of this application, a portion of the second metal layer extends onto the second transparent conductive layer, such that the second metal layer and the second transparent conductive layer at least partially overlap in the normal direction of the substrate.

[0034] In some embodiments of this application, the holding capacitance is the sum of a first capacitor, a second capacitor, and a third capacitor, wherein the first capacitor is formed based on a first overlapping region of the first metal layer and the second metal layer and a first insulating layer located in the first overlapping region, the second capacitor is formed based on a second overlapping region of the second metal layer and the first light-transmitting conductive layer and a second insulating layer located in the second overlapping region, and the third capacitor is formed based on a third overlapping region of the first light-transmitting conductive layer and the second light-transmitting conductive layer and a second insulating layer located in the third overlapping region.

[0035] This application provides a display panel comprising a substrate, a pixel array, multiple scan lines, and multiple data lines. The substrate has a display area and a non-display area. The pixel array is disposed on the display area of ​​the substrate and has multiple pixel units arranged in an array. Multiple scan lines are formed on the substrate and electrically connected to each column of pixel units in the pixel array. Multiple data lines are formed on the substrate and electrically connected to each row of pixel units in the pixel array. The multiple pixel units include a first pixel unit, and the first pixel unit includes a thin-film transistor, a first insulating layer, a first metal layer, a second insulating layer, a common electrode, and an extended metal layer. The thin-film transistor has a first end, a second end, and a control end, wherein the first end is electrically connected to a corresponding data line, and the control end is electrically connected to a corresponding scan line. The first insulating layer is formed on the substrate. The first metal layer is formed on the first insulating layer and electrically connected to the second end of the thin-film transistor. The second insulating layer covers the first metal layer. A common electrode has a grid-like structure and is formed on the second insulating layer. The common electrode has a first portion and a second portion, wherein the first portion of the common electrode at least partially overlaps with the orthographic projection region of the first metal layer, and the second portion of the common electrode substantially does not overlap with the orthographic projection region of the first metal layer. An extended metal layer is electrically connected to the first metal layer and is covered by the second insulating layer, wherein at least a portion of the extended metal layer is formed within the orthographic projection region of the second portion of the common electrode.

[0036] In some embodiments of this application, the first pixel unit further includes a counter substrate, a liquid crystal layer, and a black matrix. The liquid crystal layer is formed between the common electrode and the counter substrate. The black matrix is ​​formed on the side of the counter substrate facing the substrate, wherein at least a portion of the orthographic projection region of the black matrix overlaps with the orthographic projection region of the second portion of the common electrode. The extended metal layer is located within the at least a portion of the orthographic projection region of the black matrix.

[0037] In some embodiments of this application, the pixel unit further includes a second pixel unit, and the second pixel unit includes an extended metal layer, wherein the extended metal layer of the first pixel unit and the extended metal layer of the second pixel unit are both located within the orthographic projection region of the second portion of the common electrode.

[0038] This application provides a display panel comprising a substrate, a pixel array, multiple scan lines, and multiple data lines. The substrate has a display area and a non-display area. The pixel array is disposed on the display area of ​​the substrate and has multiple pixel units arranged in an array. Multiple scan lines are formed on the substrate and electrically connected to each column of pixel units in the pixel array. Multiple data lines are formed on the substrate and electrically connected to each row of pixel units in the pixel array. The multiple pixel units include a first pixel unit and a second pixel unit. The first pixel unit is electrically connected to the nth scan line, and the second pixel unit is electrically connected to the (n+1)th scan line, where n is a natural number. The second pixel unit includes a thin-film transistor, a first insulating layer, a first metal layer, and a common electrode. The thin-film transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal is electrically connected to the corresponding data line, and the control terminal is electrically connected to the (n+1)th scan line. The first insulating layer is formed on the substrate and covers the nth scan line. A first metal layer is formed on the first insulating layer and electrically connects to the second end of the thin-film transistor, wherein the first metal layer has a first portion and a second portion. A common electrode has a gate-like structure and is formed on the second insulating layer, wherein the common electrode has a first portion and a second portion. The orthographic projection regions of the first portion of the first metal layer and the first portion of the common electrode at least partially overlap, and the orthographic projection regions of the second portion of the first metal layer, the second portion of the common electrode, and the nth scan line at least partially overlap.

[0039] In some embodiments of this application, the nth scan line located in two adjacent column pixel units includes a first line segment and a second line segment connected to each other, wherein the first line segment and the second line segment are not parallel to each other.

[0040] In some embodiments of this application, the overlapping area of ​​the orthographic projection region of the second portion of the first metal layer and the first segment of the nth scan line is approximately the same as the overlapping area of ​​the orthographic projection region of the second portion of the first metal layer and the second segment.

[0041] In some embodiments of this application, the overlapping area of ​​the orthographic projection region of the second portion of the first metal layer and one of the first line segment and the second line segment of the nth scan line is greater than the overlapping area of ​​the orthographic projection region of the second portion of the first metal layer and the other of the first line segment and the second line segment.

[0042] This application provides an electrostatic discharge (ESD) protection structure for an array substrate, comprising a glass substrate and multiple display panels. The multiple display panels are arranged adjacent to each other on the glass substrate. The common electrode of each display panel is connected to the common electrode of the adjacent display panel.

[0043] In some embodiments of this application, the display panels are all arranged in the same direction.

[0044] In some embodiments of this application, two adjacent rows or columns of display panels are arranged with a virtual symmetry line as a reference, facing opposite sides.

[0045] In some embodiments of this application, the common electrode of each display panel is connected to the common electrode of the adjacent display panel by at least one line.

[0046] This application provides an electrostatic discharge (ESD) protection structure for an array substrate, characterized by comprising: a glass substrate divided into multiple array blocks; and multiple display panels arranged adjacently in each of the array blocks of the glass substrate. Each array block comprises: at least one first metal layer disposed on the glass substrate surrounding at least two of the multiple display panels; a first insulating layer covering the first metal layer and exposing at least a portion of the first metal layer; at least one second metal layer disposed on the first insulating layer surrounding at least two of the multiple display panels; a second insulating layer covering the second metal layer and exposing at least a portion of the second metal layer; and multiple conductive layers passing through the first insulating layer and the second insulating layer at least in multiple bridging regions of the first metal layer, electrically connecting the first metal layer and the second metal layer.

[0047] In some embodiments of this application, when there are multiple first metal layers, the bridging region is located at least at the bend of the first metal layer.

[0048] In some embodiments of this application, when there are multiple first metal layers, the first insulating layer will separate the multiple first metal layers.

[0049] In some embodiments of this application, when there are multiple second metal layers, the second insulating layer will separate the multiple second metal layers.

[0050] In some embodiments of this application, when viewed from above, the distance between the side of the first metal layer that is electrically connected to the second metal layer through the conductive layer and the side of the second metal layer that is electrically connected to the first metal layer through the conductive layer that is far from the first metal layer is 200~300μm.

[0051] In some embodiments of this application, when viewed from above, the distance between the parallel sides of the first metal layer electrically connected by the conductive layer is 150~300μm.

[0052] This application also proposes an electrostatic discharge (ESD) protection structure, characterized in that it comprises: a glass substrate divided into multiple array blocks; and multiple display panels arranged adjacently in each of the array blocks of the glass substrate; wherein each of the array blocks has: multiple metal layers arranged sequentially on the glass substrate in a manner surrounding at least two of the multiple display panels; multiple insulating layers separating the multiple metal layers and exposing at least a portion of the multiple metal layers; and multiple conductive layers passing through the multiple insulating layers and electrically connecting the stacked multiple metal layers, at least in multiple bridging regions of the multiple metal layers.

[0053] This application provides a pixel array substrate, comprising a substrate, a pixel array, and an electrostatic discharge (ESD) protection structure. The substrate has a display area and a non-display area. The pixel array is disposed within the display area of ​​the substrate. The ESD protection structure is disposed within the non-display area of ​​the substrate and surrounds at least a portion of the frame area of ​​the substrate. The ESD protection structure has a plurality of light-transmitting portions arranged in sequence at intervals, each light-transmitting portion being formed by stacking at least an insulating layer and a transparent conductive layer.

[0054] This application provides an electrostatic discharge (ESD) protection structure suitable for installation on a non-display area of ​​a pixel array substrate in a display panel. The ESD protection structure comprises multiple metal strip patterns. These multiple metal strip patterns are respectively disposed in multiple border areas of the non-display area, wherein each metal strip pattern has multiple light-transmitting portions arranged in a sequentially spaced manner, and each light-transmitting portion is formed by stacking at least an insulating layer and a transparent conductive layer.

[0055] This application provides a display device comprising a display panel, a display driver chip, and a touch sensing chip. The display panel, in a cross-sectional configuration along a sectional direction, further comprises a substrate, a first metal layer, a plurality of light-emitting elements, a protective layer, and a second metal layer. The first metal layer is formed on the substrate and includes a plurality of first electrode regions and a plurality of second electrode regions, wherein the plurality of first electrode regions and the plurality of second electrode regions are electrically independent of each other and are alternately arranged on the substrate at intervals. Each light-emitting element includes a first electrode and a second electrode formed on opposite sides, the first electrode being electrically connected to a corresponding first electrode region. The protective layer fills the spaces between the plurality of light-emitting elements and covers at least a portion of the surface of each light-emitting element. The second metal layer is formed on the protective layer and includes a plurality of third electrode regions, wherein the plurality of third electrode regions are respectively formed on the plurality of light-emitting elements and electrically connected to the second electrode of the corresponding light-emitting element. The orthographic projection areas of the plurality of third electrode regions on the substrate do not completely overlap with the orthographic projection areas of the plurality of second electrode regions on the substrate.

[0056] This application provides a display panel comprising a substrate, a first metal layer, a plurality of light-emitting elements, a protective layer, and a second metal layer. The first metal layer is formed on the substrate and includes a plurality of first electrode regions and a plurality of second electrode regions, wherein the plurality of first electrode regions and the plurality of second electrode regions are electrically independent of each other and are alternately arranged on the substrate at intervals. Each light-emitting element includes a first electrode and a second electrode formed on opposite sides, the first electrode being electrically connected to a corresponding first electrode region. The protective layer fills the spaces between the plurality of light-emitting elements and covers at least a portion of the surface of each light-emitting element. The second metal layer is formed on the protective layer and includes a plurality of third electrode regions, wherein the plurality of third electrode regions are respectively formed on the plurality of light-emitting elements and are electrically connected to the second electrode of the corresponding light-emitting element. The orthographic projection areas of the plurality of third electrode regions on the substrate and the orthographic projection areas of the plurality of second electrode regions on the substrate do not overlap completely.

[0057] In some embodiments, the second metal layer further includes a plurality of fourth electrode regions, wherein the plurality of third electrode regions and the plurality of fourth electrode regions are electrically independent of each other, and the plurality of fourth electrode regions are electrically connected to the corresponding plurality of second electrode regions.

[0058] This application provides a display panel that includes a pixel array substrate or an electrostatic protection structure as described above.

[0059] Through one or more of the technical solutions described in this application, the display panel and its pixel array proposed in the embodiments of this application increase the equivalent area of ​​the pixel electrode by forming an additional extended metal layer. Since the extended metal layer is formed under the area covered by the common electrode and the black matrix, the aperture ratio / transmittance of the display panel can be maintained while increasing the pixel storage capacitance.

[0060] In addition, through one or more of the technical solutions described in this application, the electrostatic discharge (ESD) protection structure of the array substrate and the liquid crystal display panel proposed in the embodiments of this application can connect the capacitors of multiple display panels on the array substrate in series, thereby forming a larger capacitance, which helps to absorb the static electricity generated during the manufacturing process. This makes the glass substrate of the array substrate less prone to ESD (ESD damage), thus avoiding ESD damage to the metal lines in the TFT array substrate caused by high temperatures, and preventing the indium tin oxide (ITO) electrodes from becoming opaque, reducing defects in the insulating layer, and enabling accurate voltage setting between the electrodes. Furthermore, the embodiments of this application can effectively prevent damage to the structure of the array substrate. Moreover, the embodiments of this application are applicable regardless of how the multiple display panels on the glass substrate of the array substrate are arranged.

[0061] In addition, through one or more of the technical solutions described in this application, the electrostatic discharge (ESD) protection structure of the array substrate proposed in the embodiments of this application can achieve ESD protection even when a small-sized display panel is configured on the array substrate without test circuit traces. Furthermore, because the first metal layer and the second metal layer are a double-layer structure, the horizontal area generated by the configuration on the array substrate can be reduced, thereby increasing the number of display panels that can be configured on the array substrate. Moreover, because the first metal layer and the second metal layer are a double-layer structure, the overall impedance of the array substrate is lower, making it easier to achieve the functions of attracting and dissipating static electricity.

[0062] In addition, through one or more of the technical solutions described in this application, the electrostatic protection structure of the pixel array substrate proposed in this embodiment has a design with multiple light-transmitting parts. This reduces large-area metal obstruction, allowing UV light to irradiate the frame adhesive FP coating area through the light-transmitting parts during the frame bonding process of the display panel. This enables the UV light to better irradiate the frame adhesive, thereby improving the curing rate of the frame adhesive and thus further improving the yield and reliability of panel assembly. Furthermore, because the light-transmitting parts of the electrostatic protection structure are formed of transparent conductive material, the light-transmitting parts do not cause a reduction in the equivalent area of ​​the metal strip pattern. Therefore, the electrostatic dissipation capability of the electrostatic protection structure can be maintained, and the electrostatic dissipation capability is not reduced due to the setting of the light-transmitting parts.

[0063] On the other hand, compared with the traditional electrostatic discharge ring design, the electrostatic protection structure with inner and outer ring structures proposed in this application has a larger width in the cross-sectional direction, which can increase the effective conductive area of ​​the electrostatic protection structure and further improve the electrostatic dissipation capability.

[0064] In addition, through one or more of the technical solutions described in the embodiments of this application, the display device and display panel proposed in the embodiments of this application can form independent electrodes in the display panel for touch sensing, so that the signal timing during the display period and the touch sensing period can be independent of each other, avoiding the problem of needing to make trade-offs.

[0065] In addition, through one or more of the technical solutions described in the embodiments of this application, the display device and display panel proposed in the embodiments of this application can keep the upper surface of all light-emitting elements basically at the same level without any height difference. Therefore, the subsequent process will not be affected by the flatness of the display panel, thereby effectively improving the process yield and reliability. Simple Explanation of the Diagram

[0066] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort. Figure 1 is a schematic diagram of the configuration of the display device according to an embodiment of this application; Figures 2A and 2B are schematic diagrams illustrating the component configuration of a display device and its display panel according to some embodiments of this application; Figures 3A and 3B are schematic diagrams of scan driving circuits according to some embodiments of this application; Figures 4A to 6B are circuit diagrams of the scanning drive circuits of different embodiments of this application; Figures 7A to 8B are schematic diagrams illustrating the structural configuration of the holding capacitor in the scan drive circuit of different embodiments of this application; Figures 9A to 12 are schematic diagrams illustrating the configuration of the display panel and its fan-out wiring according to different embodiments of this application; Figure 13 is a schematic diagram of the equivalent circuit of the pixel array according to an embodiment of this application; Figures 14A to 18C are schematic diagrams illustrating the structural configuration of pixel arrays in different embodiments of this application; Figure 19 is a voltage-current relationship diagram of the thin-film transistor of the pixel unit in some embodiments of this application; Figure 20 is a schematic diagram of the array substrate configuration of some embodiments of this application; Figure 21 is a schematic diagram of the configuration of adjacent display panels on an array substrate according to some embodiments of this application; Figures 22A and 22B are schematic diagrams showing the configuration of the display panel on the array substrate of this application; Figures 23A to 24B are schematic diagrams showing the electrostatic protection structure configured within the array block of the array substrate according to different embodiments of this application; Figures 25A and 25B are schematic diagrams illustrating the configuration of pixel array substrates according to different embodiments of this application; Figures 26A and 26B are schematic diagrams of the pixel array substrate and its electrostatic protection structure from different perspectives according to embodiments of this application; Figures 27A to 27C are schematic diagrams of the top view and cross-sectional structure of a display panel; Figures 28A to 30G are top and cross-sectional structural schematic diagrams of the display panel according to different embodiments of this application; and Figure 31 is a schematic diagram of signal waveforms of a display device according to some embodiments of this application. Implementation

[0067] To make the features and advantages of the embodiments of this application more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following description contains specific information related to exemplary embodiments in the embodiments of this application. The accompanying drawings and detailed descriptions in the embodiments of this application are merely exemplary embodiments. However, the embodiments of this application are not limited to these exemplary embodiments. Other variations and embodiments of the embodiments of this application will be apparent to those skilled in the art. Unless otherwise stated, the same or corresponding elements in the drawings may be indicated by the same or corresponding reference numerals. Furthermore, the drawings and illustrations in the embodiments of this application are generally not drawn to scale and are not intended to correspond to actual relative dimensions.

[0068] It should be noted that the terms "vertical," "left," "right," "up," "down," and similar expressions used in this article are only for indicating relative positional relationships based on diagrams, and do not limit the components using these terms to only be implemented in a representational manner. When the absolute position of the described object changes, the description of the relative position may also change accordingly.

[0069] For the purposes of consistency and ease of understanding, the same features are indicated by reference numerals in the exemplary drawings (although this is not the case in some examples). However, features in different embodiments may differ in other respects, and therefore should not be narrowly limited to the features shown in the drawings.

[0070] The terms "first," "second," and "third," etc., in the specification and accompanying drawings of the embodiments of this application are used to distinguish different objects, areas, levels, or steps, and are not used to describe a specific order (unless otherwise specified in the scope of the patent application).

[0071] The terms "connection" or "coupling" used in the embodiments of this application do not imply that there can be no space between the objects. That is, the connection or coupling between two objects can mean that the two objects are directly connected / coupled to each other, or that they are connected / coupled to each other through other objects.

[0072] In all descriptions related to specific numerical values ​​in the embodiments of this application, although not directly described, they all contain the meaning of "approximately," that is, these specific numerical values ​​will cover the possible numerical error range, thereby representing possible unintended effects and deviations in the process or material selection. The numerical error range may include numerical changes that do not significantly change the material structure, properties, or effects, such as a range of 0% to 10% deviation. This error range is clear to those with ordinary knowledge in the art.

[0073] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0074] Figure 1 is a schematic diagram of the configuration of the display device according to an embodiment of this application. Referring to Figure 1, the display device 10 in this embodiment may be, for example, a liquid crystal display (LCD) device, which includes a backlight module 100 and a display panel D100. The backlight module 100 and the display panel D100 are disposed on the xy plane, and the display panel D100 is disposed on the backlight module 100 along the z-axis. The backlight module 100 is used to provide sufficient brightness and uniformly distributed light source toward the display panel D100. The display panel D100 is used to control and adjust the light passing through it, so as to display a corresponding image thereon. In this embodiment, the display device 10 may be any electronic device with display function, such as a television, a screen, a laptop computer, or a mobile phone, and this application is not limited thereto.

[0075] The backlight module 100 includes a light-emitting layer 110, wherein the light-emitting layer 110 includes a plurality of light-emitting elements (LEDs) arranged in an array. The light-emitting elements (LEDs) can be used to emit light towards the display panel D100. In some embodiments, the light-emitting elements (LEDs) can be white, red, green, or blue light-emitting diodes (or light-emitting diodes with emission wavelengths in the white, red, green, or blue light range), or combinations of the above-mentioned light-emitting diodes, and this application is not limited thereto.

[0076] Furthermore, in some embodiments, the backlight module 100 may further include a quantum dot film 120 and an optical adjustment layer 130, wherein the quantum dot film 120 is disposed on the light-emitting layer 110, and the optical adjustment layer 130 is disposed on the quantum dot film 120, that is, the quantum dot film 120 is disposed between the light-emitting layer 110 and the optical adjustment layer 130. In embodiments where the quantum dot film 120 is disposed, the light-emitting elements LEDs may be, for example, blue light-emitting diodes.

[0077] A quantum dot film 120 is disposed on the light transmission path of the light-emitting layer 110 and is used to adjust the wavelength of some of the light emitted by the light-emitting elements LEDs, while allowing another portion of the light emitted by the LEDs to pass through directly without adjustment. For example, when the light-emitting elements LEDs emit light in the blue light wavelength range (e.g., 400nm-520nm), the quantum dot film 120 can adjust the wavelength of the first portion of the received light to the red light wavelength range (e.g., 610nm-720nm), adjust the wavelength of the second portion of the received light to the green light wavelength range (e.g., 520nm-610nm), and maintain the third portion of the received light in the blue light wavelength range for direct output without adjustment. In this way, the first to third portions of light emitted by the light-emitting layer 110 can mix to form white light after passing through the quantum dot film 120.

[0078] The optical adjustment layer 130 is also located on the light transmission path of the light-emitting layer 110 and is used to adjust the direction of the received light so as to make the transmitted light source more uniform. In some embodiments, the optical adjustment layer 130 includes a plurality of optical microstructures (not shown) and / or optical films (not shown) for adjusting the direction of light, but this application is not limited thereto.

[0079] The display panel D100 includes, for example, a pixel array, a counter substrate, and a non-self-emissive display medium, wherein the pixel array and the counter substrate are disposed opposite to each other, and the non-self-emissive display medium is disposed between the pixel array and the counter substrate. In some embodiments, the non-self-emissive display medium may be, for example, liquid crystal, but this application is not limited thereto. Specific configuration embodiments of the pixel array will be further described later.

[0080] From the perspective of circuit configuration and display driving, in some embodiments, the configuration of the display device 20 and its display panel D100 can be as shown in Figures 2A and 2B, where Figure 2A is a top view of the display device 20 and Figure 2B is a side view of the display device 20. For ease of explanation, Figure 2A shows the internal components of the display device 20 unfolded in the xy plane, while Figure 2B shows the configuration of the internal components of the display device 20 within the housing. From a packaging perspective, this embodiment is a display device using GOP packaging technology.

[0081] Referring to Figures 2A and 2B, in this embodiment, the display device 20, in addition to the backlight module and display panel D100 described above, may also include a scan driving circuit D120, a data driving circuit D130, a connection module D140, and a control circuit D150 for driving the display panel D100. The display panel D100 has a display area DR and a non-display area SR, where the display area DR is the area used to display images; and the non-display area SR is the area of ​​the display panel D100 where images are not displayed. The non-display area SR typically surrounds the display area DR and can also be considered as the border area of ​​the display panel D100. The scan driving circuit D120 and the data driving circuit D130 are disposed in the non-display area SR of the display panel D100. In the figures, the scan driving circuit D120 is exemplified by being disposed in the non-display areas SR on the left and right sides of the display panel D100, and the data driving circuit D130 is exemplified by being disposed in the non-display area SR on the lower side of the display panel D100, but this application is not limited thereto. One end of the connecting module D140 is located on the side of the non-display area SR near the data driving circuit D130, and the control circuit D150 is coupled to the other end of the connecting module D140.

[0082] Specifically, the display panel D100 may include a substrate D111 and a pixel array D112 located in the display area DR. The pixel array D112 is disposed on the substrate D111 and includes, for example, pixel units Pu arranged in an m×n array, that is, m columns and n rows, where m and n can be natural numbers selected according to design requirements, and this application does not limit them.

[0083] From the electrical relationship between the components, the scan driving circuit D120 is electrically connected to the display panel D100 via traces on the substrate D111. The data driving circuit D130 is electrically connected to the display panel D100 via the first transmission section WR1, and to the connection module D140 via the second transmission section WR2. On the other hand, the control circuit D150 is electrically connected to the data driving circuit D130 via the connection module D140 and the second transmission section WR2. The first transmission section WR1 and the second transmission section WR2 can be transmission lines formed on the substrate D111.

[0084] The scan drive circuit D120 is used to generate scan signals to enable / disable pixels row by row according to timing control signals. In this embodiment, the scan drive circuit D120 is illustrated as two configurations for enabling pixels in odd-numbered columns and pixels in even-numbered rows, respectively. The left scan drive circuit D120 is illustrated as including scan units s121_1, s121_3, ..., s121_m-1 connected to the odd-numbered scan lines, and the right scan drive circuit D120 is illustrated as including scan units s121_2, s121_4, s121_m connected to the even-numbered scan lines, but this application is not limited to these. In this embodiment, scan unit s121_x represents any one of the left scan units s121_1, s121_3, ..., s121_m-1, and scan unit s121_y represents any one of the right scan units s121_2, s121_4, s121_m. In other words, x can be any odd number less than m, and y can be any even number less than or equal to m, where m is an even number, but this application is not limited thereto.

[0085] The data driving circuit D130 is used to generate driving signals for the pixel array D112 according to the data control signal. Although the drawings of this embodiment illustrate a single data driving circuit D130 for illustrative purposes, this application is not limited thereto. In some embodiments, the data driving circuit D130 may be integrated into multiple driving chips, wherein the multiple driving chips can collaboratively drive pixels in different parts / regions of the pixel array D112.

[0086] More specifically, pixels in the same column of pixel array D112 correspond to the same scan line, and pixels in the same row of pixel array D112 correspond to the same data line. Pixel array D112 is electrically connected to scan drive circuit D120 via scan lines to receive scan signals, and is electrically connected to data drive circuit D130 via data lines and first transmission unit WR1 to receive data drive signals provided by data drive circuit D130. Data drive circuit D130 provides data drive signals in coordination with the turn-on timing of pixel array D112, so that pixel array D112 adjusts the passing light according to the data drive signals, thereby presenting the corresponding image in display area DR.

[0087] The connection module D140 provides a signal transmission path between the data driving circuit D130 and the control circuit D150, allowing the data control signals generated by the control circuit D150 to be transmitted to the data driving circuit D130 through the connection module D140 and the second transmission unit WR2. In some embodiments, the connection module D140 can be a flexible circuit board (hereinafter referred to as flexible circuit board D140), as shown in FIG1C. The flexible circuit board D140 has multiple connection terminals at both ends. The connection terminals on the side of the flexible circuit board D140 closest to the data driving circuit D130 are disposed on the substrate D111, and the connection terminals on the side closest to the control circuit D150 are disposed on the circuit board of the control circuit D150. The portion of the flexible circuit board D140 closest to the data driving circuit D130 and containing the connection terminals is attached to the substrate D111, wherein the width of the attached portion is approximately the distance from the top of the connection terminal of the flexible circuit board D140 to the edge 111e of the substrate.

[0088] During assembly, the flexible circuit board D140 of the display device 20 is bent so that the control circuit D150 is positioned on the back of the display panel D100 (i.e., on the other side of the substrate D111 opposite to the display area DR). In other words, when the display device 20 is assembled, the control circuit D150, the substrate D111, and the data driving circuit D130 inside the display device 20 are arranged sequentially along the z-axis.

[0089] The pixel array D112 of the display panel D100 includes a plurality of thin-film transistors (not shown). These transistors turn on or off in response to received signals, thereby controlling the operation of corresponding pixels to achieve the effect described above, adjusting the passing light according to the data drive signal, thereby presenting the corresponding image in the display area DR. From another perspective, the display panel D100 also includes a common electrode (not shown), where the display area DR can be considered as the area where the common electrode and the pixel array D112 overlap, and (at least partially) the non-display area SR can be considered as the area where the common electrode does not overlap with the pixel array D112.

[0090] The functional module configuration of each scanning unit s121_1-s121_m in the scanning drive circuit D120 described in this embodiment can be shown in Figures 3A and 3B. Figure 3A is a circuit diagram of the scanning unit s121_x (i.e., x can be any odd number between 1 and m, such as s121_1, s121_3, ... s121_m-1) that connects an odd number of scanning lines, and Figure 3B is a circuit diagram of the scanning unit s121_y (i.e., x can be any even number between 1 and m, such as s121_2, s121_4, ... s121_m) that connects an even number of scanning lines.

[0091] Referring first to Figure 3A, in this embodiment, the scanning unit 121x includes a first module MD1, a second module MD2, and a third module MD3. The first module MD1 is electrically connected to the scanning output terminals Gx-2 of the first two scanning units and Gx+2 of the last two scanning units, and generates a drive signal on node N1 based on the scanning signals from the scanning output terminals Gx-2 and Gx+2. The second module MD2 is electrically connected to the first module MD1 through node N1, and determines the pull-up timing of the scanning signal output from the scanning output terminal Gx based on the drive signal on node N1, the clock signal CK1, and the reference signal VSS. The third module MD3 is electrically connected to the second module MD2 and the scanning output terminal Gx, and determines the pull-down timing of the scanning signal output from the scanning output terminal Gx based on the clock signal CK2 and the reference signal VSS.

[0092] Referring to Figure 3B, in this embodiment, the scanning unit 121y includes a fourth module MD4, a fifth module MD5, and a sixth module MD6. The connection relationship and relative configuration of the fourth to sixth modules MD4-MD6 can be similar to those of the first to third modules MD1-MD3 in the aforementioned embodiment. The only difference between the two is the timing of the received clock signals CK3 and CK4.

[0093] In some embodiments, clock signals CK1 and CK2 are out of phase, and clock signals CK3 and CK4 are out of phase. In some embodiments, the phase of clock signal CK3 lags behind the phase of clock signal CK1 by approximately 90 degrees, the phase of clock signal CK2 lags behind the phase of clock signal CK3 by approximately 90 degrees, and the phase of clock signal CK4 lags behind the phase of clock signal CK2 by approximately 90 degrees.

[0094] In addition, the relevant descriptions of the fourth to sixth modules MD4-MD6 of the scanning unit 121y can be found in the descriptions of the first to third modules MD1-MD3 mentioned above, and will not be repeated here.

[0095] The following figures 4A to 6B further illustrate specific circuit configuration embodiments of the scanning drive circuit D120 described above. Figures 4A and 4B illustrate one circuit configuration embodiment of scanning units 121_x and 121_y, Figures 5A and 5B illustrate another circuit configuration embodiment of scanning units 121_x and 121_y, and Figures 6A and 6B illustrate yet another circuit configuration embodiment of scanning units 121_x and 121_y.

[0096] Please refer to Figure 4A first. The scanning unit 121_x in this embodiment includes transistors M1-M7 and capacitors C1 and C2. Transistors M1 and M2 can form the first module MD1 as shown in Figure 3A, transistors M3-M5 and capacitors C1 and C2 can form the second module MD2 as shown in Figure 3A, and transistors M6 and M7 can form the third module MD3 as shown in Figure 3A. In other words, the first module MD1 in Figure 3A may, for example, include transistors M1 and M2, the second module MD2 may, for example, include transistors M3-M5 and capacitors C1 and C2, and the third module MD3 may, for example, include transistors M6 and M7. However, this application is not limited to this.

[0097] In this embodiment, transistors M1-M7 each have a first terminal, a second terminal, and a control terminal. The transistors M1-M7 can be, for example, N-type transistors or P-type transistors, and this application is not limited thereto. If the transistor is an N-type transistor, the first terminal can be, for example, a drain, the second terminal can be, for example, a source, and the control terminal can be, for example, a gate. If the transistor is a P-type transistor, the first terminal can be, for example, a source, the second terminal can be, for example, a drain, and the control terminal can be, for example, a gate.

[0098] The first terminal of transistor M1 is used to receive the first scan control signal D2U. The second terminal of transistor M1 is electrically connected to node N1, and the control terminal of transistor M1 is used to receive the scan output terminal Gx-2 of the first two stages of the scan unit. The first terminal of transistor M2 is electrically connected to the second terminal of transistor M1. The second terminal of transistor M2 is used to receive the second scan control signal U2D, and the control terminal of transistor M2 is used to receive the scan output terminal Gx+2 of the last two stages of the scan unit.

[0099] The first terminal of transistor M3 is electrically connected to the second terminal of transistor M1 and the first terminal of transistor M2 via node N1, and the second terminal of transistor M3 is used to receive the clock signal CK1. The first terminal of transistor M4 is electrically connected to the control terminal of transistor M3, the second terminal of transistor M4 is used to receive the reference signal VSS, and the control terminal of transistor M4 is electrically connected to node N1. In this embodiment, the reference signal VSS is taken as a reference low level. The first terminal of transistor M5 is electrically connected to the scan output terminal Gx of scan unit 121_x, the second terminal of transistor M5 is used to receive the clock signal CK1, and the control terminal of transistor M5 is electrically connected to the first terminal of transistor M3 and node N1. The first terminal of capacitor C1 is electrically connected to the control terminal of transistor M3 and the first terminal of transistor M4, and the second terminal of capacitor C1 is used to receive the clock signal CK1. The first terminal of capacitor C2 is electrically connected to the first terminal of transistor M5 and the scan output terminal Gx, and the second terminal of capacitor C2 is electrically connected to the first terminal of transistor M3, the control terminal of transistor M5, and node N1.

[0100] The first terminal of transistor M6 is electrically connected to the scan output terminal Gx. The second terminal of transistor M6 is used to receive the reference signal VSS. The control terminal of transistor M6 is electrically connected to the control terminal of transistor M3, the first terminal of transistor M4, and the first terminal of capacitor C1. The first terminal of transistor M7 is electrically connected to the first terminal of transistor M6 and the scan output terminal Gx. The second terminal of transistor M7 is used to receive the reference signal VSS. The control terminal of transistor M7 is used to receive the clock signal CK2.

[0101] Referring to Figure 4B, the scanning unit 121_y in this embodiment includes transistors M8-M14 and capacitors C3 and C4. Transistors M8 and M9 can form the fourth module MD5 as shown in Figure 3B, transistors M10-M12 and capacitors C3 and C4 can form the fifth module MD5 as shown in Figure 3B, and transistors M13 and M14 can form the sixth module MD6 as shown in Figure 3B. In other words, the fourth module MD4 in Figure 3B may, for example, include transistors M8 and M9, the fifth module MD5 may, for example, include transistors M10-M12 and capacitors C3 and C4, and the sixth module MD6 may, for example, include transistors M13 and M14. However, this application is not limited to this.

[0102] In this embodiment, transistors M8-M14 each have a first terminal, a second terminal, and a control terminal. The transistors M8-M14 can be, for example, N-type transistors or P-type transistors, and this application is not limited thereto. If the transistor is an N-type transistor, the first terminal can be, for example, a drain, the second terminal can be, for example, a source, and the control terminal can be, for example, a gate. If the transistor is a P-type transistor, the first terminal can be, for example, a source, the second terminal can be, for example, a drain, and the control terminal can be, for example, a gate.

[0103] The first terminal of transistor M8 is used to receive the first scan control signal D2U. The second terminal of transistor M1 is electrically connected to node N2, and the control terminal of transistor M8 is used to receive the scan output terminal Gy-2 of the first two stages of the scan unit. The first terminal of transistor M9 is electrically connected to the second terminal of transistor M8. The second terminal of transistor M9 is used to receive the second scan control signal U2D, and the control terminal of transistor M9 is used to receive the scan output terminal Gy+2 of the last two stages of the scan unit.

[0104] The first terminal of transistor M10 is electrically connected to the second terminals of transistors M8 and M9 via node N2, and the second terminal of transistor M10 is used to receive the clock signal CK3. The first terminal of transistor M11 is electrically connected to the control terminal of transistor M10, the second terminal of transistor M11 is used to receive the reference signal VSS, and the control terminal of transistor M11 is electrically connected to node N2. In this embodiment, the reference signal VSS is a reference low level. The first terminal of transistor M12 is electrically connected to the scan output terminal Gy of scan unit 121_y, the second terminal of transistor M12 is used to receive the clock signal CK3, and the control terminal of transistor M12 is electrically connected to the first terminal of transistor M10 and node N2. The first terminal of capacitor C3 is electrically connected to the control terminal of transistor M10 and the first terminal of transistor M11, and the second terminal of capacitor C3 is used to receive the clock signal CK3. The first terminal of capacitor C4 is electrically connected to the first terminal of transistor M12 and the scan output terminal Gy, and the second terminal of capacitor C4 is electrically connected to the first terminal of transistor M10, the control terminal of transistor M12, and node N2.

[0105] The first terminal of transistor M13 is electrically connected to the scan output terminal Gy. The second terminal of transistor M13 is used to receive the reference signal VSS. The control terminal of transistor M13 is electrically connected to the control terminal of transistor M10, the first terminal of transistor M11, and the first terminal of capacitor C3. The first terminal of transistor M14 is electrically connected to the first terminal of transistor M13 and the scan output terminal Gy. The second terminal of transistor M14 is used to receive the reference signal VSS. The control terminal of transistor M14 is used to receive the clock signal CK4.

[0106] In other words, the configuration of transistors M8-M14 in this embodiment is similar to that of transistors M1-M7 in the embodiment of FIG4A, and the configuration of capacitors C3 and C4 is similar to that of capacitors C1 and C2 in the embodiment of FIG4A. The difference between this embodiment and the embodiment of FIG4A is that transistors M10-M12 mainly operate with reference to clock signal CK3, and transistor M14 operates with reference to clock signal CK4. In the above embodiments, capacitors C1-C4 can also be called holding capacitors, which can be used to stabilize the voltage on the connected node. Structurally, the holding capacitor can be formed by the configuration between the metal layer and the insulating layer on the display panel. This will be further explained in subsequent embodiments.

[0107] In the driving architecture shown in Figures 4A and 4B, a DC voltage is required to control the operation of the transistors. However, applying a DC voltage to the transistors for an extended period can easily cause the transistor characteristics to deviate, leading to display abnormalities during long-term use or aging tests. For example, as shown in Figures 4A and 4B, transistors M1 / M8 continuously receive a DC voltage from the first scan control signal D2U during operation. As the operating time increases, the current-voltage characteristic curve (IV curve) of transistors M1 / M8 gradually shifts to the right, causing the leakage current of transistors M1 / M8 to gradually increase, eventually leading to display abnormalities.

[0108] In addition, with the configurations shown in Figures 4A and 4B, at least seven signal lines must be provided on the display panel to supply the control signals and clock signals (such as U2D, D2U, CK1-CK4, VSS, etc.) required for the operation of the scanning units 121_x / 121_y. This limits the size of the non-display area of ​​the display panel, making it difficult to implement a narrow bezel design.

[0109] The driving architecture illustrated in Figures 5A to 6B can solve the problems of the above embodiments, and can effectively improve the quality of the display panel, extend the service life of the display panel, and further realize the design of narrow bezels.

[0110] Referring to Figures 5A and 5B, the configuration of transistors M1-M7 is similar to that of transistors M1-M7 in the embodiment of Figure 4A, and the configuration of capacitors C1 and C2 is similar to that of capacitors C1 and C2 in the embodiment of Figure 4A; transistors M8-M14, and the configuration of capacitors C3 and C4 is similar to that of capacitors C3 and C4 in the embodiment of Figure 4B.

[0111] The main difference between this embodiment and the embodiments shown in Figures 4A and 4B is that the first terminal of transistors M1 / M8 is electrically connected to its control terminal, so as to replace the original first scan control signal D2U with the scan signals from the scan output terminals Gx-2 / Gy-2 of the first two stages. Furthermore, the second terminal of transistors M2 / M9 is electrically connected to a signal line with a reference signal VSS, thereby replacing the original second scan control signal U2D with the reference signal VSS.

[0112] From another perspective, transistor M1, configured as shown in Figure 5A, is equivalent to a diode. Therefore, when an enable level (such as a high level) scan signal is applied to the control terminal of transistor M1, transistor M1 can directly transmit the enable level to its second terminal. Similarly, transistor M8, configured as shown in Figure 5B, is equivalent to a diode. Therefore, when an enable level (such as a high level) scan signal is applied to the control terminal of transistor M8, transistor M8 can directly transmit the enable level to its second terminal.

[0113] Figures 6A and 6B are schematic diagrams of a scanning drive circuit according to another embodiment of this application. Referring to Figures 6A and 6B simultaneously, the configuration of transistors M1-M7 is similar to that of capacitors C1 and C2 in the embodiment of Figure 4A; transistors M8-M14, and the configuration of capacitors C3 and C4 is similar to that of capacitors C3 and C4 in the embodiment of Figure 4B.

[0114] The main difference between this embodiment and the embodiments shown in Figures 4A and 4B is that the first terminal of transistor M1 is electrically connected to the signal line of clock signal CK2, so as to replace the original DC high-level first scan control signal D2U with clock signal CK2. Furthermore, the second terminal of transistor M2 is electrically connected to the signal line with reference signal VSS, so as to replace the original second scan control signal U2D with reference signal VSS. Similarly, the first terminal of transistor M8 is electrically connected to the signal line of clock signal CK4, so as to replace the original DC high-level first scan control signal D2U with clock signal CK4. Furthermore, the second terminal of transistor M9 is electrically connected to the signal line with reference signal VSS, so as to replace the original second scan control signal U2D with reference signal VSS.

[0115] More specifically, with the above configuration, the scanning circuits 121_x / 121_y can apply a high DC level to the first terminal of transistors M1 / M8 via clock signals CK2 / CK4 when transistors M1 / M8 are turned on (i.e., when the control terminal receives an enable scanning signal), thus not affecting the operation of transistors M1 / M8. Similarly, for transistors M2 / M9, electrically connecting their second terminal to the reference signal VSS has the same effect as connecting it to the second scan control signal U2D. Therefore, by electrically connecting the first terminal of transistors M1 / M8 to the signal line of clock signals CK2 / CK4, using clock signals CK2 / CK4 as the first scan control signal D2U, and electrically connecting the second terminal of transistors M2 / M9 to the signal line transmitting the reference signal VSS, the signal lines used to transmit the first scan control signal D2U and the second scan control signal U2D can be omitted, thereby further reducing the width of the non-display area of ​​the display panel.

[0116] Figures 7A to 8B are schematic diagrams of the structural configuration of the holding capacitor in the scanning drive circuit of different embodiments of this application, wherein Figures 7A and 7B are schematic diagrams of the structure of one holding capacitor, and Figures 8A and 8B are schematic diagrams of the structure of another holding capacitor.

[0117] Please refer to Figures 7A and 7B simultaneously. Figure 7A is a top view of the display panel D100 in the capacitor holding region according to this embodiment, and Figure 7B is a cross-sectional view of the display panel D100 along the cut-off line AA'. In this embodiment, the display panel D100 includes a first metal layer ML1, a first insulating layer IL1, a second metal layer ML2, and a second insulating layer IL2 sequentially stacked on a substrate D111. The first metal layer ML1 is covered by the first insulating layer IL1, the second metal layer ML2 is disposed on the first insulating layer IL1, and the second insulating layer IL2 covers the first insulating layer IL1 and the second metal layer ML2. The stacked structure of the display panel D100 is bonded to the upper substrate D111' using a sealant SG. In other words, the first metal layer ML1, the first insulating layer IL1, the second metal layer ML2, and the second insulating layer IL2 are fixed between the substrates D111 and D111' using the sealant SG.

[0118] In this embodiment, the first metal layer ML1, the second metal layer ML2, and the first insulating layer IL1 spaced therebetween constitute a holding capacitor Ch, wherein the capacitance value of the holding capacitor Ch is related to the area of ​​the overlapping portion of the first metal layer ML1 and the second metal layer ML2 and the equivalent distance between the first metal layer ML1 and the second metal layer ML2 (i.e., the thickness of the first insulating layer IL1 in the overlapping portion of the first metal layer ML1 and the second metal layer ML2).

[0119] Specifically, during the assembly of the display device, the display panel D100 and the color filter (not shown) disposed thereon are typically bonded together using sealant, and ultraviolet light is used for curing during the bonding process. However, as shown in the top view of Figure 7A, most of the holding capacitor Ch is composed of opaque overlapping metal layers ML1 and ML2, and the holding capacitor Ch is usually located near the edge of the display panel D100 in the corresponding scanning units s121_1-s121_m. Therefore, during the ultraviolet curing process, since the ultraviolet light cannot penetrate the opaque holding capacitor, the curing effect of the sealant is affected, thereby reducing the assembly reliability of the display device.

[0120] To address the problems of the above embodiments, this application proposes a capacitor holding structure as shown in Figures 8A and 8B, wherein Figure 8A is a top view of the display panel D100 in the capacitor holding region of this embodiment, and Figure 8B is a cross-sectional view of the display panel D100 along the cut-off line BB'.

[0121] Referring simultaneously to Figures 8A and 8B, in this embodiment, the display panel D100 includes a first metal layer ML1, a first insulating layer IL1, a second metal layer ML2, and a second insulating layer IL2 sequentially stacked on a substrate D111. The first metal layer ML1 is covered by the first insulating layer IL1, the second metal layer ML2 is disposed on the first insulating layer IL1, and the second insulating layer IL2 covers both the first insulating layer IL1 and the second metal layer ML2. Furthermore, at least a portion of the first metal layer ML1 has vias THx formed therein, allowing the first metal layer ML1 to be exposed from the first insulating layer IL1 and the second insulating layer IL2 through the vias THx.

[0122] The display panel D100 also includes a first conductive layer CL1 and a second conductive layer CL2. The first conductive layer CL1 is formed on the second insulating layer IL2 and is electrically connected to the first metal layer ML1 through a via THx. Specifically, the first conductive layer CL1 extends from the upper surface of the second insulating layer IL2 toward the sidewall of the via THx, and covers the first metal layer ML1 exposed at the bottom of the via THx through the second insulating layer IL2 and the first insulating layer IL1. The second conductive layer CL2 is formed on the first insulating layer IL1 and is electrically connected to the second metal layer ML2. In this embodiment, the first conductive layer CL1 and the second conductive layer CL2 are implemented using a light-transmitting conductive material, such as an ITO conductive film. Therefore, the first conductive layer CL1 and the second conductive layer CL2 in this embodiment can also be referred to as the first light-transmitting conductive layer CL1 and the second light-transmitting conductive layer CL2.

[0123] In this embodiment, the side where the second metal layer ML2 is electrically connected to the second conductive layer CL2 can be formed by extending a portion of the second metal layer ML2 onto the second conductive layer CL2, so that the second metal layer ML2 and the second conductive layer CL2 at least partially overlap in the z-direction (i.e., the normal direction of the substrate D111). However, this application is not limited to this.

[0124] Specifically, a first metal layer ML1, a second metal layer ML2, and a first insulating layer IL1 spaced therebetween constitute capacitor Ceq1; a second metal layer ML2, a first conductive layer CL1, and a second insulating layer IL2 spaced therebetween constitute capacitor Ceq2; and a first conductive layer CL1, a second conductive layer CL2, and a second insulating layer IL2 spaced therebetween constitute capacitor Ceq3. Since the first metal layer ML1 and the first conductive layer CL1 are short-circuited together, and the second metal layer ML2 and the second conductive layer CL2 are short-circuited together, the holding capacitor Ch in this embodiment can be equivalently represented as the sum of capacitors Ceq1, Ceq2, and Ceq3. In other words, capacitor Ceq1 is constructed based on a first overlapping region of the first metal layer ML1 and the second metal layer ML2, and the first insulating layer IL1 located within the first overlapping region. Capacitor Ceq2 is constructed based on a second overlapping region of the second metal layer ML2 and the first conductive layer CL1, and the second insulating layer IL2 located within the second overlapping region. The capacitor Ceq3 is constructed based on the third overlapping region of the first transparent conductive layer CL1 and the second transparent conductive layer CL2, and the second insulating layer IL2 located in the third overlapping region.

[0125] Furthermore, the capacitance value of capacitor Ch is determined by the area of ​​the overlapping portion of the first metal layer ML1 and the second metal layer ML2, the equivalent distance between the first metal layer ML1 and the second metal layer ML2 (i.e., the thickness of the first insulating layer IL1 in the overlapping portion of the first metal layer ML1 and the second metal layer ML2), the area of ​​the overlapping portion of the second metal layer ML2 and the first conductive layer CL1, the equivalent distance between the second metal layer ML2 and the first conductive layer CL1 (i.e., the thickness of the second insulating layer IL2 in the overlapping portion of the second metal layer ML2 and the first conductive layer CL1), the area of ​​the overlapping portion of the first conductive layer CL1 and the second conductive layer CL2 (excluding the portion overlapping with the second metal layer ML2), and the equivalent distance between the first conductive layer CL1 and the second conductive layer CL2 (i.e., the thickness of the second insulating layer IL2 in the overlapping portion of the first conductive layer CL1 and the second conductive layer CL2).

[0126] Compared to the embodiments in Figures 7A and 7B, this embodiment is equivalent to using the light-transmitting first conductive layer CL1 and the second conductive layer CL2 to form additional parallel capacitors Ceq2 and Ceq3, so that even if the capacitance Ceq1 between the original first metal layer ML1 and the second metal layer ML2 is reduced due to the reduction in area, the overall capacitance value can still be maintained at the design value.

[0127] In this way, during the curing process using ultraviolet light irradiation, the transmittance of ultraviolet light through the scanning drive circuit can be effectively improved, thereby improving the curing effect of the sealant during the assembly of the display device and increasing the reliability of the display device.

[0128] In other embodiments, the display device 30 and its display panel D100 may also be configured as shown in Figures 9A and 9B, where Figure 9A is a top view of the display device 30 and Figure 9B is a side view of the display device 30. For ease of explanation, Figure 9A shows the internal components of the display device 30 unfolded in the xy plane, while Figure 9B shows the configuration of the internal components of the display device 30 within the housing.

[0129] Referring to Figures 9A and 9B, the display device 30 of this embodiment, in addition to the backlight module and display panel D200 described above, may also include a driver chip D220, a connection module D240, and a control circuit D250 for driving the display panel D200. The display panel D200 includes a substrate D211 and a pixel array D212. This embodiment has a configuration largely the same as that described in Figures 2A and 2B above; therefore, any repetitions can be found in the descriptions of the above embodiments and will not be repeated here.

[0130] The difference between this embodiment and the embodiments shown in Figures 2A and 2B is that the scan driving circuit D120 and data driving circuit D130 of the previous embodiments are integrated into a driver chip D220 in this embodiment. The driver chip D220 is configured below the non-display area SR of the display panel D200. To accommodate the connection configuration of the driver chip D220, the display panel D220 also includes fan-out transmission units WRG1 and WRG2 disposed on the left and right non-display areas SR (relative to the display area DR). Fan-out transmission unit WRG1 is used to electrically connect odd-numbered scan lines GL1, GL3, ..., GLm-1 to the driver chip D220, and fan-out transmission unit WRG2 is used to electrically connect even-numbered scan lines GL2, GL4, ..., GLm to the driver chip D220. Fan-out transmission units WRG1 and WRG2 include multiple fan-out traces FOL for connecting scan lines GL1-GLm.

[0131] On the other hand, in the embodiment of the display device 10 / 20 / 30 integrating touch function (which may be referred to as a touch display device), the touch display device 10 / 20 / 30 further includes a touch sensing chip (not shown) disposed on the substrate D111, and the upper side (On-cell) or the inside (In-cell) of the display panel D100 / D200 is integrated with a plurality of touch sensing units (not shown) formed by touch electrodes arranged in an array, wherein the touch sensing chip can be used to drive the touch sensing units to detect the capacitance change on the panel and realize the touch sensing function.

[0132] The following figures 10A to 12 illustrate different embodiments of the fan-out traces (FOL) of the display panel D200. Figures 10A and 10B illustrate a single-layer metal structure trace design embodiment, Figures 11A and 11B illustrate a double-layer metal interlace structure trace design embodiment, and Figure 12 illustrates a single-layer-double-layer interlace hybrid structure trace design embodiment.

[0133] Please refer to Figures 10A and 10B simultaneously. The cross-sectional structure of the display panel D200 at the cutoff line CC' is shown in Figure 10B. The circuit structure of the display panel D200 includes a first metal layer ML1, a first insulating layer IL1, a second metal layer ML2, and a second insulating layer IL2 sequentially formed on the substrate D211. The first metal layer ML1 is covered by the first insulating layer IL1. The second metal layer ML2 is disposed on the first insulating layer IL1, and the second insulating layer IL2 covers both the first insulating layer IL1 and the second metal layer ML2. In the display area DR, the first metal layer ML1 is used as scan lines GL1-GLm to transmit signals.

[0134] In the single-layer metal structure trace design of this embodiment, the fan-out traces FOL of the fan-out transmission units WRG1 and WRG2 are formed on the substrate D211 and are directly connected to the first metal layer ML1 of the corresponding scan lines GL1-GLm. In other words, the fan-out traces FOL are equivalent to the trace pattern of the first metal layer ML1 formed on the substrate D211, so as to electrically connect the scan lines GL1-GLm and the driver chip D220.

[0135] Since the fan-out trace FOL in this embodiment is implemented by forming a first metal layer ML1 directly on the substrate D211, which is covered by two insulating layers IL1 and IL2, the first metal layer ML1 can be completely covered, thereby reducing the corrosion resistance and moisture resistance of the first metal layer ML1 and extending the service life of the display panel D200.

[0136] However, since the fan-out traces (FOL) are made of a single layer of metal, the spacing between the traces must meet certain design specifications to avoid short circuits. Therefore, the single-layer structure of the fan-out traces in this embodiment inevitably makes it difficult to reduce the width of the non-display area (SR), which is detrimental to the narrow bezel design requirements of current small-sized display devices.

[0137] Please refer to Figures 11A and 11B simultaneously. The circuit structure of the display panel D200 in this embodiment is similar to that in the embodiment of Figure 10B. Each scan line GL1-GLm is also implemented using the first metal layer ML1. The main difference between this embodiment and the aforementioned embodiments of Figures 10A and 10B is that the fan-out traces FOL of the fan-out transmission units WRG1 and WRG2 are constructed with a structure of double-layer metal staggered arrangement.

[0138] Specifically, in this embodiment, the fan-out traces FOL of each fan-out transmission unit WRG1 and WRG2 are staggered and sequentially connected to the corresponding scan lines GL1-GLm using the first metal layer ML1 and the second metal layer ML2. Taking the trace design of the fan-out transmission unit WRG1 as an example, the fan-out trace FOL connecting scan line GL1 is formed using the first metal layer ML1, the fan-out trace FOL connecting scan line GL3 is formed using the second metal layer ML2, the fan-out trace FOL connecting scan line GL5 is formed using the first metal layer ML1, and so on. Similarly, in the fan-out transmission unit WRG2, the fan-out trace FOL connecting scan line GL2 is formed using the second metal layer ML2, the fan-out trace FOL connecting scan line GL4 is formed using the first metal layer ML1, and so on.

[0139] In other words, in each fan-out transmission section WRG1 and WRG2, adjacent traces of each fan-out trace FOL are located on different metal layers. Observing the fan-out connection configuration of the overall scan lines GL1-GLm, scan lines GL2 and GL3 are electrically connected to the driver chip D220 through the fan-out trace FOL formed in the second metal layer ML2, scan lines GL4 and GL5 are electrically connected to the driver chip D220 through the fan-out trace FOL formed in the first metal layer ML1, and so on.

[0140] More specifically, since the scan lines GL1-GLm transmit signals through the first metal layer ML1, in the configuration where the second metal layer ML2 serves as the fan-out trace FOL, a bridging structure BA is used to electrically connect the fan-out trace FOL and the corresponding scan line. The cross-sectional structure of the bridging structure BA at the cutoff line DD' is shown in Figure 11B. In the bridging structure BA, vias TH1 and TH2 are formed in the areas where the first insulating layer IL1 and the second insulating layer IL2 cover the first metal layer ML1 and the second metal layer ML2, respectively. Via TH1 exposes the second metal layer ML2, and via TH2 exposes the first metal layer ML1. The bridging structure BA also includes a conductive layer CL. The conductive layer CL covers the second insulating layer IL2 and the vias TH1 and TH2, allowing the first metal layer ML1 and the second metal layer ML2 to be electrically connected to each other through the conductive layer CL. In some embodiments, the conductive layer CL may be implemented, for example, as an ITO conductive film, but this application is not limited to this.

[0141] In the double-layer metal staggered structure routing design of this embodiment, since the fan-out routing FOL is arranged in an alternating configuration of different layers of first metal layer ML1 and second metal layer ML2, and there is a first insulating layer IL1 between the routing lines, the design specification of the routing spacing of the fan-out routing FOL can be smaller than that of the single-layer metal structure routing design, thus better meeting the narrow bezel design requirements of current small-size display devices.

[0142] However, in a configuration where the second metal layer ML2 serves as the fan-out trace (FOL), because it only has a single insulating layer IL2, if the edge angle of the second metal layer ML2 is too large, the second insulating layer IL2 covering the second metal layer ML2 may experience breakage or discontinuity at the edge of the second metal layer ML2 (also known as "undercut"), causing the second metal layer ML2 to be exposed. Consequently, the corrosion resistance and moisture resistance of the second metal layer ML2 are lower than those of the first metal layer ML1. This may result in poor image display on the display panel D200.

[0143] To solve the respective problems of the routing designs in FIGS. 10A to 11B above, an embodiment of the present application proposes a routing design of a single-layer and double-layer staggered hybrid structure, as shown in FIG. 12. In this embodiment, the scanning lines GL1-GLm can be divided into a first scanning line group GLo and a second scanning line group GLi, where the first scanning line group GLo includes the scanning lines GL1-GLa, and the second scanning line group GLi includes the scanning lines GLa+1-GLm, 2≤a<m. In other words, at least two scanning lines from top to bottom of the display panel D200 belong to the first scanning line group GLo, and the subsequent (m-a) scanning lines belong to the second scanning line group GLi.

[0144] In the fan-out transmission parts WRG1 and WRG2, the fan-out routing FOL connected to the first scanning line group GLo will adopt the routing design of the single-layer metal structure as shown in FIG. 10A, and the fan-out routing FOL connected to the second scanning line group GLi will adopt the routing design of the double-layer metal staggered arrangement structure as shown in FIG. 11A.

[0145] That is to say, the fan-out routing FOL electrically connected to the 1st to ath scanning lines GL1-GLa will all be formed on the substrate D211 with the first metal layer (such as ML1 in FIGS. 10B and 10B). On the other hand, the fan-out routing FOL electrically connected to the (a + 1)th to mth scanning lines GLa+1-GLm will be formed on the substrate D211 with the first metal layer and the second metal layer (such as ML2 in FIGS. 10B and 11B) staggered, so that each fan-out routing FOL in each of the fan-out transmission parts WRG1 and WRG2 is formed with a different metal layer from the adjacent fan-out routing FOL.

[0146] In some embodiments, a is, for example, 4. That is, the fan-out routing FOL of the 1st to 4th scanning lines GL1-GL4 of the display panel D200 is formed with the first metal layer, and the 5th to mth scanning lines GL5-GLm of the display panel D200 are formed with the first metal layer and the second metal layer staggered.

[0147] Specifically, due to the layout characteristics of the fan-out routing FOL of arranging from top to bottom and from outside to inside (that is, the routing connected to the scanning lines GL1-GLm closer to the upper side will be arranged closer to the edge of the substrate D211), and in the display panel D200, the risk of under cut is higher in the area closer to the edge of the substrate D211.

[0148] Therefore, this embodiment sets the gate fan-out trace FOL (i.e., the fan-out trace FOL connecting the first scan line group GLo) near the edge of the substrate D211 as a single-layer metal structure, and sets the fan-out trace near the display area DR (i.e., the fan-out trace FOL connecting the second scan line group GLi) as a double-layer metal staggered arrangement structure, thereby minimizing the risk of undercut while maintaining the minimum spacing of some fan-out traces, thus simultaneously taking into account the corrosion resistance and moisture resistance of the display panel D200 as well as the design requirements of a narrow bezel.

[0149] In some embodiments, the linewidth of the fan-out trace FOL electrically connected to the first scan line group GLo is greater than the linewidth of the fan-out trace FOL electrically connected to the second scan line group GLi.

[0150] The configuration of the pixel array in the aforementioned display panels D100 / D200 is further illustrated below with reference to Figures 13 to 18B. For ease of explanation, the following description will focus on the display panel D100 and its components, but this application is not limited thereto.

[0151] Figure 13 is a schematic diagram of the equivalent circuit of the pixel array according to an embodiment of this application. Referring to Figure 13, the pixel array D112 includes a plurality of pixel units Pu arranged in an array. The first column of pixel units Pu is electrically connected to the first scan line GL1, the second column of pixel units Pu is electrically connected to the second scan line GL2, the first row of pixel units Pu is electrically connected to the first data line DL1, and the second row of pixel units Pu is electrically connected to the second data line DL2. The connection relationship of other pixel units can be deduced similarly.

[0152] From the perspective of the equivalent circuit, taking the pixel unit Pu in the first row of the first column as an example, the pixel unit Pu includes a thin-film transistor M and capacitors Cp1, Cp2, and Cp3. Capacitor Cp1 is composed of a common electrode COM and a data line DL1, and can be considered as electrically connected between the data line DL1 and the common voltage VCOM. Capacitor Cp2 is composed of a common electrode COM and a scan line GL1, and can be considered as electrically connected between the scan line GL1 and the common voltage VCOM. Capacitor Cp3 is composed of a common electrode COM and the pixel electrode Ep of the thin-film transistor M, and can be considered as electrically connected between the pixel electrode Ep and the common voltage VCOM, and is connected in parallel with the liquid crystal cell LC.

[0153] Figures 14A and 14B are schematic diagrams illustrating the structural configuration of pixel arrays according to some embodiments of this application. Figures 14A and 14B illustrate a pixel structure with dual gates as an example. Figure 14A is a top view of pixel array D112, and Figure 14B is a cross-sectional view of pixel array D112. Referring simultaneously to Figures 14A and 14B, pixel array D112 includes thin-film transistors M11, M12, M21, and M22. The control terminals of thin-film transistors M11 and M12 are electrically connected to scan line GL1, and the control terminals of thin-film transistors M21 and M22 are electrically connected to scan line GL2. The first terminals of thin-film transistors M11 and M21 are electrically connected to data line DL1, and the first terminals of thin-film transistors M12 and M22 are electrically connected to data line DL2. The second terminals of thin-film transistors M11, M12, M21, and M22 are electrically connected to the corresponding pixel electrodes EP11, EP12, EP21, and EP22, respectively. In this embodiment, the control terminal of the thin-film transistors M11-M22 can be, for example, the gate, the first terminal of the thin-film transistors M11-M22 can be, for example, one of the source and the drain, and the second terminal of the thin-film transistors M11-M22 can be, for example, the other of the source and the drain, but this application is not limited thereto.

[0154] Taking the pixel unit Pu corresponding to the thin-film transistor M11 as an example, from a top view, the portion where the common electrode COM overlaps with the pixel electrode EP11 formed by the panel-shaped metal layer MP1 forms part of the pixel storage capacitance of the pixel unit Pu (i.e., capacitance Cp3 in the equivalent circuit), wherein the pixel electrode EP11 is disposed in the region overlapping with the gate structure of the common electrode COM. On the other hand, the pixel array D112 of this embodiment also includes a black matrix BMX, wherein the shape of the black matrix BMX is designed to roughly correspond to the shape of the common electrode COM, and is stacked on one side of the common electrode COM, but roughly exposes the region of the gate structure of the common electrode COM.

[0155] From the cross-sectional structure at the cut-off line EE', in the pixel array D112, a first insulating layer IL1 is formed on the substrate D111. Metal layers MP1 and MP2 are formed alternately on the first insulating layer IL1 and are covered by a second insulating layer IL2. A common electrode COM of a gate structure is formed on the second insulating layer IL2, wherein the width of the first portion of the common electrode COMa covering the metal layer MP1 is smaller than the width of the second portion of the common electrode COMb covering the interval between the metal layers MP1 and MP2. In other words, the orthographic projection regions of the first portion of the common electrode COMa and the metal layer MP1 at least partially overlap, and the orthographic projection regions of the second portion of the common electrode COMb and the metal layer MP1 substantially do not overlap. In this embodiment, the metal layer MP1 constitutes the pixel electrode EP11 corresponding to the thin-film transistor M11. In terms of the configuration relative to the black matrix, the orthographic projection areas of the common electrode COM and the black matrix BMX will roughly overlap. The orthographic projection areas of the black matrix BMX and the first part of the grid structure, the common electrode COMa, will roughly not overlap. The orthographic projection area of ​​the black matrix BMX located in the corresponding area of ​​the second part of the common electrode COMb will overlap with the orthographic projection area of ​​the second part of the common electrode COMb.

[0156] The liquid crystal layer (LCL) can be formed between the common electrode (COM) and the upper substrate (D111') by injecting liquid crystal material. The black matrix (BMX) is disposed on the side of the substrate (D111') facing the substrate (D111) and is located above the second part of the common electrode (COMb). The stacked structure on the left and right sides of the black matrix (BMX) can be regarded as two adjacent pixel units (Pu).

[0157] Specifically, the size of the pixel storage capacitor is mainly determined by the overlap area between the metal layer MP1 and the common electrode COM, as well as the thickness of the insulating layer IL2 between them. A larger overlap area and a thinner insulating layer IL2 allow for a larger pixel storage capacitor value. A larger pixel storage capacitor can effectively maintain display quality and reduce problems such as flicker and crosstalk in the display panel.

[0158] However, in typical pixel array designs, the thickness of the insulating layer IL2 is limited, while increasing the area of ​​the metal layer MP1 would reduce the aperture ratio and light transmittance of the display panel. In other words, it is difficult to simultaneously increase the pixel storage capacitance and maintain the aperture ratio / light transmittance under current designs.

[0159] To address the aforementioned problems, embodiments of this application propose a pixel array structural configuration as shown in Figures 15A to 16B, wherein Figures 15A and 15B are top and cross-sectional schematic diagrams of the pixel array structural configuration according to one embodiment of this application, and Figures 16A and 16B are top and cross-sectional schematic diagrams of the pixel array structural configuration according to another embodiment of this application.

[0160] Referring simultaneously to Figures 15A and 15B, the pixel array D112 of this embodiment includes thin-film transistors M11, M12, M21, and M22. Similar to Figure 14B, the pixel array D112, viewed from the stacked structure of the pixel units Pu corresponding to the thin-film transistor M11, includes substrates D111 and D111', a first insulating layer IL1, a metal layer MP1, a second insulating layer IL2, a liquid crystal layer LCL, and a black matrix BMX. The configuration of these components can be referred to the descriptions in Figures 14A and 14B, and will not be repeated here.

[0161] The main difference from Figures 14A and 14B is that the pixel array D112 in this embodiment further includes an extended metal layer MP1e. The extended metal layer MP1e is electrically connected to the drain of the thin-film transistor M11 and electrically connected to the metal layer MP1. The extended metal layer MP1e extends from the metal layer MP1 to the spacing region GR between the metal layers MP1 and MP2, and is at least partially formed in the orthographic projection region of the black matrix BMX (or, as may be referred to, formed in the orthographic projection region of the second common electrode COMb).

[0162] With the aforementioned configuration of the extended metal layer MP1e, the area of ​​the pixel electrode EP11 of the thin-film transistor M11 can be equivalent to the sum of the projected areas of the metal layer MP1e and the extended metal layer MP1e, thereby effectively increasing the pixel storage capacitance of the pixel unit Pu. Furthermore, since the extended metal layer MP1e is roughly located within the shading / projected area of ​​the black matrix BMX, the increased shading area does not reduce the aperture ratio / transmittance. Thus, the effects of increasing the pixel storage capacitance and maintaining the aperture ratio / transmittance are achieved simultaneously.

[0163] More specifically, in this embodiment, viewed from the top view of FIG15A, the first portion of the extended metal layer MP1e extends horizontally from the drain of the thin-film transistor M11 to the spacer region GR located between metal layers MP1 and MP2, and the second portion of the extended metal layer MP1e extends along the orthographic projection region of the second common electrode COMb, approximately parallel to the gate structure of the common electrode COM. In other words, the first and second portions of the extended metal layer MP1e form a "7" shaped structure in the top view.

[0164] In this embodiment, the extended metal layer MP1e may be formed on the same layer as the data lines DL1 and DL2, and may be made of an opaque metal material, but this application is not limited to this. When using an extended metal layer MP1e on the same layer as the data lines DL1 and DL2, the width of the extended metal layer MP1e is designed to be less than or equal to the width of the data lines DL1 and DL2 to prevent the extended metal layer MP1e from short-circuiting with adjacent pixel electrodes.

[0165] In some embodiments, the pixel units of the obliquely adjacent thin-film transistors M22 also have an extended metal layer MP1e similar to that shown in Figures 15A and 15B, and the extended metal layer of the thin-film transistor M22 and the extended metal layer MP1e of the thin-film transistor M11 are formed in the same second part of the common electrode COMb orthogonal projection area.

[0166] Please refer to Figures 16A and 16B. The structural configuration and function of this embodiment are largely the same as those of Figures 15A and 15B, so similar parts will not be repeated. The main difference between this embodiment and the aforementioned Figures 15A and 15B is that the extended metal layer MP1e in the embodiments of Figures 15A and 15B is implemented with metal in the same layer as the data lines DL1 and DL2, and is formed by extending from the drain of the thin-film transistor M11. Therefore, the second part of the extended metal layer MP1e will extend from the top to the bottom of the pixel array, and is closer to the scan line GL1 connecting the thin-film transistor M11.

[0167] In contrast, in Figures 16A and 16B, the extended metal layer MP1e is formed in the spacing region GR by extending from the metal layer MP1. That is, the extended metal layer MP1e is configured on the same layer as the metal layer MP1 and extends from the bottom to the top of the pixel array. In other words, in this embodiment, the extended metal layer MP1e is closer to the next scan line GL2 connected to the thin-film transistor M11.

[0168] In some embodiments, the pixel units of the obliquely adjacent thin-film transistors M22 also have an extended metal layer MP1e similar to that shown in Figures 16A and 16B, and the extended metal layer of the thin-film transistor M22 and the extended metal layer MP1e of the thin-film transistor M11 are formed in the same second part of the orthogonal projection area of ​​the common electrode COMb.

[0169] Figures 17A and 17B are schematic diagrams of the structural configuration of pixel arrays according to some embodiments of this application. Figures 17A and 17B illustrate a pixel structure with three gates as an example. Figure 17A is a top view of pixel array D112, and Figure 17B is a cross-sectional view of pixel array D112. Referring simultaneously to Figures 17A and 17B, pixel array D112 includes thin-film transistors M11, M12, M21, M22, M31, and M32. The control terminals of thin-film transistors M11 and M12 are electrically connected to scan line GL1, the control terminals of thin-film transistors M21 and M22 are electrically connected to scan line GL2, and the control terminals of thin-film transistors M31 and M32 are electrically connected to scan line GL3. The first terminals of thin-film transistors M11, M21, and M31 are electrically connected to data line DL1, and the first terminals of thin-film transistors M12, M22, and M32 are electrically connected to data line DL2. The second terminals of thin-film transistors M11, M12, M21, M22, M31, and M32 are electrically connected to the corresponding pixel electrodes EP11, EP12, EP21, EP22, EP31, and EP32, respectively. In this embodiment, the control terminal of thin-film transistors M11-M32 can be, for example, a gate electrode; the first terminal of thin-film transistors M11-M32 can be, for example, one of the source and drain electrodes; and the second terminal of thin-film transistors M11-M32 can be, for example, the other of the source and drain electrodes, but this application is not limited thereto.

[0170] Furthermore, in some embodiments of the tri-gate pixel structure, the scan line segment connecting two adjacent rows of thin-film transistors can be divided into two interconnected segments, wherein the extension directions of the two segments are not parallel to each other. Taking scan line GL2 as an example, the scan line segment connecting thin-film transistors M21 and M22 can be divided into a first segment Ls1 closer to one side thin-film transistor M21 and a second segment Ls2 closer to the other side thin-film transistor M22, wherein the extension directions of the first segment Ls1 and the second segment Ls2 are not parallel to each other. Other scan lines GL1 and GL3 can also be configured in a similar manner, and will not be repeated here.

[0171] Taking the pixel unit Pu corresponding to the thin-film transistor M21 as an example, from a top view, the portion where the common electrode COM overlaps with the pixel electrode EP21 formed by the panel-shaped metal layer MP1 forms part of the pixel storage capacitance of the pixel unit Pu (i.e., capacitance Cp3 in the equivalent circuit). The pixel electrode EP21 is disposed in the region overlapping with the gate structure of the common electrode COM (i.e., the first part of the common electrode COMa). On the other hand, the pixel array D112 of this embodiment also includes a black matrix BMX, wherein the shape of the black matrix BMX is designed to roughly correspond to the shape of the common electrode COM, and is stacked on one side of the common electrode COM, but roughly exposes the region of the gate structure of the common electrode COM.

[0172] From the cross-sectional structure at the cut-off line EE', in the pixel array D112, scan line GL2 is disposed on substrate D111, and a first insulating layer IL1 is formed on substrate D111 and covers scan line GL2. Metal layers MP1 and MP2 are formed alternately on the first insulating layer IL1. In some embodiments, metal layers MP1 and MP2 and the first insulating layer IL1 are coplanar. A second insulating layer IL2 is formed on metal layers MP1 and MP2 and the first insulating layer IL1, and a common electrode COM is formed on the second insulating layer IL2, wherein the width of the first portion of the common electrode COMa located on metal layers MP1 and MP2 is smaller than the width of the second portion of the common electrode COMb located at the interval between metal layers MP1 and MP2.

[0173] In other words, the projected regions of the first common electrode COMa and the metal layer MP1 at least partially overlap, and the projected regions of the second common electrode COMb and the metal layers MP1 / MP2 do not substantially overlap. In this embodiment, the metal layer MP1 constitutes the pixel electrode EP21 corresponding to the thin-film transistor M21. With respect to the black matrix BMX configuration, the projected regions of the common electrode COM and the black matrix BMX substantially overlap, wherein the projected regions of the black matrix BMX and the first common electrode COMa of the gate structure substantially do not overlap, and the projected regions of the black matrix BMX partially located in the corresponding regions of the second common electrode COMb partially overlap with the projected regions of the second common electrode COMb.

[0174] The liquid crystal layer (LCL) can be formed between the common electrode (COM) and the upper substrate (D111') by injecting liquid crystal material. The black matrix (BMX) is disposed on the side of the substrate (D111') facing the substrate (D111) and is located above the second part of the common electrode (COMb). The stacked structure on the left and right sides of the black matrix (BMX) can be regarded as two adjacent pixel units (Pu).

[0175] Specifically, taking the pixel unit Pu corresponding to transistor M21 as an example, the size of the pixel storage capacitor is mainly determined by the overlap area between the metal layer MP1 and the common electrode COM, as well as the thickness of the insulating layer IL2 between them. The larger the overlap area and the thinner the insulating layer IL2, the larger the capacitance value of the pixel storage capacitor can be.

[0176] However, similar to the problems described in Figures 14A and 14B, the thickness of the insulating layer IL2 is also limited in the design of a typical tri-gate pixel array. Increasing the area of ​​the metal layer MP1 would reduce the aperture ratio and transmittance of the display panel. In other words, it is difficult to simultaneously increase the pixel storage capacitance and maintain the aperture ratio / transmittance under the current design. Insufficient pixel storage capacitance can lead to unstable pixel voltage.

[0177] In addition, in the double-layer staggered fan-out trace design, when the transistor M21 changes from on to off, the charge on the pixel electrode EP21 no longer flows to the data line, thus entering a charge conservation state, which causes capacitive coupling effect between the overlapping scan lines, resulting in an increase in coupling and a relative increase in leakage current.

[0178] To address the aforementioned problems, embodiments of this application propose a pixel array structural configuration as shown in Figures 18A to 18C, wherein Figures 18A and 18B are top views of the pixel array structural configurations of different embodiments of this application, and Figure 18C is a cross-sectional view of the pixel array structural configuration according to the embodiment of Figure 18A or Figure 18B.

[0179] Please refer to Figures 18A and 18C simultaneously. In this embodiment, the pixel array D112 includes thin-film transistors M11, M12, M21, M22, M31, and M32. Looking at the stacked structure of the pixel units Pu corresponding to thin-film transistors M21 and M32, similar to Figure 17B, the pixel array D112 includes substrates D111 and D111', a first insulating layer IL1, a metal layer MP1, a second insulating layer IL2, a liquid crystal layer LCL, and a black matrix BMX. The configuration of these components can be referred to the descriptions in Figures 17A and 17B above, and will not be repeated here.

[0180] The main difference from Figures 17A and 17B is that in this embodiment, the pixel electrodes EP21 / EP32 extend to the area on the scan lines GL1 / GL2 of the preceding pixel unit. For example, the metal layer MP1, which is the pixel electrode EP21, extends to the area on the scan line GL1, and the metal layer MP2, which is the pixel electrode EP32, extends to the area on the scan line GL2. In this embodiment, the coverage area of ​​the pixel electrodes EP21 / EP32 on the first line segment Ls1 is approximately the same as the coverage area of ​​the pixel electrodes EP21 / EP32 on the second line segment Ls2. In other words, in this embodiment, the pixel electrodes EP21 / EP32 simultaneously cover the first line segment Ls1 and the second line segment Ls2 of the corresponding scan lines GL1 / GL2 (also referred to as a "full coverage configuration"). From another perspective, the full coverage configuration means that the metal layer MP1 / MP2, which serves as the pixel electrode EP21 / EP32, at least partially overlaps with the orthographic projection areas of the first line segment Ls1 and the second line segment Ls2 of the corresponding scan line GL1 / GL2, wherein the overlap area of ​​the metal layer MP1 / MP2 and the orthographic projection area of ​​the first line segment Ls1 is approximately the same as the overlap area of ​​the orthographic projection areas of the metal layer MP1 / MP2 and the second line segment Ls2.

[0181] More specifically, as shown in Figure 18C, from the cross-sectional structure at the cut-off line EE', the metal layer MP2 extends to form on the first insulating layer IL1 covering the scan line GL2. The metal layer MP2 can be divided into a first portion MP2a and a second portion MP2b. The first portion MP2a is located below the first common electrode COMa and does not overlap with the scan line GL2. The second region MP2b of the metal layer MP2 is at least partially located above the scan line GL2 and below the second common electrode COMb. In other words, in this embodiment, the orthographic projection regions of the first portion MP2a of the metal layer MP2 and the first common electrode COMa at least partially overlap. The orthographic projection regions of the second portion MP2b of the metal layer MP2, the second common electrode COMb, and the scan line GL2 at least partially overlap.

[0182] With the above-described configuration of the metal layer MP2, the pixel storage capacitance of the pixel electrode EP32 corresponding to the thin-film transistor M11 can be considered as a combination of the capacitance formed by the first part MP2a and the first common electrode COMa of the metal layer MP2, plus the capacitance formed by the second part MP2b and the second common electrode COMa of the metal layer MP2. In other words, the area of ​​the pixel electrode EP32 can be considered as the sum of the projected areas of the first part MP2a and the second part MP2b of the metal layer MP2. Compared to the pixel structures in Figures 17A and 17B, this embodiment effectively increases the pixel storage capacitance of the pixel unit Pu by increasing the area of ​​the pixel electrode EP32.

[0183] Experiments have verified that, compared to traditional pixel structures, the full-coverage pixel structure in Figure 18A, without process offset, can increase the capacitance of the pixel capacitor (i.e., capacitor Cp3 in Figure 13) by approximately 13% and the capacitance of the scan line capacitor (i.e., capacitor Cp2 in Figure 13) by approximately 8.2%. Furthermore, the overlap between the second part MP2b of the metal layer MP2 and the previous scan line GL2 effectively increases the scan line capacitance Cp2. Since the coupling between the upper and lower traces in a double-layer staggered fan-out trace design is generally inversely proportional to the capacitance of the scan line capacitor Cp2, increasing the scan line capacitance Cp2 in this embodiment reduces trace coupling, thereby lowering the gate-source voltage of the transistor M32. As shown in Figure 19, compared with the voltage and current characteristic curves CV1 of the pixel array configuration in Figures 17A and 17B, the voltage and current characteristic curve CV2 of this embodiment shows a significant leftward shift, which effectively reduces the gate-source voltage VGS and leakage current IDS.

[0184] Please refer to Figures 18B and 18C simultaneously. The pixel structure of the embodiment in Figure 18B is largely the same as that of the embodiment in Figure 18A. Therefore, the relevant or similar parts can be referred to the description of the above embodiments, and will not be repeated here. The main difference between this embodiment and the aforementioned embodiment in Figure 18A is that the pixel electrodes EP21 / EP32 in this embodiment only cover the first segment Ls1 / second segment Ls2 of the corresponding scan lines GL1 / GL2 on one side (also referred to as "single-side coverage configuration").

[0185] Taking the configuration illustrated in Figure 18B as an example, pixel electrode EP21 covers most of the first line segment Ls1 and a portion of the second line segment Ls2 of scan line GL1, and pixel electrode EP32 covers most of the first line segment Ls1 and a portion of the second line segment Ls2 of scan line GL2. That is, in this embodiment, the coverage area of ​​pixel electrodes EP21 / EP32 on the first line segment Ls1 is greater than the coverage area of ​​pixel electrodes EP21 / 32 on the second line segment Ls2 (i.e., left-side single-sided coverage configuration), but this application is not limited to this. In other embodiments, the pixel structure may also be designed such that the coverage area on the first line segment Ls1 is smaller than the coverage area of ​​pixel electrodes EP21 / 32 on the second line segment Ls2 (i.e., right-side single-sided coverage configuration).

[0186] In other words, the coverage area of ​​the pixel electrode EP21 / EP32 on one of the first line segment Ls1 and the second line segment Ls2 on the corresponding scan line GL1 / GL2 in this embodiment is greater than the coverage area of ​​the pixel electrode EP21 / EP32 on the other of the first line segment Ls1 and the second line segment Ls2. From another perspective, a single-sided coverage configuration means that the overlap area of ​​the metal layer MP1 / MP2, which is the pixel electrode EP21 / EP32, with the orthographic projection area of ​​one of the first line segment Ls1 and the second line segment Ls2 on the corresponding scan line GL1 / GL2 is greater than the overlap area of ​​the metal layer MP1 / MP2 with the other of the first line segment Ls1 and the second line segment Ls2 on the corresponding scan line GL1 / GL2.

[0187] Looking at the section EE' passing through the first line segment Ls1, the cross-sectional structures of Figures 18A and 18B will both be as shown in Figure 18C. If we look at the cross-sectional structure passing through the second line segment Ls2, the cross-sectional structure of Figure 18A will be as shown in Figure 18C, but the cross-sectional structure of Figure 18B will be as shown in Figure 17B.

[0188] Experiments have shown that, compared to traditional pixel structures, the single-sided coverage configuration of the pixel structure in Figure 18B can increase the capacitance value of the pixel capacitor (i.e., capacitor Cp3 in Figure 13) by about 10.4% and the capacitance value of the scan line capacitor (i.e., capacitor Cp2 in Figure 13) by about 15% without any process offset.

[0189] More specifically, during the manufacturing process of the pixel array D112, the process offset of pixel electrodes EP21 / EP32 is generally between 1.35μm (3 sigma) and 2.7μm (6 sigma). Therefore, to cover the scan lines GL1 / GL2 with pixel electrodes EP21 / EP32, the overlap width between pixel electrodes EP21 / EP32 and scan lines GL1 / GL2 needs to be at least between 1.35μm and 2.7μm to avoid failing to achieve the expected coverage structure due to process offset. Furthermore, in the pixel structures shown in Figures 18A and 18B, the process offset of pixel electrodes EP21 / EP32 also affects the estimated capacitance values ​​of capacitors Cp2 and Cp3. If this process offset causes excessive changes in capacitance values, it may affect the design considerations for various performance aspects of the display panel.

[0190] The embodiment in Figure 18B, compared to the embodiment in Figure 18A, adopts a single-sided coverage configuration design, which can effectively reduce the impact of the process offset of pixel electrodes EP21 / EP32 on the capacitance value. Experimental verification shows that...

[0191] With the pixel electrodes EP21 / EP32 offset vertically, the pixel capacitor offset of the pixel structure using the single-sided coverage configuration shown in Figure 18B is 5.3% based on an offset of 3 sigma, which is about half the pixel capacitor offset of the full-coverage configuration shown in Figure 18A (10.9%). On the other hand, the scan line capacitor offset of the pixel structure using the single-sided coverage configuration shown in Figure 18B is 10.5%, which is about half the pixel capacitor offset of the full-coverage configuration shown in Figure 18A (20.2%).

[0192] As can be seen from the above, compared with the full coverage configuration, the single-sided coverage configuration can not only effectively increase the capacitance values ​​of the pixel capacitor and the scan line capacitor, but also further reduce the impact of process offset on the pixel capacitor and the scan line capacitor. This can make the common electrode voltage uniformity in the panel better and significantly optimize the panel's flicker problem.

[0193] The following figures 20 to 24B further illustrate some technical features of the above-mentioned display devices 10 / 20 / 30 and display panels D100 / D200 during the assembly and manufacturing process. For ease of explanation, the following description will focus on display device 10 and display panel D100, but this application is not limited thereto.

[0194] Figure 20 is a schematic diagram of the configuration of the array substrate according to an embodiment of this application. Referring to Figure 20, the array substrate 1 of this application includes a glass substrate SUB (or a mother substrate SUB) and a plurality of display panels D100, wherein the area on the glass substrate SUB where the plurality of display panels D100 are formed can be divided into a plurality of array blocks ABLK. In some embodiments, in each array block ABLK, the edges of the display panels D100 are arranged adjacently, so that test circuit traces cannot be arranged between the display panels D100. Preferably, the plurality of display panels D100 are arranged on the array substrate 1 without gaps. In this embodiment, the common electrode on each display panel D100 overlaps with the scan lines, data lines, pixel electrodes and other metals in the display area to form corresponding capacitors. During the manufacturing process of the display panels D100, they are first formed on the array substrate 1, and then divided and assembled into independent display devices 20 as shown in Figures 2A and 2B or independent display devices 30 as shown in Figures 9A and 9B.

[0195] Taking the configuration of adjacent display panels D100a and D100b in Figure 21 as an example, Figure 21 is a schematic diagram of the configuration of adjacent display panels on the array substrate according to an embodiment of this application. The common electrode COM1 of display panel D100a overlaps with the scan line GL, data line DL, and pixel electrode Ep of thin-film transistor M in the display area. Similarly, display panel D100b has a similar configuration. From the perspective of the equivalent circuit, as shown in Figure 13, and again taking the pixel unit Pu on display panel D100a as an example, the pixel unit Pu can be equivalently regarded as having thin-film transistor M and capacitors Cp1, Cp2, and Cp3. The specific connection relationship can be referred to the description of the embodiment in Figure 13 above, and will not be repeated here. Therefore, in the display area of ​​each display panel D100a / D100b, the equivalent capacitance of each pixel unit Pu on display panel D100a / D100b is equal to the sum of the capacitance values ​​of capacitors Cp1, Cp2, and Cp3. Therefore, the total capacitance of the display area of ​​display panel D100a / D100b is equal to the sum of the capacitance values ​​of capacitors Cp1, Cp2 and Cp3 multiplied by the number of pixel units Pu in the display area.

[0196] In this embodiment, adjacent display panels D100a and D100b are electrically connected to each other via at least one line 3, where their common electrodes COM1 and COM2 are interconnected. In this embodiment, display panels D100a and D100b are illustrated as having their common electrodes COM1 and COM2 interconnected via two of the aforementioned lines 3, but this application is not limited to this. In some embodiments, display panels D100a and D100b may also use more of the aforementioned lines 3 to electrically connect their common electrodes COM1 and COM2.

[0197] Referring to Figures 20 and 21, in this embodiment, each display panel D100 in each array block ABLK of the array substrate 1 has an electrical connection configuration similar to the common electrode COM described above, such that the total capacitance Ctotal within the same array block ABLK is equal to the sum of the equivalent capacitances of all display panels D100, thereby forming an equivalent large capacitor among the display panels D100. In some embodiments, all adjacent display panels in the array substrate 1 are interconnected via at least one line 3, thereby increasing the overall equivalent capacitance of the array substrate 1. Normally, static electricity generated by friction or handling is absorbed by the common electrode COM. The large equivalent capacitance design described above further helps to absorb static electricity, achieving an optimized electrostatic discharge protection effect.

[0198] Figures 22A and 22B are schematic diagrams of the configuration of the display panel of this application on the array substrate. In this embodiment, the configuration of the display panel D100 is similar to that described in the previous embodiments, having a display area DR and a non-display area SR. Its specific structural configuration can be referred to the description of the above embodiments, and will not be repeated here. In Figure 22A, the display panels D100 are all arranged in the same configuration facing the same direction. That is, in the vertical direction, the foot area of ​​the display panel D100 (the lower side of the figure, i.e., the wider side of the non-display area SR, or the side used to configure the data driving circuit D130) is adjacent to the head area of ​​the adjacent display panel D100 (the upper side of the figure, i.e., the narrower side of the non-display area SR). In addition, the display panels D100 are interconnected with each other through a plurality of the lines 3. For example, in Figure 22A, the top left display panel D100 is connected to the adjacent display panel D100 below it by two lines 3, and the top left display panel D100 is connected to the adjacent display panel D100 to its right by three lines 3. In other words, the arrangement of the embodiment in Figure 22A can be described as a head-to-tail configuration.

[0199] Furthermore, in Figure 22B, the multiple display panels D100 in the upper row and the multiple display panels D100 in the lower row are arranged facing opposite directions. That is, the head area of ​​the upper row display panel D100 is adjacent to the head area of ​​the adjacent lower row display panel D100. In addition, the display panels D100 are interconnected with each other through a plurality of lines 3. For example, the upper left display panel D100 in Figure 22B is connected to the adjacent display panel D100 below it by two lines 3, and the upper left display panel D100 is connected to the adjacent display panel to its right by three lines 3. In other words, the arrangement of the embodiment in Figure 22B can be described as a head-to-head connection.

[0200] Experimental tests, as shown in the table below, revealed a 4.38% probability of electrostatic discharge (ESD) damage to the metal lines in the array substrate when there are no test circuit traces on the array substrate and the common electrodes of adjacent display panels are not connected. In contrast, the embodiments of this application, through the aforementioned structural configuration, reduce the probability of ESD damage to 0%. Are the common electrodes connected to each other? Array Block Input Department electrostatic damage rate Glass substrates without test circuit traces none 12 2213 4.38% have 6 1080 0% [Table 1]

[0201] In another embodiment of this application, FIG23A is a schematic diagram of an electrostatic discharge (ESD) protection structure configured within an array block of an array substrate according to an embodiment of this application. Referring to FIG23A, the array substrate 1 of this application, as described above, includes a glass substrate SUB and a plurality of display panels D100, wherein the glass substrate SUB can be divided into a plurality of array blocks ABLK, and the display panels D100 in each array block ABLK can be arranged, for example, edge-to-edge. In this embodiment, each array block ABLK has, for example, twelve display panels D100, but is not limited thereto; more or fewer may be configured, for example, four, six, eight, etc., and this application is not limited thereto.

[0202] Next, please refer to Figures 23A, 23B and 23C, where Figure 23B is a cross-sectional view of line FF' in Figure 23A, which is also a cross-sectional view of the electrostatic protection structure of the embodiment of this application, and Figure 23C is a partially enlarged schematic diagram of the electrostatic protection structure of Figure 23A.

[0203] Each of the array blocks ABLK has metal layers ML1 and ML2, insulating layers IL1 and IL2, and multiple conductive layers CL.

[0204] As shown in Figures 23A and 23B, in each array block ABLK, a metal layer ML1 is disposed on the glass substrate SUB in such a way that at least six of the plurality of display panels D100 are surrounded, to form a plurality of electrostatic discharge lines EDL1 on each array block ABLK. An insulating layer IL1 covers the metal layer ML1, leaving at least a portion of the metal layer ML1 exposed. A metal layer ML2 is disposed on the insulating layer IL1 in such a way that at least six of the plurality of display panels D100 are surrounded, to form a plurality of electrostatic discharge lines EDL2 on each array block ABLK corresponding to the plurality of electrostatic discharge lines EDL1. An insulating layer IL2 covers the metal layer ML2, leaving at least a portion of the metal layer ML2 exposed.

[0205] In the embodiment of Figure 23A, metal layer ML2 is outside metal layer ML1. More specifically, metal layer ML2 is closer to the edge of array block ABLK than metal layer ML1, but is not limited thereto. Although not shown in the figure, it can also be the other way around, that is, metal layer ML1 is outside metal layer ML2. Whether metal layer ML1 or metal layer ML2 is closer to the plurality of display panels D100, it can effectively conduct static electricity. The key point is that metal layers ML1 and ML2 are stacked. In the embodiment of Figure 23A, metal layer ML1 surrounds two display panels D100, and metal layer ML2 surrounds six of the display panels D100, but is not limited thereto, and can also surround two, four, eight or more of the display panels D100.

[0206] As shown by the dashed line between metal layers ML1 and ML2 in Figure 23A, this represents the conductive layer CL. The area enclosed by the dashed line in Figure 23A is the bridging structure BA (or bridging region BA). The conductive layer CL is formed within the bridging structure BA, and the bridging structure BA is located at least at the bend of metal layer ML1 (i.e., at the corner of array block ABLK). Furthermore, as shown by the dashed line in Figure 23B, at least a portion of the conductive layer CL is connected to metal layer ML1 through the portion exposed by insulating layer IL1, and at least another portion of the conductive layer CL is connected to metal layer ML2 through the portion exposed by insulating layer IL2. This allows the conductive layer CL to pass through insulating layers IL1 and IL2, electrically connecting metal layers ML1 and ML2. In other words, the conductive layer CL electrically connects metal layers ML1 and ML2 to each other.

[0207] By electrically connecting metal layers ML1 and ML2 through multiple conductive layers CL and multiple bridging structures BA, the corresponding multiple electrostatic discharge lines EDL1 and EDL2 can be electrically connected together. In this embodiment, although the diagram illustrates the bridging structure BA located at the bend of metal layer ML1, this application is not limited to this. The bridging structure BA can also be located at other positions besides the bend of metal layer ML1, as long as it allows metal layers ML1 and ML2 to be electrically connected to each other. Furthermore, it should be understood that the electrostatic discharge effect is better when the bridging structure BA is located at the bend of metal layer ML1.

[0208] With the above configuration, even with a small display panel D100 on the array substrate 1 without test circuit traces, electrostatic discharge (ESD) protection can still be achieved. Furthermore, because the metal layers ML1 and ML2 are a double-layer structure, the horizontal area generated by their arrangement on the array substrate 1 can be reduced, thereby increasing the number of display panels D100 that can be configured in each array block ABLK on the mother substrate SUB. Moreover, because the ESD protection structure includes a double-layer structure with metal layers ML1 and ML2, the overall impedance of the mother substrate SUB is lower / the equivalent area is larger, making it easier to achieve the effects of attracting and dissipating static electricity.

[0209] As shown in Figure 23C, in this embodiment, the spacing P1 (or pitch) between two adjacent electrostatic discharge lines EDL1 / EDL2 can be greater than 200 μm. More specifically, the pitch can be, for example, in top view, the distance P1 from the side of the metal layer ML1 electrically connected to the metal layer ML2 via the conductive layer CL to the side of the metal layer ML2 electrically connected to the metal layer ML1 away from the metal layer ML1 can be 200-300 μm (that is, the pitch of adjacent electrostatic discharge lines EDL1 / EDL2 can be between 200-300 μm). Furthermore, the spacing P2 between the parallel sides of the metal layer ML1 electrically connected via the conductive layer CL can be 150-300 μm.

[0210] Through the above embodiments of this application, combined with the dimensions of the aforementioned spacing P1 and spacing P2, the configuration space required for the electrostatic discharge protection structure of an array block ABLK is only 900-1500μm, saving a significant amount of space compared to conventional technologies. This allows for the configuration of more small-sized display panels D100.

[0211] Please refer to Figures 24A and 24B, where Figure 24B is a cross-sectional view along line GG' of Figure 24A, and is also a cross-sectional view of the electrostatic discharge protection structure of another embodiment of this application. As shown in Figures 24A and 24B, there are two metal layers ML2, respectively disposed on both sides of metal layer ML1, and located at different heights from metal layer ML1. Furthermore, there are also two metal layers ML1 in certain areas on the glass substrate SUB. When there are multiple metal layers ML1, multiple electrostatic discharge lines EDL1 are formed, and the insulating layer IL1 electrically isolates each electrostatic discharge line EDL1 in the non-bridging area. Similarly, when there are multiple metal layers ML2, multiple electrostatic discharge lines EDL2 are formed, and the insulating layer IL2 electrically isolates each electrostatic discharge line EDL2 in the non-bridging area. With this arrangement, it is not necessary to additionally provide more insulating layers, and the thickness of the array substrate 1 can also be reduced.

[0212] In another embodiment of this application, although not shown in the figures, each array block ABLK has multiple metal layers, multiple insulating layers, and multiple conductive layers. The multiple metal layers are sequentially stacked on the glass substrate SUB, surrounding at least two of the multiple display panels D100. The multiple insulating layers separate the multiple metal layers and expose at least a portion of each metal layer. The multiple conductive layers electrically connect the multiple metal layers stacked on different layers through at least a multiple bridging structure of the multiple metal layers, passing through the multiple insulating layers.

[0213] Through the above embodiments of this application, electrostatic protection can be achieved by configuring a small-sized display panel D100 on the array substrate 1 without the need for test circuit traces.

[0214] Figures 25A and 25B are schematic diagrams illustrating the configuration of pixel array substrates according to different embodiments of this application. Referring first to Figure 25A, the pixel array substrate D110 of this embodiment is similar to the configuration of Figures 1A to 2B above, including a display area DR and a non-display area SR. The display area DR is the area on substrate D111 where the pixel array D112 is disposed, and the non-display area SR is the area on substrate D111 other than the display area DR. The non-display area SR can also be divided into a border area BA and a circuit fan-out area FA. The border area BA is the area for applying frame adhesive, and the circuit fan-out area FA is the area for configuring scan driving circuits (such as D120) and / or data driving circuits (such as D130).

[0215] In some embodiments, the non-display areas SR can be configured in an offset manner on the substrate D111, that is, the widths of the non-display areas SR on the two sides of the display area SR can be different. For example, as shown in FIG25A, the width of the non-display area SR on the lower side of the substrate D111 is greater than the width on the upper side, wherein the lower non-display area SR can serve as the circuit fan-out region FA of the data driving circuit, but this application is not limited to this. In addition, the non-display areas SR on the left and right sides of the display area DR can be symmetrically configured, that is, the non-display areas SR on both sides have the same width.

[0216] On the other hand, considering the relative configuration of the pixel array substrate D110, the bezel area BA is closer to the edge of the substrate D111 than the circuit fan-out area FA. In other words, the circuit fan-out area FA is closer to the display area DR than the bezel area BA.

[0217] In this embodiment, the pixel array substrate D110, in addition to including the substrate D111 and the pixel array D112, also includes an electrostatic discharge (ESD) protection structure D113. The ESD protection structure D113 is formed by a metal strip pattern on the substrate D111. The metal strip pattern surrounds the substrate D111 and is at least partially located within the bezel area BA, forming an open annular structure. In other words, when the frame adhesive is applied to the display panel, at least a portion of it is applied to the area where the ESD protection structure is located.

[0218] Taking Figure 25A as an example, the metal strip pattern of the electrostatic protection structure D113 surrounds the left, upper, and right sides of the substrate D111; the metal strip pattern is only provided on the two sides of the lower side of the substrate D111, while the middle area of ​​the lower side of the substrate D111 does not have a metal strip pattern. The middle area without a metal strip pattern is the opening of the annular structure. However, this application is not limited to this.

[0219] To ensure the effectiveness of electrostatic discharge, in some embodiments, the width of the metal strip pattern is greater than or equal to 40 micrometers. Furthermore, to prevent the electrostatic protection structure D113 from being damaged during display panel cutting, in some embodiments, the metal strip pattern may have a gap (e.g., 20 millimeters) between it and the edge of the substrate D111.

[0220] In the process of applying and bonding frame adhesive to a display panel using a pixel array substrate D110, when a UV light source shines from the back of the pixel array substrate D110 toward the display panel, the electrostatic discharge structure D113, which is made of opaque metal, blocks part of the UV light that assists in the curing of the frame adhesive, reducing the curing rate of the frame adhesive and resulting in poor display performance of the liquid crystal display panel.

[0221] Please refer to Figure 25B next. The pixel array substrate D110' of this embodiment is similar to the pixel array substrate D110 of the embodiment in Figure 25A above. The main difference between the two is that the design of the electrostatic protection structure D113' of this embodiment is different from the electrostatic protection structure D113 of the previous embodiment.

[0222] Specifically, the electrostatic protection structure D113' in this embodiment is also constructed by a metal strip pattern surrounding the substrate D111. The main difference between it and the electrostatic protection structure D113 is that the metal strip pattern of the electrostatic protection structure D113' in this embodiment has multiple light-transmitting parts TRP. The multiple light-transmitting parts TRP can be formed by transparent conductive material (e.g., ITO) and are arranged sequentially at intervals along the extension direction of the metal strip pattern, so that the electrostatic protection structure D113' forms a ring structure with holes formed by the light-transmitting parts TRP.

[0223] By designing the electrostatic protection structure D113', during the curing of the frame adhesive, UV light irradiating from the back of the substrate D111 can pass through the light-transmitting TRP portion to the frame adhesive on the front of the substrate D111, thereby improving the curing rate of the frame adhesive and thus enhancing the yield and reliability of panel assembly. Furthermore, because the light-transmitting TRP portion of the electrostatic protection structure D113' is formed of a transparent conductive material, it does not reduce the equivalent area of ​​the metal strip pattern. Therefore, the electrostatic dissipation capability of the electrostatic protection structure can be maintained, and the electrostatic dissipation capability is not diminished by the inclusion of the light-transmitting TRP portion.

[0224] The design of the electrostatic discharge protection structure D113' of this application embodiment will be further described below with reference to Figures 26A and 26B, wherein Figure 26A is a top view of the pixel array substrate D210 of this application embodiment, and Figure 26B is a partial cross-sectional view of the pixel array substrate D210 of this application embodiment.

[0225] Please refer to Figure 26A first. The configuration of the pixel array substrate D210 in this embodiment is similar to that of the pixel array substrate D110' in the previous embodiment. The pixel array substrate D210 includes a substrate D211 and an electrostatic discharge (ESD) protection structure D213. The area on the substrate D211 where the pixel array is disposed is the display area DR, and the area on the substrate D211 other than the display area DR is the non-display area SR. The non-display area SR can be divided into a border area BA, a scan circuit fan-out area GFA, and a data circuit fan-out area DFA. The border area BA is the area for applying frame adhesive, the scan circuit fan-out area GFA is the area for configuring the scan driving circuit (such as D120), and the data circuit fan-out area DFA is the area for configuring the data driving circuit (such as D130). The border area BA includes a first border area BA1 and a second border area BA2 located on opposite sides of the substrate D211, and a third border area BA3 located between the first border area BA1 and the second border area BA2.

[0226] In this embodiment, the electrostatic protection structure D213 includes a first metal strip pattern MSP1, a second metal strip pattern MSP2, and a third metal strip pattern MSP3, wherein the first metal strip pattern MSP1 is disposed in the first border area BA1, the second metal strip pattern MSP2 is disposed in the second border area BA2, and the third metal strip pattern MSP3 is disposed in the third border area BA3.

[0227] Specifically, the first metal strip pattern MSP1, the second metal strip pattern MSP2, and the third metal strip pattern MSP3 are electrically connected to each other to form a metal pattern surrounding the first to third border regions BA1-BA3. In this embodiment, the first metal strip pattern MSP1, the second metal strip pattern MSP2, and the third metal strip pattern MSP3 are formed continuously and integrally, but this application is not limited to this.

[0228] Please refer to Figures 26A and 26B simultaneously. In this embodiment, the electrostatic protection structure D213 is, for example, composed of a metal layer ML1, an insulating layer IL1, a transparent conductive layer TC, a metal layer ML2, and an insulating layer IL2 stacked in sequence to form the first to third metal strip patterns MSP1-MSP3.

[0229] Taking the cross-sectional structure of the first metal strip pattern MSP1 on the cutoff line HH' as an example, as shown in Figure 26B, the metal layer ML1 and the second metal layer ML2 of the electrostatic protection structure D213 will have a porous structure, so that the metal layers ML1 and ML2 form a discontinuous island structure in their cross-sectional structure, wherein at least some of the island structures will be arranged sequentially at approximately fixed intervals. The interval between adjacent island structures forms the aforementioned porous structure.

[0230] It should be noted that although the cross-section at line HH' shows that the island-like structures in metal layer ML1 / second metal layer ML2 are independent, in reality, these island-like structures are electrically connected to each other at different cross-sections, thus forming a perforated structure. This perforated structure corresponds to the shape of the light-transmitting portion TRP. Figure 26A illustrates this with a rectangular perforation as an example, but this application is not limited to this.

[0231] Metal layer ML1 is formed on the first side of substrate D211 (the direction shown in FIG26B is the upper side of the substrate), insulating layer IL1 is formed and covers metal layer ML1, and transparent conductive layer TC is formed on insulating layer IL1 and electrically connected to second metal layer ML2. The spacer region (i.e., hole structure) between each island structure in metal layer ML1 and second metal layer ML2, as well as insulating layer IL1, transparent conductive layer TC and insulating layer IL2 covering the spacer region, form the light-transmitting part TRP of electrostatic protection structure D213.

[0232] During the bezel bonding process of the display panel, the frame adhesive FP is applied to the insulating layer IL2 and irradiated with UV light from the second side of the substrate D211 (the direction shown in Figure 26B is the underside of the substrate) toward the first side. At this time, the UV light can irradiate the frame adhesive FP through the various light-transmitting parts TRP in the electrostatic protection structure D213, causing the frame adhesive FP to undergo a curing reaction in response to the UV light.

[0233] Compared to the traditional electrostatic discharge ring design, the electrostatic protection structure D213 in this embodiment has a higher transmittance of UV light because it reduces the large area of ​​metal obstruction. This allows UV light to reach the FP coating area through the light-transmitting part TRP, thus better assisting the curing of the frame adhesive.

[0234] In some embodiments, the metal layer ML1 and the second metal layer ML2 may have different widths in the cross-sectional direction of the metal strip pattern (e.g., in the direction of the slit line HH'). As shown in FIG26B, in this embodiment, the metal layer ML1 has a first width W1 in the direction of the slit line HH', and the second metal layer ML2 has a second width W2 in the direction of the slit line HH', wherein the first width W1 is greater than the second width W2.

[0235] In some embodiments, the ratio (W2 / W1) of the second width W2 to the first width W1 may be, for example, between 1 / 2 and 2 / 3, but this application is not limited thereto. In some embodiments, the first width W1 may be, for example, between 50mm and 70mm, preferably 60mm; the second width W2 may be, for example, between 30mm and 50mm, preferably 40mm, but this application is also not limited thereto.

[0236] More specifically, the portion of the electrostatic discharge (ESD) protection structure D213 in this embodiment that has two metal layers ML1 and ML2 can be referred to as the inner ring structure ER1, and the portion of the ESD protection structure D213 that has only a single metal layer ML1 can be referred to as the outer ring structure ER2. The first width W1 mentioned above is the sum of the width of the inner ring structure ER1 and the width of the outer ring structure ER2, and the second width W2 mentioned above is the width of the inner ring structure ER1.

[0237] Compared to traditional electrostatic discharge ring designs, the electrostatic protection structure D213, with its inner ring structure ER1 and outer ring structure ER2, has a wider cross-section, meaning the outer ring structure ER2 extends closer to the edge of the substrate D211. This increases the effective conductive area of ​​the electrostatic protection structure D213, further enhancing its electrostatic dissipation capability.

[0238] On the other hand, in some embodiments, within the regions of the first metal strip pattern MSP1 / the second metal strip pattern MSP2 / the third metal strip pattern MSP3, the metal layer ML1 and the second metal layer ML2 are electrically independent of each other, that is, they are isolated by the insulating layer IL1. The metal layer ML1, the second metal layer ML2 and the transparent conductive layer TC are only electrically connected together in the bridging region BR of the electrostatic protection structure D213.

[0239] In other words, the inner ring structure ER1 (mainly composed of metal layer ML1, transparent conductive layer TC, and second metal layer ML2) and the outer ring structure ER2 (mainly composed of metal layer ML1) of the electrostatic protection structure D213 are only electrically connected through the bridging area BR located below the substrate D211. As a result, even if the outer ring structure ER2 is damaged by the cutting wheel due to cutting errors during the cutting of the pixel array substrate D210, the electrostatic protection structure D213 will still retain the inner ring structure ER1 to maintain a certain electrostatic dissipation capability, thereby reducing the risk of the cutting wheel damaging the panel's electrostatic protection capability.

[0240] Figures 27A to 27C are schematic diagrams of a display panel configuration. Referring first to Figure 27A, in the display panel D300 of this embodiment, each pixel unit Pu can correspond to a light-emitting element LED. The light-emitting element LED can be, for example, a white light-emitting diode or a blue light-emitting diode, but this application is not limited thereto. The light-emitting element LED can be a sub-millimeter light-emitting diode (mini-LED), a micro light-emitting diode (micro-LED), or an organic light-emitting diode (OLED), but this application is not limited thereto. In other embodiments, the light-emitting element LED can also be of other sizes and / or types. Depending on the type of light-emitting element selected, the display panel D300 can be, for example, a ULED panel, a mini-LED panel, a micro-LED panel, or an OLED panel, but this application is not limited thereto.

[0241] In some embodiments, each pixel unit Pu may include multiple sub-pixels, such as a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B. The first sub-pixel R, the second sub-pixel G, and the third sub-pixel B are each controlled to emit light of different wavelengths. For example, the first sub-pixel R may include a light-emitting element with a red light wavelength range (e.g., 610nm-720nm), the second sub-pixel G may include a light-emitting element with a green light wavelength range (e.g., 520nm-610nm), and the third sub-pixel B may include a light-emitting element with a blue light wavelength range (e.g., 400nm-520nm). In some embodiments, the light-emitting elements of the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B may be red light-emitting diodes (or light-emitting diodes with emission wavelengths in the red light segment), green light-emitting diodes (or light-emitting diodes with emission wavelengths in the green light segment), and blue light-emitting diodes (or light-emitting diodes with emission wavelengths in the blue light segment), respectively. Similarly, the light-emitting elements of each sub-pixel R / G / B can be mini-LED or micro-LED, but this application is not limited thereto.

[0242] Please refer to Figure 27B, which is a schematic cross-sectional view of the display panel D100 along section II'. In this embodiment, the display panel D300 includes light-emitting elements LED1-LED3, a substrate D111, a metal layer ML3, a protective layer PL, a metal layer ML4, a sealing layer SL, a circuit layer WL, a bonding portion AD, and an isolation layer CDL. The metal layer ML3 includes first electrode regions 1121, 1122, and 1123 formed on the substrate D111, wherein each electrode region 1121-1123 is electrically connected to each other through the corresponding circuit layer WL. The light-emitting elements LED1-LED3 are respectively disposed on the first electrode regions 1121-1123 of the metal layer ML3, wherein each light-emitting element LED has two electrodes located on opposite sides of the light-emitting elements LED1-LED3. The electrodes (or lower electrodes) of each light-emitting element LED1-LED3 on the side (or lower side) closest to the metal layer ML1 are electrically connected to the corresponding first electrode regions 1121-1123 via the junction AD. A protective layer PL fills the spaces between the light-emitting elements LED1-LED3 and covers at least a portion of the surface of each light-emitting element LED1-LED3 to prevent unintended short circuits between them. The protective layer PL exposes at least the electrodes (or upper electrodes) on the other side (i.e., the side furthest from the metal layer ML3, or upper side) of the light-emitting elements LED1-LED3. A metal layer ML4 is disposed on the protective layer PL and electrically connected to the upper electrodes of the light-emitting elements LED1-LED3. The light-emitting elements LEDs can receive drive signals controlling their illumination through the metal layers ML3 and ML4. A sealing layer SL is formed and covers the metal layer ML4.

[0243] Specifically, in the embodiment of FIG27B, the light-emitting elements LED1-LED3 can be, for example, vertically packaged light-emitting diodes, wherein the electrodes of each light-emitting diode are disposed on opposite sides, so that the driving signal can be received through the metal layers ML3 and ML4 located on both sides of the light-emitting elements LED1-LED3.

[0244] In short, in the display panel 100 configuration of this embodiment, the first electrode regions 1121-1123 of the metal layer ML3 can be respectively regarded as the lower electrodes of the light-emitting elements LED1-LED3 (hereinafter referred to as lower electrodes 1121-1123), and the metal layer ML4 connected to each light-emitting element LED1-LED3 can be regarded as the upper electrode of the light-emitting elements LED1-LED3 (hereinafter referred to as upper electrode ML4). Therefore, the driver chip 140 can provide signals through the upper electrode ML2 and the corresponding lower electrodes 1121-1123 of the light-emitting elements LED1-LED3 to control the lighting state of the light-emitting elements LED1-LED3.

[0245] In the display panel D300 with vertically packaged light-emitting elements as shown in Figures 27A and 27B, to achieve an in-cell embedded touch design, the upper and lower electrodes of each pixel unit Pu need to be used as touch electrodes to sense capacitance changes during touch. In other words, the display panel D300 needs to share upper and lower electrodes to achieve display and touch functions respectively. To achieve electrode sharing, each driving cycle of the display panel D300 needs to be further divided into a display period and a touch sensing period, as shown in Figure 31.

[0246] In this embodiment, the display panel D300 enters the display period in response to the reset signal RST. During the display period, the driver chip 140 provides display scan signals GLs through the upper and lower electrodes to sequentially control the illumination state of the pixel units Pu, thereby realizing the display of the screen on the display panel 100. After the display period ends, the display panel 100 enters the touch sensing period in response to the control signal EM (which can also be regarded as the display blank period within the driving cycle). During the touch sensing period, each pixel unit Pu can be regarded as a touch sensing unit, used to receive the touch scan signal TX issued by the touch sensing chip (not shown) and to send back the sensing signal associated with the electrical changes of the display panel D300 to the touch sensing chip, thereby determining whether a touch action has occurred.

[0247] Under the aforementioned control method, the D300 display panel needs to periodically switch between display and touch sensing periods. This necessitates a trade-off between pixel charging time and touch sensing time, creating difficulties in drive timing design. Furthermore, increasing the D300 display panel's frame rate per second (FPS) inevitably leads to a decrease in touch sensing sensitivity due to the reduced display blanking time.

[0248] Secondly, in the manufacturing process of the touch display panel using vertically packaged light-emitting elements LED1-LED3, due to the differences in the actual size and setting of each light-emitting element LEDs, the position of the upper electrode of each light-emitting element LEDs will be high or low and not on the same plane, as shown in Figure 27C, where Figure 27C is a schematic diagram of the cross-sectional structure of the display panel D300 along the cut line JJ'.

[0249] Referring to Figure 27C, the light-emitting element LED1 on the left side of Figure 27C is configured in an ideal state. That is, when the light-emitting element LED1 is mounted on the substrate D111 via the bonding portion AD and connected to the first electrode region 1211 (or lower electrode wire), the height H1 of both the bonding portion AD and the light-emitting element LED1 (i.e., the shortest distance from the upper surface of the first electrode region 1121 to the top of the light-emitting element LED1) is approximately the same as the height of the protective layer PL. This allows the upper electrode of the light-emitting element LED1 to be exposed and positioned approximately flush with the upper edge of the protective layer PL (i.e., the upper electrode and the upper side of the protective layer PL are approximately on the same plane). Therefore, in an ideal state, the metal layer ML4 formed on the protective layer PL can be easily electrically connected to the exposed upper electrode, and the metal layer ML4 in the upper electrode region of the light-emitting element LED1 can still have a uniform linewidth to ensure electrical signal transmission.

[0250] The diagram illustrates configurations that often occur in real-world scenarios for light-emitting elements LED2 and LED3. Taking LED2 as an example, the height of LED2 and its corresponding junction AD are slightly less than the height of LED1 and its junction AD. This results in the overall height H2 of junction AD and LED2 being less than the height of the protective layer PL (approximately H1). Consequently, the protective layer PL covers the upper electrode of LED2 during its formation. Because the upper electrode of LED2 is covered by the protective layer PL, the metal layer ML4 cannot effectively connect electrically to the upper electrode of LED2, preventing LED2 from receiving a driving signal and illuminating. This configuration of LED2 can be considered an under-configuration state.

[0251] Regarding the configuration of LED3, its height is slightly greater than that of LED1. This results in the overall height H3 of the junction AD and LED3 being greater than the height of the protective layer PL (approximately H1). Consequently, the upper side of LED3 extends beyond the upper surface of the protective layer PL, causing the upper electrode of LED3 and the upper surface of the protective layer PL to be out of sync. Therefore, when forming the metal layer ML4 on the protective layer PL, because the upper electrode of LED3 is higher than the upper surface of the protective layer PL, the metal layer ML4 needs to be bent to extend to and electrically connect with the upper electrode of LED3. However, the linewidth at the bend (here, the width of the metal layer ML4 in the xz plane) is thin, making it prone to wire breakage and preventing normal signal transmission. The configuration of LED3 can be considered an over-proportioned configuration.

[0252] As described above, in a typical display panel structure, the thickness of the light-emitting elements LED1-LED3 may vary during actual manufacturing, and the corresponding bonding portions AD may also have different thicknesses / heights during the manufacturing process. These various process and material differences accumulate when the display panel 100 is packaged, resulting in different heights (e.g., H1-H3) of the upper electrodes of each light-emitting element LED1-LED3. This leads to the aforementioned connection defects during the formation / deposition of the metal layer ML4.

[0253] To address the aforementioned issues, this application proposes several novel display panel structural designs, as shown in Figures 28A to 30G. The designs in the embodiments of Figures 28A to 29B can form independent electrodes within the display panel for touch sensing, allowing the signal timing during display and touch sensing to be independent of each other, avoiding the need for trade-offs, thereby achieving cost savings and reducing the complexity of touch signal processing. The designs in the embodiments of Figures 30A to 30G can be used to achieve the effect of surface planarization of the display panel.

[0254] Referring first to Figures 28A and 28B, the display panel D400 of this embodiment includes a plurality of pixel units Pu arranged in an array, wherein each pixel unit Pu includes a display unit Du and a touch sensing unit Tc, and each display unit Du has a light-emitting element (such as LED1-LED3). Looking at the cross-sectional structure of line II' in Figure 28B, the display panel D400 includes light-emitting elements LED1-LED3, a substrate D111, a metal layer ML3, a protective layer PL, a metal layer ML4, a sealing layer SL, a circuit layer WL, a bonding portion AD, and an isolation layer CDL. The metal layer ML3 includes first electrode regions 2121, 2122, and 2123 and second electrode regions 2124 and 2125 formed on the substrate D111, wherein each of the first electrode regions 2121-2123 is electrically connected to each other through the corresponding circuit layer WL, and the second electrode regions 2124 and 2125 are electrically independent of the first electrode regions 2121-2123. From a structural configuration perspective, the first electrode regions 2121-2123 and the second electrode regions 2124 and 2125 are arranged alternately, meaning that a second electrode region 2124 or 2125 is provided between every two adjacent first electrode regions 2121-2123. For example, a second electrode region 2124 is provided between first electrode regions 2121 and 2122, and a second electrode region 2125 is provided between first electrode regions 2122 and 2123.

[0255] Light-emitting elements LED1-LED3 are respectively disposed on the first electrode regions 2121-2123 of the metal layer ML3, wherein each light-emitting element LED1-LED3 has two electrodes, which are located on opposite sides of the light-emitting element LED1-LED3. The electrode (or lower electrode or first electrode) of each light-emitting element LED1-LED3 on the side (or lower side) of the metal layer ML3 is electrically connected to the corresponding first electrode region 2121-2123.

[0256] The protective layer PL is filled between the light-emitting elements LED1-LED3 and covers at least a portion of the surface of each light-emitting element LED1-LED3 to prevent unintended short circuits between the light-emitting elements LED1-LED3. The protective layer PL exposes at least the electrode (or upper electrode or second electrode) on the other side of the light-emitting elements LED1-LED3 (i.e., the side away from the first metal layer 212, or the upper side).

[0257] The metal layer ML4 includes third electrode regions 2141, 2142, and 2143 and fourth electrode regions 2144 and 2145 formed on the protective layer PL, wherein the third electrode regions 2141-2143 are electrically connected to the upper electrodes of the corresponding light-emitting elements LED1-LED3, respectively. In other words, the first electrode region 2121 and the third electrode region 2141 can serve as the upper and lower electrodes of the light-emitting element LED1 to receive driving signals, the first electrode region 2122 and the third electrode region 2142 can serve as the upper and lower electrodes of the light-emitting element LED2 to receive driving signals, and the first electrode region 2123 and the third electrode region 2143 can serve as the upper and lower electrodes of the light-emitting element LED3 to receive driving signals.

[0258] In this embodiment, the protective layer PL forms vias THL in the regions corresponding to the second electrode regions 2124 and 2125, such that the fourth electrode regions 2144 and 2145 of the second metal layer 214, in addition to having a first portion formed on the upper side of the protective layer 213 at intervals from the third electrode regions 2141-2143, also have a second portion extending electrically connected to the second electrode regions 2124 and 2125 through the vias THL.

[0259] Specifically, taking the corresponding configuration of the light-emitting element LED1 as an example, the substrate D111 portion on which the light-emitting element LED1 is disposed, and the first electrode region 2121 and the third electrode region 2141 electrically connected to the light-emitting element LED1 constitute a display unit Du. The second electrode region 2124 and the fourth electrode region 2144 constitute a touch sensing unit Tc adjacent to the display unit Du on the truncated line II'. The corresponding structural configuration of the display unit Du and the touch sensing unit Tc is formed in each pixel unit Pu.

[0260] On the other hand, from the top view of Figure 28A, this embodiment illustrates a 12-column pixel unit Pu (this application is not limited to this), where each touch sensing unit Tc is electrically connected to the touch sensing chip through the corresponding touch scan lines TX1-TXn. In some embodiments, adjacent touch scan lines TX1-TXn have different connection configurations, and each x touch scan lines TX1-TXn can have a repeated connection configuration, where x is a natural number. For example, touch scan line TX1 is electrically connected to 8 touch sensing units Tc in columns 9 to 12 of the right side of the display panel D400; touch scan line TX2 is electrically connected to 12 touch sensing units Tc in columns 5 to 8 of the right side of the display panel D400 and 4 touch sensing units Tc in columns 9 to 12 of the right side of the third row (i.e., 16 other touch sensing units Tc in columns 5 to 12 of the right side of the third row of the display panel D400 besides the aforementioned 8 touch sensing units Tc). The touch sensing unit Tc and the touch scan line TX3 are electrically connected to 16 touch sensing units Tc in columns 1 to 4 of the 4th row on the right side of the display panel D400, and 8 touch sensing units Tc in columns 5 to 12 of the 4th row on the right side (that is, the other 24 touch sensing units Tc in the 4th row on the right side, excluding the 8 touch sensing units Tc connected to touch scan line TX1 and the 16 touch sensing units Tc connected to touch scan line TX2). The arrangement of other areas can be deduced similarly, and will not be repeated here.

[0261] More specifically, the cross-sectional structure of the display panel D400 in this embodiment on the cut line II' is roughly the same as that in the embodiments of FIG27A and FIG27B. The main difference between this embodiment and the previous embodiments is that in this embodiment, a second electrode region 2124 and 2125, which are electrically independent of the lower electrode of the light-emitting elements LED1-LED3, are added to the first metal layer 212. In addition, compared with the metal layer ML4 in the previous embodiment, a fourth electrode region 2144 and 2145, which are electrically independent of the electrode on the light-emitting elements LED1-LED3, are cut out on the metal layer ML4 in this embodiment. The second electrode region 2124 and the fourth electrode region 2144, which are electrically connected to each other, will form a touch electrode in a touch sensing unit Tc. The second electrode region 2125 and the fourth electrode region 2145, which are electrically connected to each other, will form a touch electrode in another touch sensing unit Tc. In other words, this embodiment can form a touch sensing unit Tc that will not interfere with the display unit Du by configuring the second electrode regions 2124 and 2125 with the fourth electrode regions 2144 and 2145.

[0262] Therefore, in the architecture of the display panel D400 in this embodiment, the display unit Du and the touch sensing unit Tc can be controlled by corresponding scan lines for display and touch sensing respectively. It is not necessary to choose between the display and touch sensing time lengths in each driving cycle, which can effectively reduce the design difficulty of the control timing and also ensure that the touch sensing sensitivity does not decrease with the screen refresh rate.

[0263] In some embodiments, viewed from a top view, the first electrode regions 2121-2123 may be, for example, a square region with a side length of approximately 10 μm, and the spacing between adjacent first electrode regions is approximately 25 μm. In other words, the side lengths of the second electrode regions 2124 and 2125 and the fourth electrode regions 2144 and 2145 may be between 10 μm and 25 μm, but this application is not limited to this.

[0264] Referring to Figures 29A and 29B, the display panel D500 of this embodiment includes a plurality of pixel units Pu arranged in an array. Each pixel unit Pu includes a display unit Du and a touch sensing unit Tc, and each display unit Du has a light-emitting element (such as LED1-LED3). Looking at the cross-sectional structure along line II' in Figure 29B, the display panel D500 includes light-emitting elements LED1-LED3, a substrate 311, a metal layer ML3, a protective layer PL, a metal layer ML4, a sealing layer SL, a circuit layer WL, a bonding portion AD, and an isolation layer CDL. The metal layer ML3 includes first electrode regions 3121, 3122, and 3123 and second electrode regions 3124 and 3125 formed on the substrate 311. Each of the first electrode regions 3121-3123 is electrically connected to each other through the corresponding circuit layer WL, and the second electrode regions 3124 and 3125 are electrically independent of the first electrode regions 3121-3123.

[0265] Specifically, the display panel D500 of this embodiment has a structural configuration that is largely the same as that of the display panel D400 of the embodiments shown in Figures 28A and 28B. The main difference is that in the metal layer ML4 of the display panel D500 of this embodiment, the metal layer adjacent to the third electrode regions 3141-3143 is removed. This allows the second electrode regions 3124 and 3125 of the metal layer ML3, which were originally located on the lower side, to be unshielded by the upper metal layer ML4. Therefore, when a user touches the corresponding position of the display panel D500 with their finger, the finger capacitance can be directly coupled to the second electrode regions 3124 and 3125 of the metal layer ML3, and thus can be detected. In other words, the main structural difference between the display panel D500 of this embodiment and the display panel D400 of the aforementioned embodiments is that the metal layer ML4 of this embodiment does not include a fourth electrode region (such as 2144 and 2145) electrically connected to the second electrode regions 3124 and 3125. Therefore, a through-hole THL structure similar to that in Figure 28B does not need to be formed on the protective layer PL. Other similar parts can be referred to the description of the above embodiments, and will not be repeated here.

[0266] Overall, the embodiments in Figures 28A to 29B respectively illustrate a simplified implementation of an independent touch electrode architecture by adding independent electrode regions (i.e., second electrode regions 2124 / 2125 / 3124 / 3125) to the metal layer ML3 and dividing the metal layer ML4 configuration. In the architecture of these embodiments, the third electrode regions 2141-2143 / 3141-3143, which serve as the upper electrode, do not obscure the area of ​​the touch sensing unit Tc, so that the capacitance change caused by touching the panel can be coupled to the lower second electrode region. In other words, in these embodiments, the orthographic projection area of ​​the third electrode regions 2141-2143 / 3141-3143 on the substrate D111 does not completely overlap with (i.e., at least partially does not overlap with) the orthographic projection areas of the second electrode regions 2124 / 2125 / 3124 / 3125 on the substrate 211 / 311. In some embodiments, the orthographic projection areas of the third electrode regions 2141-2143 / 3141-3143 on the substrate D111 and the orthographic projection areas of the second electrode regions 2124 / 2125 / 3124 / 3125 on the substrate D111 do not overlap at all.

[0267] Figures 30A to 30G are schematic cross-sectional views of display panels according to different embodiments of this application. In some embodiments, the protective layer of the display panel is designed to be thicker than the height of the light-emitting elements and their corresponding lower electrode wires and junctions, so that the upper surface of the protective layer is higher than the upper electrode of each light-emitting element. Then, a special process (e.g., photolithography) is used to expose the upper electrode covered by the protective layer, forming an opening between the upper electrode of each light-emitting element and the protective layer. This allows the upper electrode wires to be electrically connected to the upper electrode within the opening, thereby achieving a planarized display panel structure (as shown in the embodiments of Figures 30A to 30F). In another embodiment, the light-emitting elements are subjected to a force toward the substrate during installation, where the light-emitting elements undergo different displacements depending on their individual size / height, resulting in different substrate spacings, thus keeping the upper electrodes of the light-emitting elements on the same plane. This allows the display panel to form a flat surface to facilitate the installation of the upper electrode wires and their electrical connection with each light-emitting element, thereby achieving a planarized display panel structure (as shown in the embodiment of Figure 30G). The structures of the embodiments shown in Figures 30A to 30G will be described below.

[0268] Referring first to Figure 30A, the display panel D600a of this embodiment includes a substrate D111, a metal layer ML3, a plurality of light-emitting elements LED1-LED3, a metal layer ML4, and a light-shielding portion 415. The metal layer ML3 is disposed on the substrate D111. The light-emitting elements LED1-LED3 are respectively disposed on the metal layer ML3 through corresponding bonding portions AD, so that the lower electrode of the light-emitting elements LED1-LED3 is electrically connected to the metal layer ML3 through the bonding portion AD. A protective layer PL is formed on the substrate D111 and covers the metal layer ML3, the bonding portion AD, and the peripheral area of ​​the light-emitting elements LED1-LED3, thereby avoiding unintended short circuits between adjacent light-emitting elements LED1-LED3. The protective layer PL exposes at least part or all of the upper electrode of the light-emitting elements LED1-LED3, and the height / thickness of the protective layer PL formed on the substrate D111 is greater than or equal to the height H1-H3 corresponding to any light-emitting element LED1-LED3, so as to form an opening OP on at least one or more of the light-emitting elements LED1-LED3. The height H1-H3 of any light-emitting element LED1-LED3 referred to herein may, for example, be the sum of the height / thickness of any light-emitting element LED1-LED3, its corresponding metal layer ML3, and the junction AD. The metal layer ML4 is disposed on the protective layer PL and extends toward the opening OP to be electrically connected to the upper electrode of each light-emitting element LED1-LED3 through the opening OP.

[0269] More specifically, metal layer ML3 includes lower electrode wires 4121-4123, and metal layer ML4 includes upper electrode wires 4141-4143. The lower electrodes of light-emitting elements LED1-LED3 are electrically connected to the lower electrode wires 4121-4123 through corresponding junctions AD, and the upper electrodes of light-emitting elements LED1-LED3 are electrically connected to the upper electrode wires 4141-4143 through corresponding openings OP. With the above configuration, light-emitting elements LED1-LED3 with different heights H1-H3 can achieve a better electrical connection effect through the upper electrode wires 4141-4143 extending to the openings OP, and the poor connection situation shown in FIG27C will not occur due to the light-emitting element being configured too low (such as LED2) or too high (such as LED3). Furthermore, since the height difference of each light-emitting element LED1-LED3 can be compensated to the same height by the upper electrode wires 4141-4143 extending to the opening, the overall upper electrode wires 4141 (including the part of the line segment located on the upper surface of the protective layer PL) can have a uniform line width. This ensures the transmission of electrical signals and also avoids process risks such as wire breakage and poor contact caused by bending of the traces.

[0270] In other words, with the structural configuration shown in Figure 30A, the upper surfaces of all light-emitting elements LED1-LED3 can be kept at essentially the same level without any height difference. Therefore, subsequent processes will not be affected by the flatness of the display panel, thereby effectively improving process yield and reliability.

[0271] In this embodiment, the substrate D111 can be a flexible or rigid substrate such as a printed circuit board, a glass substrate, or a thin film substrate, and the substrate D111 can be transparent or opaque depending on the selected material and the required application type, which is not limited to this application.

[0272] In some embodiments, the material of the bonding portion AD can be any material capable of providing adhesion to stably bond the light-emitting elements LED1-LED3 and the metal layer ML3, such as solder paste, anisotropic conductive film (ACF), or other adhesive materials. Furthermore, the bonding process for setting the light-emitting elements LED1-LED3 onto the metal layer ML3 via the bonding portion AD can be implemented by screen printing bonding, inkjet printing (IJP) bonding, or exposure development and baking, etc., and this application is not limited to these methods.

[0273] Referring to Figure 30B, the display panel D600b of this embodiment is largely the same as that of the embodiment in Figure 30A, including a substrate D111, a metal layer ML3, multiple light-emitting elements LED1-LED3, a metal layer ML4, and a light-shielding portion 415. The description of the relevant components / configurations can be found in the embodiment of Figure 30A above, and will not be repeated here.

[0274] The main difference between this embodiment and the embodiment shown in FIG30A is that the display panel D600b further includes a conductive extension portion 416. The conductive extension portion 416 is disposed within the opening OP corresponding to the light-emitting element LED2 and is electrically connected to the upper electrode of the light-emitting element LED2. The height of the conductive extension portion 416 is less than or equal to the depth of the opening OP of the light-emitting element LED2, and the upper electrode wire 4142 is electrically connected to the upper electrode of the light-emitting element LED2 through the conductive extension portion 416.

[0275] Specifically, in this embodiment, the light-emitting element LED2 is in an under-configuration state (H2).

[0276] It should be noted that the conductive extension 416 in this embodiment may only be provided in the opening of the light-emitting element that is too low in height, and other light-emitting elements that can be directly connected to the upper electrode wire may not need to have a similar configuration.

[0277] Referring to Figure 30C, the display panel D600c of this embodiment is largely the same as that in the embodiments of Figures 30A and 30B, including a substrate D111, a metal layer ML3, multiple light-emitting elements LED1-LED3, a metal layer ML4, and a light-shielding part 415. The description of the relevant components / configurations can be found in the embodiments of Figures 30A and 30B above, and will not be repeated here.

[0278] ​The main difference between this embodiment and the embodiment in Figure 30B is that the display panel D600c includes a plurality of conductive extensions 4161-4163 corresponding to the light-emitting elements LED1-LED3 respectively. The conductive extensions 4161-4163 are respectively disposed in the openings OP of the light-emitting elements LED1-LED3 and electrically connected to the upper electrodes of the corresponding light-emitting elements LED1-LED3.

[0279] In this embodiment, each conductive extension 4161-4163 fills the corresponding opening CP, so that the upper surface of the conductive extension 4161-4163 and the upper surface of the protective layer are approximately on the same plane. In other words, the height H1-H3 of each light-emitting element LED1-LED3 plus the height of the corresponding conductive extension 4161-4163 is equal to the height of the protective layer PL.

[0280] It should be noted that in this embodiment, the conductive extensions 4161-4163 can be disposed in the opening OP of each light-emitting element LED1-LED3, so that the equivalent height of each light-emitting element LED1-LED3 is equal to the height of the protective layer PL. In this way, the upper electrode wires 4141-4143 formed on the protective layer PL can extend horizontally and connect to the conductive extensions 4161-4163, and are electrically connected to the upper electrodes of the corresponding light-emitting elements LED1-LED3 through the conductive extensions 4161-4163. Therefore, the upper electrode wires 4141-4143 in this embodiment can maintain a uniform linewidth to achieve better electrical signal transmission characteristics.

[0281] Referring to Figure 30D, the display panel D600d of this embodiment is largely the same as that of the embodiment in Figure 30A, including a substrate D111, a metal layer ML3, multiple light-emitting elements LED1-LED3, a metal layer ML4, and a light-shielding portion 415. The description of the relevant components / configurations can be found in the embodiment in Figure 30A above, and will not be repeated here.

[0282] The main difference between this embodiment and the embodiment shown in FIG. 30A is that the protective layer PL of the display panel D600d includes a spacer portion 4131 and a flattening portion 4132. The spacer portion 4131 is disposed on the substrate D111 and covers a portion of the metal layer ML3, the bonding portion AD, and the light-emitting elements LED1-LED3. The flattening portion 4132 is disposed on the spacer portion to cover another portion of the light-emitting elements LED1-LED3 and exposes the upper electrode of the light-emitting elements LED1-LED3. In this embodiment, the sum of the heights of the spacer portion 4131 and the flattening portion 4132 (i.e., the height of the protective layer PL) is set to be greater than or equal to the maximum height of the light-emitting elements LED1-LED3, so as to form an opening OP on at least one or a portion of the light-emitting elements LED1-LED3. The metal layer ML4 is disposed on the flattening portion 4132 and is electrically connected to the light-emitting elements LED1-LED3 through the opening OP.

[0283] Specifically, compared to the embodiment in Figure 30A, the protective layer PL in this embodiment can be implemented using a two-layer structure. The lower layer (spacer 4131) mainly provides insulation and support, while the upper layer (flattening layer 4132) mainly provides a flat upper surface. Furthermore, a material that can be removed using a specific process is selected, allowing the upper electrodes of the light-emitting elements LED1-LED3 to be exposed after the removal process. Therefore, the structural configuration in Figure 30D can further improve the surface flatness of the display panel D600d.

[0284] In some embodiments, the spacer portion 4131 may be implemented using a material with filling and insulating properties, such as silicon nitride (SiNx), silicon oxide (SiOx), acrylic, epoxy resin, or a silicon-based polymer, and this application is not limited thereto. On the other hand, the flattening portion 4132 may be implemented using a material with good surface flatness after coating, such as acrylic, epoxy resin, or a silicon-based polymer, and this application is also not limited thereto.

[0285] Referring to Figure 30E, the display panel D600e of this embodiment is largely the same as that in the embodiments of Figures 30B and 30D, including a substrate D111, a metal layer ML3, multiple light-emitting elements LED1-LED3, a metal layer ML4, a light-shielding portion 415, and a conductive extension portion 416. The description of the related components / configurations can be found in the embodiments of Figures 30B and 30D above, and will not be repeated here.

[0286] The main difference between this embodiment and the aforementioned embodiment in Figure 30B is that the protective layer PL of the display panel D600e adopts a double-layer structure configuration as shown in Figure 30D, which includes a spacer portion 4131 and a flattening portion 4132. For the relevant configuration and material description of the spacer portion 4131 and the flattening portion 4132, please refer to the aforementioned embodiment in Figure 30D, and will not be repeated here.

[0287] Referring to Figure 30F, the display panel D600f of this embodiment is largely the same as that in the embodiments of Figures 30C and 30D, including a substrate D111, a metal layer ML3, multiple light-emitting elements LED1-LED3, a metal layer ML4, a light-shielding portion 415, and multiple conductive extension portions 4161-4163. The description of the relevant components / configurations can be found in the embodiments of Figures 30C and 30D above, and will not be repeated here.

[0288] The main difference between this embodiment and the aforementioned embodiment in Figure 30C is that the protective layer PL of the display panel D600f adopts a double-layer structure configuration as shown in Figure 30D, which includes a spacer portion 4131 and a flattening portion 4132. For the relevant configuration and material description of the spacer portion 4131 and the flattening portion 4132, please refer to the aforementioned embodiment in Figure 30D, and will not be repeated here.

[0289] Figure 30G is a schematic cross-sectional view of a display panel according to an embodiment of this application. Referring to Figure 30G, the display panel D700 of this embodiment includes a substrate D111, a metal layer ML3, a plurality of light-emitting elements LED1-LED3, a protective layer PL, a metal layer ML4, a light-shielding portion 515, and a support portion 516. The metal layer ML3 is disposed on the substrate D111. The light-emitting elements LED1-LED3 are respectively disposed on the metal layer ML3 through corresponding bonding portions AD, so that the lower electrode of the light-emitting elements LED1-LED3 is electrically connected to the metal layer ML3 through the bonding portion AD. The protective layer PL is formed on the substrate D111 and covers the metal layer ML3, the bonding portion AD, and the peripheral area of ​​the light-emitting elements LED1-LED3, thereby avoiding unintended short circuits between adjacent light-emitting elements LED1-LED3. The protective layer PL exposes at least part or all of the upper electrode of the light-emitting elements LED1-LED3, and the height / thickness of the protective layer PL formed on the substrate D111 is approximately equal to the height HL corresponding to the light-emitting elements LED1-LED3. The height HL corresponding to any light-emitting element LED1-LED3 referred to herein may, for example, be the sum of the height / thickness of any light-emitting element LED1-LED3 and its corresponding metal layer ML3 and bonding portion AD. Metal layer ML4 and light-shielding portion 515 are disposed on the protective layer PL and the upper electrode of the light-emitting elements LED1-LED3, wherein metal layer ML4 is electrically connected to the upper electrode of each light-emitting element LED1-LED3. Furthermore, in the protective layer PL, a support portion 516 is disposed between adjacent light-emitting elements LED1-LED3. The support portion 516 is used to provide a supporting force to resist the applied force during the manufacturing process of applying force to the light-emitting elements LED1-LED3, thereby defining the position of the upper electrode of the light-emitting elements LED1-LED3, wherein the upper side of the support portion 516 and the upper electrode of the light-emitting elements LED1-LED3 are approximately on the same plane. In this embodiment, the support portion 516 is, for example, columnar, and its height is less than or equal to the lowest of the light-emitting elements LED1-LED3, but this application is not limited thereto.

[0290] More specifically, metal layer ML3 includes lower electrode wires 5121-5123, and metal layer ML4 includes upper electrode wires 5141-5143. The lower electrodes of light-emitting elements LED1-LED3 are electrically connected to the lower electrode wires 5121-5123 through corresponding bonding portions AD. During the installation process, each light-emitting element LED1-LED3 is subjected to a planar force toward the substrate D111 to embed its lower electrode into the bonding portion AD. Due to differences in their size / height, each light-emitting element LED1-LED3 has a different embedding depth in the bonding portion AD, resulting in a corresponding difference in the distance between each light-emitting element LED1-LED3 and the substrate D111. For example, as shown in Figure 30G, the height H1 of light-emitting element LED1 is greater than the height H2 of light-emitting element LED2. Therefore, after a force is applied, the distance between light-emitting element LED1 and substrate D111 will be less than the distance between light-emitting element LED2 and substrate D111, so that the sum of the height H1 of light-emitting element LED1 and the corresponding distance between substrate D111 is approximately the same as the sum of the height H2 of light-emitting element LED2 and the corresponding distance between substrate D111, i.e., equal to the height HL. Similarly, the height H1 of light-emitting element LED1 is less than the height H3 of light-emitting element LED3. Therefore, after a force is applied, the distance between light-emitting element LED1 and substrate D111 will be greater than the distance between light-emitting element LED3 and substrate D111, so that the sum of the height H1 of light-emitting element LED1 and the corresponding distance between substrate D111 is approximately the same as the sum of the height H3 of light-emitting element LED3 and the corresponding distance between substrate D111.

[0291] With the above configuration, the light-emitting elements LED1-LED3, which have different heights H1-H3, will have different substrate spacings, so that the total height HL of each light-emitting element LED1-LED3 is approximately the same, thereby forming a flat surface on the display panel. This prevents the poor connection situation shown in Figure 27C from occurring due to the light-emitting elements being positioned too low (e.g., LED2) or too high (e.g., LED3). Furthermore, since the height differences H1-H3 of each light-emitting element LED1-LED3 have been compensated to the same height HL by the different substrate spacings, the electrode wires 5141-5143 can have a uniform linewidth overall. Therefore, the transmission of electrical signals can be guaranteed, while also avoiding process risks such as wire breakage and poor contact caused by bending of the traces.

[0292] In other words, with the structural configuration shown in Figure 30G, the upper surfaces of all light-emitting elements LED1-LED3 can be kept at essentially the same level without any height difference. Therefore, subsequent processes will not be affected by the flatness of the display panel, thereby effectively improving process yield and reliability.

[0293] In this embodiment, the substrate D111 can be a flexible or rigid substrate such as a printed circuit board, a glass substrate, or a thin film substrate, and the substrate D111 can be transparent or opaque depending on the selected material and the required application type, which is not limited to this application.

[0294] In some embodiments, the material of the bonding portion AD can be any material capable of providing adhesion to stably bond the light-emitting elements LED1-LED3 and the metal layer ML3, such as solder paste, anisotropic conductive film (ACF), or other adhesive materials. Furthermore, the bonding process for setting the light-emitting elements LED1-LED3 onto the metal layer ML3 via the bonding portion AD can be implemented by screen printing bonding, inkjet printing (IJP) bonding, or exposure development and baking, etc., and this application is not limited to these methods.

[0295] In summary, the display device and display panel proposed in some embodiments of this application can form independent electrodes within the display panel for touch sensing, so that the signal timing during the display period and the touch sensing period can be independent of each other, avoiding the need to make trade-offs, thereby achieving the effects of saving costs and reducing the complexity of touch signal processing.

[0296] Furthermore, some embodiments of the display device and display panel proposed in this application can form an opening structure by setting the protective layer to be higher than or equal to the upper electrode of the light-emitting element. In this configuration, the surface flatness of the display panel is determined by the protective layer and is therefore not affected by the LED size and manufacturing process. Secondly, the design of the opening structure can compensate for the height differences of each LED caused by its size and manufacturing process, while also ensuring that the upper electrode wires can be electrically connected to the upper electrodes of each LED through the openings. This results in the upper electrode wires formed on the protective layer having a uniform linewidth, ensuring the electrical signal transmission characteristics of each LED. Other embodiments of the display device, display panel, and manufacturing method proposed in this application can apply a force towards the substrate to the light-emitting element during the manufacturing process, causing the light-emitting element to have different displacements according to its individual size / height and different substrate spacings, thereby keeping the upper electrodes of the light-emitting element on the same plane. In this configuration, the size differences of individual LEDs are compensated by the different substrate spacings and are not affected by the LED size and manufacturing process, thus achieving a flat module surface. In this way, the upper electrode wires formed on the protective layer can all have a uniform linewidth, ensuring the electrical signal transmission characteristics of each LED. Because the upper surfaces of all light-emitting elements can be kept at essentially the same level without any height differences, subsequent processes are not affected by the flatness of the display panel, thereby effectively improving process yield and reliability.

[0297] It is worth mentioning that, in some embodiments, the embodiments of Figures 30A to 30G used to achieve LED surface flatness can also be applied to the touch display panel designs of Figures 27A to 29B to give the touch display panel better surface flatness. In other words, although some structures in the embodiments of Figures 29 / 30 are not shown in Figures 30 / 29 (e.g., circuit layer WL, isolation layer DL, etc.), those skilled in the art should understand, after referring to the description of the above embodiments, that the scope of this application also includes embodiments that simultaneously cover the structures of Figures 29 and 30, and will be described in advance here.

[0298] It should also be noted that the material layers (e.g., metal layers, insulating layers, etc.) described in the embodiments of this application may be described using the same or different terms in different embodiments. However, these terms are only used to describe the relative relationships between components within the current embodiment and are not specifically limited to the relative relationships of material layers between different embodiments. For example, "metal layer ML1" and "metal layer ML2" are used to describe two metal material layers with different structures / functions within the same embodiment. That is, metal layer ML1 (or the first metal layer) in one embodiment can be metal layer ML2 (or the second metal layer) in another embodiment. In other words, unless explicitly excluded in this application, material layers defined by the same term may be the same material layer or different material layers in different embodiments, which is explained in advance.

[0299] In summary, the electrostatic discharge protection structure of the display panel and the display panel and display device using it according to the embodiments of this application have been fully and clearly described. It should be noted that this application is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included within the scope of this disclosure. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

[0300] It should also be noted that any numerical values ​​mentioned in this application are not intended to limit the invention to only the specified numerical values. Those skilled in the art will understand that there are permissible errors in each numerical value / composition ratio. As long as they do not significantly affect the results / functions to be achieved by each embodiment, any value that is similar to the disclosed numerical range is considered to be within the scope of this invention.

[0301] 10, 20, 30: Display devices 100: Backlight Module 110: Emissive layer 120:Quantum dot film 121x,121y,s121_1,s121_2,s121_3,s121_4,s121_m-1,s121_m-2,s121_y: Scanning unit 130: Optical Adjustment Layer 140,D220: Driver chip 415,515:Light shielding part 416: Conductive extension 516: Support section 1121,1122,1123,2121,2122,2123,2124,2125,2141,2142,2143,2144,2145,3121,3122,3123,3124,3125: Electrode regions 4121, 4122, 4123: Lower electrode wires 4131: Spacing section 4132: Leveling section 4141, 4142, 4143: Upper electrode wires ABLK: Array Block AD: Joint BA: Border Area BA1, BA2, BA3: Border area BMX: Black Matrix C1, C2, C3, C4, Ceq1, Ceq2, Ceq3: Capacitors CDL: Isolation Layer Ch: Holding Capacitor CK1, CK2, CK3, CK4: Clock signals CL1, CL2: Conductive layers COM, COM1, COMa, COMb: Common electrode D100, D200, D300, D400, D500, D600a, D600b, D600c, D600d, D600e, D600f, D700: Display Panel D110: Pixel array substrate D111,D111',D211:Substrate D112, D212: Pixel array D113, D113', D213: Electrostatic protection structure D120: Scan drive circuit D130: Data drive circuit D140, D240: Connecting modules D150, D250: Control circuit D2U, U2D: Scan control signals DL1, DL2: Data lines DR: Display Area EM: Control signal Ep, EP11, EP12, EP21, EP32: Pixel Electrodes ER1: Inner ring structure ER2: Outer ring structure FOL: Fan-out routing FP: Frame Adhesive GFA: Fan-out area of ​​the scanning circuit GL1, GL2, GL3, GL4, GLa, GLm, GLm-1, GLm-2, GLm-3: Scan lines GLs: Scan signal Gx, Gx+2, Gx-2, Gy, Gy+2, Gy-2: Scan output terminals H1, H2, H3, HL: Height IL1, IL2: Insulating layers LC: Liquid Crystal Unit LCL: Liquid Crystal Layer Ls1, Ls2: Line segments of the scan line M1-M14, M11, M12, M21, M22, M31, M32: Transistors MD1-MD6: Modules ML1-ML4, MP1, MP2, MP2a, MP2b: Metal layers MP1e: Extended metal layer MSP1, MSP2, MSP3: Metal strip pattern N1, N2: Nodes OP: Open PL: Protective layer Pu: pixel unit RST: Reset signal SG: Sealant SR: Non-display area SUB: Glass substrate TC: Transparent conductive layer Tc: Touch sensing unit TH1, TH2, THx: Through holes TRP: Transmitting Part TX1, TX2, TX3, TXn: Touch scan lines VCOM: Common Voltage VSS: Reference Signal W1, W2: Width WL: Line Layer WR1, WR2: Transmission Section WRG1, WRG2: Fan-out transmission section

Claims

1. A display panel, characterized in that it comprises: a substrate having a display area and a non-display area, wherein the non-display area includes a border area; a pixel array disposed on the display area of ​​the substrate and having a plurality of pixel units arranged in an array; and a plurality of scan lines formed on the substrate and electrically connected to each column of pixel units of the pixel array. Multiple data lines are formed on the substrate and electrically connected to each row of pixel units in the pixel array; And an electrostatic protection structure, disposed in at least a portion of the frame area, and comprising a first metal layer, a first insulating layer, a second metal layer, and a second insulating layer stacked together, wherein at least one of the first metal layer and the second metal layer has a perforated structure to form a discontinuous island structure in the cross-section of the electrostatic protection structure, wherein the orthographic projection areas of the first metal layer and the second metal layer at least partially overlap, and the spacing between adjacent island structures forms the perforated structure.

2. The display panel as described in claim 1, wherein, The electrostatic protection structure further includes: a first conductive layer formed between the first insulating layer and the second insulating layer, and electrically connected to one of the first metal layer and the second metal layer, wherein the first conductive layer is a light-transmitting conductive layer, and the first conductive layer, the first insulating layer and the second insulating layer are stacked at the hole structure to form a plurality of light-transmitting portions, and the plurality of light-transmitting portions are arranged sequentially and at intervals along the arrangement direction of the hole structure.

3. The display panel as described in claim 1, wherein, The cross-sectional width of the first metal layer is greater than the cross-sectional width of the second metal layer.

4. The display panel as described in claim 3, wherein, The panel electrostatic protection structure includes an inner ring structure and an outer ring structure, wherein the inner ring structure has a first metal layer and a second metal layer, and the outer ring structure has only the first metal layer.

5. The display panel as described in claim 4, wherein, The electrostatic protection structure forms a metal strip pattern surrounding a portion of the non-display area based on multiple light-transmitting portions and the hole structure, and the electrostatic protection structure further includes a bridging area disposed in another portion of the non-display area, wherein the first metal layer and the second metal layer are electrically isolated from each other within the area of ​​the metal strip pattern, and are only electrically in contact with each other in the bridging area.

6. The display panel as described in claim 1, wherein, The distance between the electrostatic protection structure and the edge of the substrate is greater than or equal to 20 mm.

7. The display panel as described in any one of claims 1-6, wherein, The display panel further includes: a first fan-out transmission section disposed on one side of the non-display area and having multiple fan-out traces, wherein the multiple fan-out traces of the first fan-out transmission section are electrically connected to an odd number of the scan lines; and a second fan-out transmission section disposed on the opposite side of the non-display area relative to the first fan-out transmission section and having multiple fan-out traces, wherein the multiple fan-out traces of the second fan-out transmission section are electrically connected to an even number of the scan lines, wherein the multiple scan lines include a first scan line group and a second scan line group, the multiple fan-out traces electrically connected to the first scan line group are formed on the substrate with a first trace structure, and the multiple fan-out traces electrically connected to the second scan line group are formed on the substrate with a second trace structure.

8. The display panel as described in claim 7, wherein, The first trace structure includes a single-layer metal trace structure formed by the first metal layer, and the second trace structure includes a double-layer metal trace structure formed by the first metal layer and the second metal layer being arranged alternately.

9. The display panel as described in claim 8, wherein, The fan-out traces formed by the second metal layer are connected to the corresponding scan lines through a bridging structure, and the bridging structure includes: a first via formed on a portion of the second insulating layer covering the second metal layer; and a second via formed on a portion of the first insulating layer and the second insulating layer covering the first metal layer. A second conductive layer covers the second insulating layer, connects the second metal layer through the first through-hole, and connects the first metal layer through the second through-hole, so that the first metal layer and the second metal layer are electrically connected through the second conductive layer.

10. The display panel as described in claim 7, wherein, The non-display area further includes a data circuit fan-out area disposed adjacent to the display area, wherein the shortest distance between any scan line included in the first scan line group and the data circuit fan-out area is greater than the shortest distance between any scan line included in the second scan line group and the data circuit fan-out area.

11. The display panel as described in any one of claims 1-6, wherein, The plurality of pixel units includes a first pixel unit, and the first pixel unit includes: a thin-film transistor having a first end, a second end, and a control end, wherein the first end is electrically connected to a corresponding data line, and the control end is electrically connected to a corresponding scan line; a third insulating layer formed on the substrate; a third metal layer formed on the third insulating layer and electrically connected to the second end of the thin-film transistor; a fourth insulating layer covering the third metal layer; a common electrode having a gate-like structure and formed on the fourth insulating layer, wherein the common electrode has a first portion and a second portion, the first portion of the common electrode and the orthographic projection area of ​​the third metal layer at least partially overlap, and the second portion of the common electrode and the orthographic projection area of ​​the third metal layer substantially do not overlap; and an extended metal layer electrically connected to the third metal layer and covered by the fourth insulating layer, wherein at least a portion of the extended metal layer is formed within the orthographic projection area of ​​the second portion of the common electrode.

12. The display panel as described in claim 11, wherein, The first pixel unit further includes: a counter substrate; and a liquid crystal layer formed between the common electrode and the counter substrate; A black matrix is ​​formed on the side of the opposing substrate facing the substrate, wherein at least a portion of the orthographic projection region of the black matrix and the orthographic projection region of the second portion of the common electrode overlap each other, wherein the extended metal layer is located within the orthographic projection region of the at least portion of the black matrix.

13. The display panel as described in claim 11, wherein, Two adjacent pixel units have a spacing region, and the extended metal layer includes: a first extension, one end of which is connected to the second end of the corresponding thin-film transistor, and the other end extends toward the spacing region and is formed on the third insulating layer and at least partially covers the third metal layer; And a second extension, one end of which is connected to the other end of the first extension, and the other end of which extends along the orthographic projection region of the second common electrode and is formed on the third insulating layer.

14. The display panel as described in claim 11, wherein, Two adjacent pixel units have a spacing region, and the extended metal layer includes: a first extension, one end of which is connected to the third metal layer, and the other end of which extends toward the spacing region and is formed on the third insulating layer; And a second extension, one end of which is connected to the other end of the first extension, and the other end of which extends along the orthographic projection region of the second common electrode and is formed on the third insulating layer.

15. The display panel as described in any one of claims 1-6, wherein, The plurality of pixel units includes a first pixel unit and a second pixel unit. The first pixel unit is electrically connected to the nth scan line, and the second pixel unit is electrically connected to the (n+1)th scan line, where n is a natural number. The second pixel unit includes: a thin-film transistor having a first end, a second end, and a control end, wherein the first end is electrically connected to a corresponding data line, and the control end is electrically connected to the (n+1)th scan line; a third insulating layer formed on the substrate and covering the nth scan line; a third metal layer formed on the third insulating layer and electrically connected to the second end of the thin-film transistor, wherein the third metal layer has a first portion and a second portion; a fourth insulating layer covering the third metal layer; and a common electrode having a gate-like structure formed on the fourth insulating layer and having a first portion and a second portion, wherein the orthographic projection areas of the first portion of the third metal layer and the first portion of the common electrode at least partially overlap, and wherein the orthographic projection areas of the second portion of the third metal layer, the second portion of the common electrode, and the nth scan line at least partially overlap.

16. The display panel as described in claim 15, wherein, The nth scan line located in two adjacent column pixel units comprises a first line segment and a second line segment connected to each other, wherein the first line segment and the second line segment are not parallel to each other.

17. The display panel as described in claim 16, wherein, The overlapping area of ​​the orthographic projection region of the second part of the third metal layer and the first segment of the nth scan line is approximately the same as the overlapping area of ​​the orthographic projection region of the second part of the third metal layer and the second segment.

18. The display panel as described in claim 16, wherein, The overlapping area of ​​the orthographic projection region of the second part of the third metal layer and one of the first and second line segments of the nth scan line is greater than the overlapping area of ​​the orthographic projection region of the second part of the third metal layer and the other of the first and second line segments.

19. The display panel as described in any one of claims 1-6, wherein, It further includes: a scan driving circuit disposed on the non-display area, and comprising a plurality of scan units for electrically connecting the plurality of scan lines, wherein each scan unit includes at least one holding capacitor, and the structure of the holding capacitor includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a third conductive layer, and a fourth conductive layer, wherein: the third conductive layer and the fourth conductive layer are light-transmitting conductive layers, the third conductive layer is disposed on the second insulating layer, and the fourth conductive layer is disposed on the first insulating layer and at least a portion thereof is covered by the second insulating layer, wherein one end of the fourth conductive layer is connected to the second metal layer; wherein at least a portion thereof of the first metal layer has a through-hole formed to expose the at least a portion thereof of the first metal layer from the first insulating layer and the second insulating layer, wherein the third conductive layer is connected to the at least a portion thereof of the first metal layer exposed via the through-hole.

20. The display panel as described in claim 19, wherein, A portion of the second metal layer extends and forms on another portion of the fourth conductive layer, such that the second metal layer and the fourth conductive layer at least partially overlap in the normal direction of the substrate.

21. The display panel as described in claim 19, wherein, The holding capacitance is the sum of a first capacitor, a second capacitor, and a third capacitor, wherein the first capacitor is formed based on a first overlapping region of the first metal layer and the second metal layer and a first insulating layer located in the first overlapping region; the second capacitor is formed based on a second overlapping region of the second metal layer and the third conductive layer and a second insulating layer located in the second overlapping region; and the third capacitor is formed based on a third overlapping region of the third conductive layer and the fourth conductive layer and a second insulating layer located in the third overlapping region.

22. The display panel as described in any one of claims 1-6, wherein, The display panel further comprises: a third metal layer formed in the display area on the substrate, and comprising a plurality of first electrode regions and a plurality of second electrode regions, wherein the plurality of first electrode regions and the plurality of second electrode regions are electrically independent of each other, and the plurality of first electrode regions and the plurality of second electrode regions are alternately arranged on the substrate at intervals; a plurality of light-emitting elements, wherein each light-emitting element comprises a first electrode and a second electrode formed on opposite sides, the first electrode being electrically connected to a corresponding first electrode region; and a protective layer filling between the plurality of light-emitting elements and covering at least a portion of the surface of each light-emitting element; A fourth metal layer is formed on the protective layer and includes a plurality of third electrode regions, wherein the plurality of third electrode regions are respectively formed on the plurality of light-emitting elements and electrically connected to the second electrode of the corresponding light-emitting element, wherein each pixel unit includes a display unit and a touch sensing unit, the display unit includes a corresponding light-emitting element and a first electrode region and a third electrode region electrically connected to the corresponding light-emitting element, and the touch sensing unit includes a second electrode region and a fourth electrode region adjacent to the display unit.

23. The display panel as described in claim 22, wherein, The orthographic projection areas of the plurality of third electrode regions on the substrate will not completely overlap with the orthographic projection areas of the plurality of second electrode regions on the substrate.

24. The display panel as described in claim 23, wherein, The orthographic projection areas of the plurality of third electrode regions on the substrate and the orthographic projection areas of the plurality of second electrode regions on the substrate do not overlap at all.

25. The display panel as described in claim 24, wherein, The fourth metal layer further includes a plurality of fourth electrode regions, wherein the plurality of third electrode regions and the plurality of fourth electrode regions are electrically independent of each other, and the plurality of fourth electrode regions are electrically connected to the corresponding plurality of second electrode regions.

26. An electrostatic discharge (ESD) protection structure, characterized in that it comprises: a mother substrate including a plurality of array blocks; and a plurality of display panels sequentially arranged on the mother substrate, wherein each array block includes: a first metal layer formed on each array block in a manner surrounding at least two of the plurality of display panels to form a plurality of first ESD lines on each array block; a first insulating layer covering the first metal layer and exposing at least a portion of the first metal layer; and a second metal layer formed on the first insulating layer in a manner surrounding at least two of the plurality of display panels. The array comprises: a plurality of second electrostatic discharge lines corresponding to the plurality of first electrostatic discharge lines on each of the array blocks; a second insulating layer covering the second metal layer and exposing at least a portion of the second metal layer; and a first conductive layer formed in the bridging region, wherein at least a portion of the first conductive layer is connected to the first metal layer through the portion exposed by the first insulating layer, and at least another portion of the first conductive layer is connected to the second metal layer through the portion exposed by the second insulating layer, thereby electrically connecting the plurality of first electrostatic discharge lines and the plurality of second electrostatic discharge lines to each other in the bridging region.

27. The electrostatic discharge protection structure as described in claim 26, wherein, A portion of the bridging region is located at the corner of each of the array blocks.

28. The electrostatic discharge protection structure as described in claim 27, wherein, Another portion of the bridging area is positioned equidistant from the bridging areas at the two adjacent corners.

29. The electrostatic discharge protection structure as described in claim 26, wherein, The first insulating layer electrically isolates each of the first electrostatic discharge lines in the non-bridging region, and the second insulating layer electrically isolates each of the second electrostatic discharge lines in the non-bridging region.

30. The electrostatic discharge protection structure as described in claim 26, wherein, In the plurality of first electrostatic discharge lines and the plurality of second electrostatic discharge lines, the pitch between two adjacent first electrostatic discharge lines or second electrostatic discharge lines is greater than 200 μm.

31. The electrostatic discharge protection structure as described in claim 30, wherein, The line spacing between two adjacent first electrostatic discharge lines or second electrostatic discharge lines is between 200μm and 300μm.

32. The electrostatic discharge protection structure as described in claim 30, wherein, The width of the plurality of first electrostatic discharge lines and the plurality of second electrostatic discharge lines does not exceed 1500 μm.

33. The electrostatic protection structure as described in any one of claims 26-32, characterized in that, Each of the aforementioned display panels has a common electrode, and each of the aforementioned display panels is electrically connected to the common electrode of the adjacent display panel.

34. The electrostatic discharge protection structure as described in claim 33, wherein, The multiple display panels are arranged in the same direction.

35. The electrostatic discharge protection structure as described in claim 33, wherein, The multiple display panels in two adjacent rows or columns are arranged with a virtual line of symmetry as a reference, facing opposite sides.

36. The electrostatic discharge protection structure as described in any one of claims 26-32, wherein, Each of the aforementioned display panels includes: a substrate having a display area and a non-display area, wherein the non-display area includes a border area; a pixel array disposed on the display area of ​​the substrate and having a plurality of pixel units arranged in an array; and a plurality of scan lines formed on the substrate and electrically connected to each column of pixel units of the pixel array. Multiple data lines are formed on the substrate and electrically connected to each row of pixel units of the pixel array; and multiple metal strip patterns surround at least a portion of the border region, wherein each metal strip pattern comprises a stacked first metal layer, a first insulating layer, a second metal layer, and a second insulating layer, wherein at least one of the first metal layer and the second metal layer in each metal strip pattern has a hole structure to form a discontinuous island structure in the cross-section of the corresponding metal strip pattern, wherein the orthographic projection regions of the first metal layer and the second metal layer at least partially overlap, and the spacing between adjacent island structures forms the hole structure.

37. The electrostatic discharge protection structure as described in claim 36, wherein, Each of the metal strip patterns further includes: a second conductive layer formed between the first insulating layer and the second insulating layer, and electrically connected to one of the first metal layer and the second metal layer, wherein the second conductive layer is a light-transmitting conductive layer, and the second conductive layer, the first insulating layer and the second insulating layer are stacked at the hole structure to form a plurality of light-transmitting portions, and the plurality of light-transmitting portions are arranged sequentially at intervals along the arrangement direction of the hole structure.

38. The electrostatic discharge protection structure as described in claim 36, wherein, Each of the metal strip patterns has an inner ring structure and an outer ring structure, wherein the inner ring structure includes a first metal layer and a second metal layer, the outer ring structure does not include the second metal layer, and the cross-sectional width of the first metal layer in each of the metal strip patterns is greater than the cross-sectional width of the second metal layer.

39. A display device, characterized in that it comprises: a display panel as described in any one of claims 1-6, wherein each pixel unit includes a display unit and a touch sensing unit; a display driver chip electrically connected to the display unit for controlling the illumination state of the display unit; and a touch sensing chip electrically connected to the touch sensing unit for driving the touch sensing unit.

40. The display device as claimed in claim 39, wherein, The display panel further comprises: a third metal layer formed in the display area on the substrate, and comprising a plurality of first electrode regions and a plurality of second electrode regions, wherein the plurality of first electrode regions and the plurality of second electrode regions are electrically independent of each other, and the plurality of first electrode regions and the plurality of second electrode regions are alternately arranged on the substrate at intervals; a plurality of light-emitting elements, wherein each light-emitting element comprises a first electrode and a second electrode formed on opposite sides, the first electrode being electrically connected to a corresponding first electrode region; and a protective layer filling between the plurality of light-emitting elements and covering at least a portion of the surface of each light-emitting element; A fourth metal layer is formed on the protective layer and includes a plurality of third electrode regions, wherein the plurality of third electrode regions are respectively formed on the plurality of light-emitting elements and electrically connected to the second electrode of the corresponding light-emitting element, wherein each pixel unit includes a display unit and a touch sensing unit, the display unit includes a corresponding light-emitting element and a first electrode region and a third electrode region electrically connected to the corresponding light-emitting element, and the touch sensing unit includes a second electrode region and a fourth electrode region adjacent to the display unit.

41. The display device as claimed in claim 40, wherein, The display panel further includes: a first fan-out transmission section disposed on one side of the non-display area and having multiple fan-out traces, wherein the multiple fan-out traces of the first fan-out transmission section are electrically connected to an odd number of the scan lines; and a second fan-out transmission section disposed on the opposite side of the non-display area relative to the first fan-out transmission section and having multiple fan-out traces, wherein the multiple fan-out traces of the second fan-out transmission section are electrically connected to an even number of the scan lines, wherein the multiple scan lines include a first scan line group and a second scan line group, the multiple fan-out traces electrically connected to the first scan line group are formed on the substrate with a first trace structure, and the multiple fan-out traces electrically connected to the second scan line group are formed on the substrate with a second trace structure.

42. The display device as claimed in claim 41, wherein, The display driver chip includes: a scan driver circuit disposed on the non-display area, and including a plurality of scan units for electrically connecting the plurality of scan lines, wherein each scan unit includes at least one holding capacitor, and the structure of the holding capacitor includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a third conductive layer, and a fourth conductive layer, wherein: the third conductive layer and the fourth conductive layer are light-transmitting conductive layers, the third conductive layer is disposed on the second insulating layer, and the fourth conductive layer is disposed on the first insulating layer and at least a portion thereof is covered by the second insulating layer, wherein one end of the fourth conductive layer is connected to the second metal layer; wherein at least a portion thereof of the first metal layer has a via formed to expose the at least a portion thereof of the first metal layer from the first insulating layer and the second insulating layer, wherein the third conductive layer is connected to the exposed at least a portion thereof of the first metal layer via the via.

43. The display device as claimed in claim 41, wherein, The plurality of pixel units includes a first pixel unit, and the first pixel unit includes: a thin-film transistor having a first end, a second end, and a control end, wherein the first end is electrically connected to a corresponding data line, and the control end is electrically connected to a corresponding scan line; a third insulating layer formed on the substrate; a third metal layer formed on the third insulating layer and electrically connected to the second end of the thin-film transistor; a fourth insulating layer covering the third metal layer; a common electrode having a gate-like structure and formed on the fourth insulating layer, wherein the common electrode has a first portion and a second portion, the first portion of the common electrode and the orthographic projection area of ​​the third metal layer at least partially overlap, and the second portion of the common electrode and the orthographic projection area of ​​the third metal layer substantially do not overlap; and an extended metal layer electrically connected to the third metal layer and covered by the fourth insulating layer, wherein at least a portion of the extended metal layer is formed within the orthographic projection area of ​​the second portion of the common electrode.

44. The display device as claimed in claim 41, wherein, The plurality of pixel units includes a first pixel unit and a second pixel unit. The first pixel unit is electrically connected to the nth scan line, and the second pixel unit is electrically connected to the (n+1)th scan line, where n is a natural number. The second pixel unit includes: a thin-film transistor having a first end, a second end, and a control end, wherein the first end is electrically connected to a corresponding data line, and the control end is electrically connected to the (n+1)th scan line; a third insulating layer formed on the substrate and covering the nth scan line; a third metal layer formed on the third insulating layer and electrically connected to the second end of the thin-film transistor, wherein the third metal layer has a first portion and a second portion; a fourth insulating layer covering the third metal layer; and a common electrode having a gate-like structure formed on the fourth insulating layer and having a first portion and a second portion, wherein the orthographic projection areas of the first portion of the third metal layer and the first portion of the common electrode at least partially overlap, and wherein the orthographic projection areas of the second portion of the third metal layer, the second portion of the common electrode, and the nth scan line at least partially overlap.

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