Resistive random-access memory device and method for manufacturing the same

Abstract

This invention provides a resistive random access memory (RRAM) device, comprising a substrate, a first tantalum oxide layer on the substrate, a second tantalum oxide layer on the first tantalum oxide layer, a first gap layer covering the sidewalls of the first tantalum oxide layer, and a second gap layer covering the top surface of the first gap layer and the sidewalls of the second tantalum oxide layer, wherein the oxygen content of the second gap layer is higher than that of the first gap layer. This invention proposes an innovative double-layer gap layer design, combined with annealing treatment, to achieve RRAM performance reset by actively controlling the oxygen concentration distribution. Compared to traditional technologies that rely on external repair, this offers the potential for simplified manufacturing processes and reduced costs, enhancing the competitiveness of RRAM in high-durability applications.

Claims

1. A resistive random access memory (RRAM) device, comprising: One base; A first tantalum oxide layer is located on the substrate; A second tantalum oxide layer is located on the first tantalum oxide layer; a first interstitial layer covers the sidewalls of the first tantalum oxide layer; and a second interstitial layer covers the top surface of the first interstitial layer and the sidewalls of the second tantalum oxide layer, wherein the oxygen content of the second interstitial layer is higher than the oxygen content of the first interstitial layer.

2. The resistive random access memory device as claimed in claim 1, wherein, viewed in a cross-sectional view, the first gap layer has a U-shaped cross-section.

3. The resistive random access memory device as claimed in claim 1, wherein the first gap layer contacts only the sidewall of the first tantalum oxide layer and not the sidewall of the second tantalum oxide layer.

4. The resistive random access memory device as claimed in claim 1, wherein a top surface of the first gap layer is flush with a top surface of the first tantalum oxide layer.

5. The resistive random access memory device as claimed in claim 1, wherein the second gap layer contacts only the sidewall of the second tantalum oxide layer and not the sidewall of the first tantalum oxide layer.

6. The resistive random access memory device as claimed in claim 1, further comprising a lower electrode located below the first tantalum oxide layer and a top electrode layer located on the second tantalum oxide layer.

7. The resistive random access memory device as claimed in claim 6, wherein the second gap layer further covers a top surface of the top electrode layer and a sidewall of the top electrode layer.

8. The resistive random access memory device as claimed in claim 1, wherein the first tantalum oxide layer has the molecular formula TaOx, where x is greater than 0 and less than 2.

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9. The resistive random access memory device as claimed in claim 1, wherein the second tantalum oxide layer comprises tantalum pentoxide (Ta2O5), and the oxygen content of the second interstitial layer is higher than 66%.

10. A method for manufacturing a resistive random access memory (RRAM) device, comprising: Provide a base; A first tantalum oxide layer is formed on the substrate; A second tantalum oxide layer is formed on the first tantalum oxide layer; a first gap layer is formed to cover the sidewalls of the first tantalum oxide layer; and a second gap layer is formed to cover the top surface of the first gap layer and the sidewalls of the second tantalum oxide layer, wherein the oxygen content of the second gap layer is higher than the oxygen content of the first gap layer.

11. A method for manufacturing a resistive random access memory device as described in claim 10, wherein after the resistive random access memory device has been used for a period of time, the first tantalum oxide layer and the second tantalum oxide layer are fused together to form a third tantalum oxide layer.

12. A method for manufacturing a resistive random access memory device as described in claim 11, wherein the first tantalum oxide layer has the molecular formula TaOx, where x is greater than 0 and less than 2.5, the second tantalum oxide layer comprises tantalum pentoxide (Ta2O5), and the third tantalum oxide layer has the molecular formula TaOy, where y is greater than x and less than 2.

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13. The method for manufacturing a resistive random access memory device as described in claim 12, wherein after the formation of the third tantalum oxide layer, an annealing process is further performed, after which the third tantalum oxide layer reverts to the first tantalum oxide layer and the second tantalum oxide layer.

14. A method for manufacturing a resistive random access memory device as described in claim 13, wherein during the annealing process, the second interstitial layer releases oxygen atoms to the upper half of the third tantalum oxide layer, thereby transforming the upper half of the third tantalum oxide layer into the second tantalum oxide layer.

15. A method for manufacturing a resistive random access memory device as described in claim 13, wherein during the annealing process, the first gap layer absorbs oxygen atoms from the lower half of the third tantalum oxide layer, thereby converting the lower half of the third tantalum oxide layer into the first tantalum oxide layer.

16. A method for manufacturing a resistive random access memory device as described in claim 10, wherein the first gap layer contacts only the sidewall of the first tantalum oxide layer and not the sidewall of the second tantalum oxide layer.

17. A method for manufacturing a resistive random access memory device as described in claim 10, wherein a top surface of the first gap layer is flush with a top surface of the first tantalum oxide layer.

18. A method for manufacturing a resistive random access memory device as described in claim 10, wherein the second gap layer contacts only the sidewall of the second tantalum oxide layer and not the sidewall of the first tantalum oxide layer.

19. A method for manufacturing a resistive random access memory device as described in claim 10, further comprising forming a lower electrode located below the first tantalum oxide layer and forming a top electrode layer located on the second tantalum oxide layer.

20. A method for manufacturing a resistive random access memory device as described in claim 19, wherein the second gap layer further covers a top surface of the top electrode layer and a sidewall of the top electrode layer.

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