Wafer stacking structure with a dummy wafer and method of manufacturing the same

Abstract

This invention proposes a wafer stacking structure with a dummy wafer, comprising multiple component wafers vertically bonded one by one through a front circuit layer on the front side of a substrate or a back circuit layer on the back side of the substrate, wherein the front circuit layer and the back circuit layer of a component wafer are electrically connected through silicon through-hole vertical interconnects. A dummy wafer is vertically bonded to the topmost component wafer, wherein the dummy wafer has no valid circuitry or components, and multiple input / output terminals are disposed on the front or back circuit layer of the bottommost component wafer.

Claims

1. A wafer stacking structure with a dummy wafer, comprising: multiple component wafers, vertically bonded one by one through a front circuit layer on the front side of a substrate or a back circuit layer on the back side of the substrate, wherein the front circuit layer and the back circuit layer of one component wafer are electrically connected through silicon through-hole vertical interconnects; a dummy wafer, vertically bonded to the uppermost component wafer, wherein the dummy wafer has no valid circuitry or components, and the dummy wafer and the uppermost component wafer respectively include a hybrid bonding layer composed of a dielectric layer and a metal layer, the dummy wafer and the uppermost component wafer being bonded to each other through the dielectric layer and the metal layer; and a plurality of input / output terminals disposed on the front circuit layer or the back circuit layer of the lowermost component wafer.

2. The wafer stacking structure with a dummy wafer as described in claim 1, wherein the dummy wafer is a pure silicon wafer or a glass substrate.

3. The wafer stack structure with a dummy wafer as described in claim 1, wherein the endpoint of the silicon through-hole vertical interconnect in the uppermost element wafer is connected to the metal layer bonded between the uppermost element wafer and the dummy wafer to form a heat dissipation channel.

4. The wafer stacking structure with a dummy wafer as described in claim 1 further includes an radio frequency circuit layer disposed on the uppermost component wafer and directly bonded to the dummy wafer.

5. A wafer stacking structure with a dummy wafer as described in claim 1, wherein the front circuit layer includes a component layer on the substrate and a back interconnect layer on the component layer.

6. A wafer stack structure with a dummy wafer as described in claim 1, wherein the front circuit layer includes the endpoints, redistribution layers, or pads of the silicon through-hole vertical interconnect.

7. A wafer stack structure with a dummy wafer as described in claim 1, wherein the back circuit layer includes the endpoints, redistribution layers, or pads of the silicon through-hole vertical interconnect.

8. A method for manufacturing a wafer stack structure with a dummy wafer, comprising: providing a carrier wafer and a plurality of component wafers; vertically bonding the component wafers sequentially from the uppermost to the lowermost through a front circuit layer on the front side of a substrate or a back circuit layer on the back side of the substrate, wherein the front circuit layer and the back circuit layer of a component wafer are electrically connected through silicon through-hole vertical interconnects; after the component wafers are bonded to the carrier wafer, retaining the carrier wafer as a dummy wafer of the wafer stack structure, wherein the dummy wafer does not contain any active circuitry or components, and the dummy wafer is bonded to the uppermost component wafer through a hybrid bonding method.

9. The method for manufacturing a wafer stack structure with a dummy wafer as described in claim 8 further includes forming a plurality of input / output terminals on the front circuit layer or the back circuit layer of the lowest element wafer.

10. A method for manufacturing a wafer stack structure having a dummy wafer as described in claim 8, wherein the dummy wafer is a pure silicon wafer or a glass substrate.

11. The method for manufacturing a wafer stack structure having a dummy wafer as described in claim 8 further includes forming a hybrid bonding layer consisting of a dielectric layer and a metal layer on the surface of the substrate of the uppermost element wafer and on a surface of the dummy wafer, respectively.

12. A method for manufacturing a wafer stack structure with a dummy wafer as described in claim 11, wherein one end of the silicon through-hole vertical interconnect in the uppermost element wafer is connected to the metal layer bonded in the hybrid bonding layer between the uppermost element wafer and the dummy wafer, forming a heat dissipation channel.

Images