Transistor with strain-modulation structure and method of fabricating the same

Abstract

This invention relates to a transistor with a strain-controlled region and its fabrication method. A heterostructure is formed within the drain or source structure region of the silicon substrate of the transistor. Due to the difference in thermal expansion coefficients between the silicon substrate and the heterostructure, strain is induced in the transistor's channels, forming a strain-controlled region. This region controls the energy valley distribution of the carriers within the channels, increasing band curvature and correspondingly reducing the effective mass of the carriers, thereby improving carrier mobility. The fabrication method includes selective etching of the drain or source structure region on the silicon substrate surface to form trenches, and growing the heterostructure within the trenches, thus forming the transistor with the strain-controlled region.

Claims

1. A transistor with a strain-controlled region, comprising: A silicon substrate has a channel; a gate structure disposed above the channel; a source structure disposed on one side of the silicon substrate with respect to the gate structure; and a drain structure disposed on the other side of the silicon substrate with respect to the gate structure; wherein a trench or a plurality of trenches are provided in the region where the source structure or the region where the drain structure is located, and each of the trenches or the plurality of trenches has a heterostructure, each of the heterostructures or the plurality of heterostructures having a different coefficient of thermal expansion relative to the silicon substrate, the difference in the coefficient of thermal expansion between the heterostructures or the plurality of heterostructures and the silicon substrate during the cooling stage of the manufacturing process, and a strain force is applied along the extension direction of the channel to form a strain control zone; wherein each of the trenches or the plurality of trenches includes a vertical hole and a V-groove, the depth of the vertical hole being at least beyond the channel, and the V-groove being disposed on the bottom surface of the vertical hole.

2. The transistor with strain control region as claimed in claim 1, wherein the surface of the silicon substrate is a first crystal plane, the first crystal plane being a (100) crystal plane.

3. The transistor with strain-controlled regions as described in claim 1, wherein the plurality of trenches are arranged in an array.

4. The transistor with strain control region as described in claim 1, wherein each of the V-grooves exposes a second crystal plane, the second crystal plane being the (111) crystal plane.

5. The transistor with strain control region as described in claim 4, wherein each of the V-grooves is provided with a buffer layer.

6. The transistor with a strain-controlled region as described in claim 5, wherein each of the heterostructures comprises: A heterogeneous undoped layer is disposed on each of its respective buffer layers; And a hetero-doped layer, disposed on the respective hetero-undoped layer.

7. The transistor with strain-controlled region as described in claim 1, wherein the material of the heterostructure is a group III-V material.

8. The transistor with a strain-controlled region as described in claim 1, wherein the material of the heterostructure is gallium nitride.

9. The transistor with a strain control region as described in claim 1, wherein the strain control region occupies 0.1 to 70% of the channel.

10. A method for manufacturing a transistor with a strain-controlled region, characterized by comprising the following steps: preparing a silicon substrate: providing the silicon substrate, the silicon substrate having a first crystal plane as its surface; defining a pattern: defining a pattern in a selected region of a source structure or a drain structure on the silicon substrate; fabricating a trench: fabricating a trench at the pattern definition location, and exposing a second crystal plane at the bottom of the trench; fabricating a buffer layer: depositing a buffer layer at the bottom of the trench; fabricating a heterostructure: depositing and forming a heterostructure on the buffer layer, the heterostructure comprising a stacked structure of at least an undoped region and a heavily doped region; Doping and annealing: Ion implantation is performed in the region where the source structure or drain structure is located (where the heterostructure is not present) to achieve a predetermined doping concentration, followed by thermal annealing. Annealing provides energy, causing the doped atoms to move into their lattice positions on the silicon substrate. And gate structure fabrication: A gate structure is formed above the channel between the source and drain structures. Above the channel is a dielectric layer, and above the dielectric layer is a metal gate. By utilizing the difference in thermal expansion coefficients or lattice constants between the heterolayer and the substrate material, strain is induced along the channel direction during the cooling process to form a strain-controlled region. The step of creating the trench further includes: creating a vertical hole: forming a vertical hole at a pattern-defined location by etching, wherein the depth of the vertical hole is at least greater than the channel; Sidewall passivation: A second passivation layer is formed by depositing passivation material on the silicon substrate. The second passivation layer is grown on the surface of the first passivation layer and the sidewall and bottom surface of the vertical hole. Partial passivation layer removal: The second passivation layer on the surface of the first passivation layer and the bottom of the vertical hole is removed by etching to complete the sidewall passivation of the vertical hole. V-groove etching: A V-groove is etched at the bottom of the vertical hole, and a second crystal plane of the silicon substrate is exposed in the V-groove. The second crystal plane is (110) crystal plane to form the trench.

11. A method for manufacturing a transistor with a strain-controlled region as described in claim 10, wherein before performing the step of defining the pattern, the method further includes: Fabrication of the first passivation layer: A first passivation layer is deposited on the surface of a silicon substrate.

12. A method for manufacturing a transistor with a strain-controlled region as described in claim 11, wherein in the step of defining the pattern, a mask layer is first fabricated on the first passivation layer, and then electron beam lithography is used to remove the mask layer according to a predefined pattern to expose the first passivation layer, thereby completing the step of defining the pattern.

13. A method for manufacturing a transistor with a strain-controlled region as described in claim 12, wherein the step of fabricating the buffer layer involves depositing the buffer layer in the V-groove.

14. The method for manufacturing a transistor with a strain-controlled region as described in claim 13, wherein the step of forming a heterostructure further includes: Growth of a pre-heterogeneous undoped layer: A pre-heterogeneous undoped material is grown on the buffer layer to form a pre-heterogeneous undoped layer; Cleaning the surface of the silicon substrate: The pre-heterogeneous undoped layer and the buffer layer are removed from the surface of the silicon substrate; Cleaning the trench: The first passivation layer on the surface of the silicon substrate, the second passivation layer on the sidewall of the trench, and a portion of the removed pre-heterogeneous undoped layer are removed to form a heterogeneous undoped layer; And the growth of a heterogeneous doped layer: a heterogeneous doped layer is grown on the remaining undoped heterogeneous layer.

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