Semiconductor device and method for forming the same

TWI938047BActive Publication Date: 2026-09-01POWERCHIP SEMICON MFG CORP
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Patent Information

Application Number
TW114134874
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-09-11
Publication Date
2026-09-01
Estimated Expiration
2045-09-10

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    Figure TWG2TB001909035_003
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Abstract

This disclosure provides a semiconductor device and a method for forming the same. The semiconductor device includes a substrate, a plurality of support structures, a plurality of first capacitor structures, and a plurality of second capacitor structures. The substrate includes a plurality of trenches extending therefrom from a top surface of the substrate. The plurality of support structures are respectively disposed in the plurality of trenches, each having a top surface higher than the top surface of the substrate, and including inner sidewalls and outer sidewalls opposite to each other and connected by the top surface. The inner sidewalls of the support structures and the bottom surfaces connecting the inner sidewalls define a first trench in the trench, while the outer sidewalls of two adjacent support structures, together with the top surface of the substrate, define a second trench between two adjacent first trenches. The plurality of first capacitor structures are respectively disposed in the plurality of first trenches. The plurality of second capacitor structures are respectively disposed in the plurality of second trenches.
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Claims

1. A semiconductor device, comprising: The substrate includes a plurality of trenches extending therefrom from the top surface of the substrate; Multiple support structures, each disposed in a plurality of said trenches, having a top surface higher than the top surface of the base, and including inner and outer sidewalls opposite to each other and connected by the top surface, wherein the inner sidewalls of said support structures and the bottom surface connecting the inner sidewalls define a first trench in said trenches, and the outer sidewalls of two adjacent said support structures, together with the top surface of the base, define a second trench between two adjacent first trenches; multiple first capacitor structures, each disposed in a plurality of said first trenches; And multiple second capacitor structures, each disposed in multiple second trenches.

2. The semiconductor device of claim 1, wherein the first capacitor structure and the second capacitor structure include a lower electrode layer extending along the bottom surface, the inner sidewall, the top surface and the outer sidewall of the support structure and the top surface of the substrate, an upper electrode layer disposed above the lower electrode layer, and a first dielectric disposed between the lower electrode layer and the upper electrode layer.

3. The semiconductor device as claimed in claim 2, further comprising: A first insulating layer is disposed on the substrate and covers a plurality of the support structures, a plurality of the first capacitor structures and a plurality of the second capacitor structures; A first conductive contact is disposed in the first insulating layer and electrically connected to the upper electrode layer; and a second conductive contact is disposed in the first insulating layer and electrically connected to the lower electrode layer through the first dielectric.

4. The semiconductor device of claim 3, wherein the second conductive contact is spaced horizontally from the upper electrode layer.

5. A semiconductor device, comprising: The substrate includes a plurality of trenches extending therefrom from the top surface of the substrate; A plurality of conductive support structures are respectively disposed in a plurality of said trenches, each having a top surface higher than the top surface of the substrate, and including inner sidewalls and outer sidewalls opposite to each other and connected by the top surface, wherein the inner sidewalls of said conductive support structures and the bottom surface connecting said inner sidewalls define a first trench in said trench, and the outer sidewalls of two adjacent said conductive support structures together with the top surface of the substrate define a second trench between two adjacent first trenches; a first dielectric extends on the bottom surface, the inner sidewalls, the top surface and the outer sidewalls of said conductive support structures and on the top surface of the substrate; And an upper electrode layer, disposed on the first dielectric, to form a plurality of first capacitor structures and a plurality of second capacitor structures in a plurality of first trenches and a plurality of second trenches respectively.

6. The semiconductor device as claimed in claim 5, further comprising: A conductive patterned layer is disposed on and electrically connected to the upper electrode layer, and the substrate includes a doped silicon substrate, wherein the conductive support structure is electrically connected to the doped silicon substrate.

7. A method of forming a semiconductor device, comprising: Multiple trenches are formed in the substrate, extending from the top surface of the substrate into it; Multiple support structures are formed in multiple trenches, each support structure having a top surface higher than the top surface of the base and including inner and outer sidewalls opposite to each other and connected by the top surface. The inner sidewalls of the support structures and the bottom surfaces connecting the inner sidewalls define a first trench in the trench, while the outer sidewalls of two adjacent support structures, together with the top surface of the base, define a second trench between two adjacent first trenches. Multiple first capacitor structures are formed in multiple first trenches; and multiple second capacitor structures are formed in multiple second trenches.

8. The method of claim 7, wherein the first capacitor structure and the second capacitor structure include a lower electrode layer extending along the bottom surface, the inner sidewall, the top surface and the outer sidewall of the support structure and the top surface of the substrate, an upper electrode layer formed above the lower electrode layer, and a first dielectric formed between the lower electrode layer and the upper electrode layer.

9. The method as described in claim 8, further comprising: A first insulating layer is formed on the substrate, covering the plurality of the support structures, the plurality of the first capacitor structures and the plurality of the second capacitor structures; A first conductive contact electrically connected to the upper electrode layer is formed in the first insulating layer; and a second conductive contact passing through the first dielectric to be electrically connected to the lower electrode layer is formed in the first insulating layer.

10. The method of claim 9, wherein the second conductive contact is spaced horizontally from the upper electrode layer.

Citation Information

Patent Citations

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    TW202444192A