Semiconductor structure and method for manufacturing the same

TWI938076BActive Publication Date: 2026-09-01DIODES INC
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Patent Information

Application Number
TW114139423
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Priority Date
2025-08-07
Filing Date
2025-10-14
Publication Date
2026-09-01
Estimated Expiration
2045-10-13

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    Figure TWG2TB001909064_003
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Abstract

Embodiments of the present invention relate to a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a semiconductor material layer having a first surface and a second surface relative to the first surface, wherein the semiconductor material layer has a first conductivity type; an oxide layer disposed on the semiconductor material layer, having a first region, a second region, and a groove, the second region being located between the groove and the first region, the groove penetrating the oxide layer; and a first contact member disposed on the semiconductor material layer, located in the groove, and at least a portion of the first contact member being surrounded by the oxide layer, wherein the first region has a first thickness, and the second region has a second thickness different from the first thickness.
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Claims

1. A semiconductor structure comprising: A semiconductor material layer having a first surface and a second surface opposite to the first surface, wherein the semiconductor material layer has a first conductivity type; An oxide layer is disposed on the semiconductor material layer, having a first region, a second region, and a groove, the second region being located between the groove and the first region, the groove penetrating the oxide layer; and a first contact is disposed on the semiconductor material layer, located in the groove, and at least a portion of the first contact is surrounded by the oxide layer, wherein the first region has a first thickness, and the second region has a second thickness different from the first thickness.

2. The semiconductor structure according to claim 1, wherein the second region of the oxide layer is located between the first region and the first contact.

3. The semiconductor structure according to claim 1, wherein the second region of the oxide layer is surrounded by the first region.

4. The semiconductor structure according to claim 1, wherein there is a first distance between the first contact and the second region of the oxide layer, the first distance being greater than zero.

5. The semiconductor structure according to claim 1, wherein the first thickness is greater than the second thickness.

6. The semiconductor structure according to claim 1, wherein the first thickness is less than the second thickness.

7. The semiconductor structure according to claim 1, further comprising: A first doped region extends from the first surface to the second surface, wherein the first doped region has a second conductivity type and is located below the oxide layer in the second region.

8. The semiconductor structure according to claim 7, wherein the oxide layer in the second region is perpendicularly aligned with the first doped region.

9. The semiconductor structure according to claim 7, wherein the width of the oxide layer in the second region is substantially the same as the width of the first doped region.

10. The semiconductor structure according to claim 7, further comprising: A second doped region extends from the first surface to the second surface, wherein the second doped region has the second conductivity type, and the second doped region is located below the interface between the first contact and the oxide layer.

11. The semiconductor structure according to claim 10, wherein there is a second distance between the first doped region and the second doped region, the second distance being greater than zero.

12. The semiconductor structure according to claim 1, wherein the first contact further comprises: A masking layer is disposed on the semiconductor material layer; A conductive layer is disposed on the masking layer; And a welding layer is disposed on the conductive layer.

13. The semiconductor structure according to claim 12, wherein the first contact further comprises: A side-cut structure is formed in the masking layer and is located between the oxide layer and the conductive layer.

14. The semiconductor structure according to claim 1, wherein the first contact is an anode or electrically connected to an anode.

15. The semiconductor structure according to claim 1, further comprising: A conductive material layer is formed on or beneath the surface of the oxide layer in the second region.

16. A semiconductor structure comprising: A semiconductor material layer having a first surface and a second surface opposite to the first surface, wherein the semiconductor material layer has a first conductivity type; An oxide layer is disposed on the semiconductor material layer, having a first groove and a second groove adjacent to the first groove and penetrating the oxide layer; a first contact is disposed on the semiconductor material layer and located in the second groove; and a first doped region extends from the first surface to the second surface, wherein the first doped region has a second conductivity type, and wherein the first doped region is located below the first groove.

17. The semiconductor structure according to claim 16, further comprising: A second doped region extends from the first surface to the second surface, wherein the second doped region has the second conductivity type, and the second doped region is located below the interface between the first contact and the oxide layer.

18. The semiconductor structure according to claim 16, wherein the oxide layer further has a third groove and an outer boundary, the third groove being located between the first groove and the outer boundary, and a third doped region having the second conductivity type extending from the first surface to the second surface below the third groove.

19. The semiconductor structure according to claim 18, wherein the depth of the first doped region is substantially the same as the depth of the third doped region.

20. The semiconductor structure according to claim 18, wherein the first doped region is surrounded by the third doped region.

21. The semiconductor structure according to claim 18, wherein the width of the third groove is substantially the same as the width of the first groove.

22. The semiconductor structure according to claim 18, wherein the width of the third groove is substantially the same as the width of the third doped region.

23. The semiconductor structure according to claim 16, further comprising: An encapsulation material layer is disposed on and around the oxide layer and the first contact, wherein at least a portion of the encapsulation material layer is disposed in the first groove.

24. The semiconductor structure according to claim 23, wherein the first contact further comprises: A side-cut structure is formed at a first end of the edge of the first contact or at a second end opposite to the first end, wherein at least a portion of the encapsulation material layer is disposed in the side-cut structure and located between the oxide layer and the first contact.

25. A method for manufacturing a semiconductor structure, comprising: A semiconductor material layer is received, having a first surface and a second surface relative to the first surface; An oxide layer is formed on the semiconductor material layer; A first groove is formed in the oxide layer; a second groove is formed in the oxide layer adjacent to the first groove, exposing the semiconductor material layer from the second groove; a first doped region is formed in the semiconductor material layer through the first groove; And forming a first contact in the second groove, wherein the first doped region is located below the first groove.

26. The manufacturing method according to claim 25, wherein there is a first distance between the first contact and the first groove, the first distance being greater than zero.

27. The manufacturing method according to claim 25, further comprising: An encapsulation material layer is formed on the oxide layer and the first contact, wherein at least a portion of the oxide layer is disposed between the encapsulation material layer and the first doped region.

28. The manufacturing method according to claim 25, wherein the semiconductor material layer has a diced region; the first groove is located between the diced region and the first contact.

29. The manufacturing method according to claim 25, wherein forming the first contact further comprises: A masking layer is formed in the second groove, so that the masking layer is in contact with the semiconductor material layer and the oxide layer; A conductive layer is formed on the masking layer.

30. The manufacturing method according to claim 29, wherein forming the first contact further comprises: Simultaneously, the mask layer and the conductive layer are etched to form a side-cut structure located between the oxide layer and the first contact.

31. The manufacturing method according to claim 30, wherein, The etching rate of the mask layer is different from that of the conductive layer.

32. The manufacturing method according to claim 31, wherein the etching rate of the mask layer is greater than the etching rate of the conductive layer.

33. The manufacturing method according to claim 29, wherein forming the first contact further comprises: A solder layer is formed on the conductive layer, wherein the etching rate of the mask layer is different from the etching rate of the solder layer.

34. The manufacturing method according to claim 25, further comprising: A third conductive layer is formed on the second surface of the semiconductor material layer.

35. The manufacturing method according to claim 25, further comprising: A second doped region is formed in the semiconductor material layer through the second groove, wherein at least a portion of the second doped region is exposed from the second groove.

36. The manufacturing method according to claim 35, wherein the first doped region and the second doped region are formed simultaneously.

37. The manufacturing method according to claim 25, further comprising: A third groove is formed in the oxide layer adjacent to the first groove, the first groove being located between the second groove and the third groove; and a third doped region is formed in the semiconductor material layer through the third groove, wherein the third groove and the first groove are formed simultaneously, and the third doped region and the first doped region are formed simultaneously.

38. The manufacturing method according to claim 25, further comprising: A first opening is formed in the oxide layer adjacent to the first groove; And enlarge the first opening to form the second groove in the oxide layer, wherein the first doped region is formed through the first opening.

39. The manufacturing method according to claim 38, wherein the first groove and the first opening are formed simultaneously.

40. The manufacturing method according to claim 38, wherein forming the first groove and forming the first opening are performed before forming the second groove.

Citation Information

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