Method for forming semiconductor structure

TWI938109BActive Publication Date: 2026-09-01POWERCHIP SEMICON MFG CORP
View PDF 3 Cites 0 Cited by

Patent Information

Application Number
TW114143332
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-11-06
Publication Date
2026-09-01
Estimated Expiration
2045-11-05

Smart Images

  • Figure TWG2TB001909097_001
    Figure TWG2TB001909097_001
  • Figure TWG2TB001909097_002
    Figure TWG2TB001909097_002
  • Figure TWG2TB001909097_003
    Figure TWG2TB001909097_003
Patent Text Reader

Abstract

This disclosure provides a method for forming a semiconductor structure, comprising the following steps: providing a substrate; forming a first pattern on the top surface of the substrate; removing a portion of the substrate using the first pattern as a mask to form an isolation trench defining a plurality of active regions; and applying a hydrophobic treatment to the side surfaces of the isolation trench, such that the side surfaces of the isolation trench are first hydrophobic surfaces.
Need to check novelty before this filing date? Find Prior Art

Claims

1. A method for forming a semiconductor structure, comprising: Provide a base; A first pattern is formed on the top surface of the substrate; A portion of the substrate is removed using the first pattern as a mask to form an isolation trench defining a plurality of active regions; the side surfaces of the isolation trench are hydrophobically treated such that the side surfaces of the isolation trench are a first hydrophobic surface, wherein the hydrophobic treatment causes the surface of the first pattern to be a second hydrophobic surface; and the first pattern is removed by a wet etching process to expose the top surface of the substrate, wherein the top surface of the substrate is a hydrophilic surface.

2. The method as described in claim 1, wherein the first hydrophobic surface and the second hydrophobic surface are directly connected to each other.

3. The method of claim 1, wherein the hydrophobic treatment comprises a gas-phase treatment by introducing hexamethyldisilazane (HMDS).

4. The method as described in claim 1, wherein the hydrophobic treatment includes plasma treatment.

5. The method of claim 4, wherein the plasma treatment uses a source gas comprising F, H2, N2 or a combination thereof.

6. A method for forming a semiconductor structure, comprising: Provide a base; A first pattern is formed on the top surface of the substrate; A portion of the substrate is removed using the first pattern as a mask to form an isolation trench defining a plurality of active zones; the side surfaces of the isolation trench are hydrophobically treated such that the side surfaces of the isolation trench are a first hydrophobic surface, wherein the hydrophobic treatment includes plasma treatment using a source gas containing carbon tetrafluoride (CF4).

7. The method of claim 6, wherein the plasma treatment includes a source gas used for ashing treatment, the source gas comprising H2 and N2.

Citation Information

Patent Citations

  • Manufacturing method for fin body

    CN110838449A

  • Method of reducing pattern collapse in high aspect ratio nanostructures

    TW201140682A

  • Surface treatment agent for semiconductor substrate

    TW201324599A