Vertical ferroelectric field effect transistor and an array of memory strings thereof

Abstract

This invention provides a memory structure comprising a ring-channel ferroelectric memory transistor organized as horizontal NOR memory strings for random access. The NOR memory strings are formed over a semiconductor substrate in a plurality of scalable memory stacks of thin-film ferroelectric memory transistors. These three-dimensional memory stacks are fabricated in a process including forming vias in a multilayer film stack for forming local word line structures and forming slit trenches to divide the film stack into memory stacks including the local word line structures formed therein. The memory structure of the ring-channel ferroelectric memory transistor enables a scalable configuration for realizing a high-density, high-capacity memory device.

Description

Technical Field

[0001] This invention relates to high-density memory structures and methods for manufacturing the same. Specifically, it relates to a memory structure consisting of a three-dimensional NOR memory string formed using a ring-channel ferroelectric memory transistor. Furthermore, it relates to a vertical ring-channel ferroelectric field-effect transistor formed on a semiconductor substrate. [Cross-reference to related applications] [ ]

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 598,050, filed November 10, 2023, entitled "MEMORY STRUCTURE OF THREE-DIMENSIONAL NOR MEMORY STRINGS OF CHANNEL-ALL-AROUND FERROELECTRIC MEMORY TRANSISTORS AND METHOD OF FABRICATION" and U.S. Provisional Patent Application No. 63 / 512,894, filed July 10, 2023, entitled "MEMORY STRUCTURE OF THREE-DIMENSIONAL NOR MEMORY STRINGS OF CHANNEL-ALL-AROUND FERROELECTRIC MEMORY TRANSISTORS AND METHOD OF FABRICATION", which are incorporated herein by reference in their entirety. Prior Technology

[0003] NOR memory strings include storage transistors that share a common source region and a common drain region, wherein each storage transistor can be individually addressed and accessed. U.S. Patent 10,121,553 ('553 Patent), published November 6, 2018, entitled "Capacitive-Coupled Non-Volatile Thin-film Transistor NOR Strings in Three-Dimensional Arrays," discloses storage transistors (or memory transistors) organized as a three-dimensional array of NOR memory strings formed on a flat surface of a semiconductor substrate. The '553 Patent is hereby incorporated by reference in its entirety for all purposes. In the '553 Patent, the NOR memory string includes a large number of thin-film storage transistors sharing a common bit line and a common source line. Specifically, '553 patent discloses a NOR memory string comprising: (i) a common source region and a common drain region extending longitudinally in a horizontal direction; and (ii) gate electrodes for storing transistors, each extending vertically. In this specification, the term "vertical" refers to a direction orthogonal to the surface of the semiconductor substrate, and the term "horizontal" refers to any direction parallel to the surface of the semiconductor substrate. In a 3D array, NOR memory strings are disposed on multiple planes (e.g., 8 or 16 planes) above the semiconductor substrate, wherein the NOR memory strings on each plane are arranged in columns. For charge-trapping transistors, a charge storage film is used as the gate dielectric material to store data in each transistor. For example, the charge storage film may include a tunneling dielectric layer, a charge-trapping layer, and a barrier layer, which may be implemented as a multilayer comprising silicon oxide or oxynitride, silicon-rich nitride, and silicon oxide, arranged in this order and referred to as an ONO layer. An applied electric field across the charge storage membrane adds charge or removes charge from the charge trap in the charge trapping layer, thus changing the threshold voltage of the storage transistor to encode a given logic state in the storage transistor.

[0004] Advances in electrically scalable materials (“ferroelectric materials”), particularly for use in semiconductor manufacturing processes, have indicated new potential applications in ferroelectric memory circuits. For example, the paper “Ferroelectricity in Hafnium Oxide: CMOS compatible Ferroelectric Field Effect Transistors” (pp. 24.5.1–24.5.4), presented by TS Böscke et al. at the 2011 International Electron Devices Meeting (IEDM), reveals a ferroelectric field effect transistor (FeFET) using hafnium oxide as the gate dielectric material. By controlling the polarization direction in the ferroelectric gate dielectric layer, the FeFET can be programmed to have either of two threshold voltages. Each threshold voltage of the FeFET constitutes a state representing a specified logic value, such as a “programmed” state or an “erase” state. This FeFET has applications in high-density memory circuits. In another example, U.S. Patent No. 9,281,044, entitled "Apparatuses having a ferroelectric field-effect transistor memory array and related method," published by DV Nirmal Ramaswamy et al. on March 8, 2016, discloses a 3D array of FeFETs. Summary of the Invention

[0005] This disclosure discloses a memory structure and manufacturing method of a three-dimensional NOR memory string including a junctionless ferroelectric memory transistor, which is substantially shown and / or described below, for example, in conjunction with at least one of the figures, as more fully set forth in the claims.

[0006] In some specific examples, a three-dimensional memory structure formed above a flat surface of a semiconductor substrate includes: a plurality of memory stacks arranged along a first direction, each memory stack being separated from its directly adjacent memory stacks by trenches along the first direction; each memory stack and each trench extending in a second direction; the first and second directions being orthogonal to each other and substantially parallel to the flat surface of the semiconductor substrate; wherein each memory stack includes a plurality of active layers arranged in a third direction substantially orthogonal to the flat surface of the semiconductor substrate; each active layer includes layers arranged such that one is located at the other in the third direction. The above-mentioned method includes a first conductive layer and a second conductive layer separated by a first isolation layer, and each active layer is separated from its directly adjacent active layer by a second isolation layer along a third direction; and multiple local word line structures, which are configured as pillars formed in each memory stack and extending upward in a third direction. Each local word line structure is surrounded by the first conductive layer and the second conductive layer. Each local word line structure includes a concentric layer of an oxide semiconductor layer, a ferroelectric dielectric layer and a gate conductor layer, wherein the oxide semiconductor layer is disposed around the outer circumference of each pillar and is disposed between the first conductive layer and the second conductive layer and in contact with the first conductive layer and the second conductive layer. Each active layer in the memory stack forms a thin-film ferroelectric memory transistor array organized as NOR memory strings, and each memory transistor is formed at the intersection of the active layer and the local word line structure.

[0007] In another specific example, a method for fabricating a memory structure comprising a NOR memory string transistor above a flat surface of a semiconductor substrate includes: repeatedly depositing multiple layers and interlayer sacrificial layers alternately and in a manner one above the other to form a multilayer film stack, each multilayer including a first sacrificial layer and a second sacrificial layer and a first isolation layer located between the first sacrificial layer and the second sacrificial layer, the multilayer film stack extending in a first direction and a second direction, the first direction and the second direction being orthogonal to each other and substantially parallel to the flat surface of the semiconductor substrate, and the multilayer and interlayer sacrificial layers stacked upward in a third direction substantially orthogonal to the flat surface of the semiconductor substrate; forming a via array in the multilayer film stack, the via array extending upward through the multilayer and interlayer sacrificial layers in a third direction, the via array including a first via array formed in a memory array region; forming local word line structures in each of the first via arrays, including forming oxides in each of the first plurality of vias. A concentric layer of a semiconductor layer, a ferroelectric dielectric layer, and a gate conductor layer; trenches are formed in a multilayer film stack to divide the multilayer film stack into multiple memory stacks, each memory stack having a subset of local word line structures formed therein, each memory stack being separated from its directly adjacent memory stacks by one of the trenches along a first direction, each memory stack and each trench extending in a second direction, each memory stack including multiple layers and interlayer sacrificial layers disposed in a third direction; using a passage through the trenches, replacing the first and second sacrificial layers with a first and a second conductive layer, the first and second conductive layers contacting the oxide semiconductor layer of each local word line structure in each memory stack; using a passage through the trenches, removing the interlayer sacrificial layer to expose a portion of the oxide semiconductor layer formed on the outer circumference of the local word line structure formed in the first via array; and using a passage through the trenches, removing at least a portion of the exposed portion of the oxide semiconductor layer.

[0008] In some specific examples, an integrated circuit includes a vertical ferroelectric field-effect crystal formed above a flat surface of a semiconductor substrate, wherein the ferroelectric field-effect crystal includes: a gate conductor layer configured as pillars extending in a first direction substantially orthogonal to the flat surface of the semiconductor substrate; an annular ferroelectric dielectric layer formed adjacent to the pillars of the gate conductor layer; an annular oxide semiconductor layer formed adjacent to the annular ferroelectric dielectric layer; and a first conductive layer and a second conductive layer, each configured as a plane parallel to the flat surface of the semiconductor substrate. The first conductive layer and the second conductive layer are arranged along the first direction with one on top of the other and spaced apart by a first insulating layer. The first conductive layer and the second conductive layer surround the outer circumference of the annular oxide semiconductor layer and are in contact with the annular oxide semiconductor layer. The ferroelectric field-effect crystal is formed at the intersection of the first conductive layer, the second conductive layer and the annular oxide semiconductor layer. The first conductive layer forms the drain region and the second conductive layer forms the source region. The oxide semiconductor layer forms the junctionless channel region. The annular ferroelectric dielectric layer forms the gate dielectric layer and the gate conductor layer forms the gate electrode of the ferroelectric field-effect crystal.

[0009] In another specific example, a memory string array is provided, wherein each memory string includes a plurality of vertical ferroelectric crystals formed above a flat surface of a semiconductor substrate. Each ferroelectric crystal includes: a gate conductor layer configured as a pillar extending in a first direction substantially orthogonal to the flat surface of the semiconductor substrate; an annular ferroelectric dielectric layer formed adjacent to the pillar of the gate conductor layer; an annular oxide semiconductor layer formed adjacent to the annular ferroelectric dielectric layer; and a first conductive layer and a second conductive layer, each configured as a plane parallel to the flat surface of the semiconductor substrate, the first conductive layer and the second conductive layer being arranged along the first direction with one on top of the other and spaced apart by a first insulating layer, the first conductive layer and the second conductive layer surrounding the outer circumference of the annular oxide semiconductor layer and in contact with the annular oxide semiconductor layer. The ferroelectric field-effect crystal is formed at the intersection of the first conductive layer, the second conductive layer and the annular oxide semiconductor layer. The first conductive layer forms the drain region and the second conductive layer forms the source region. The oxide semiconductor layer forms the junctionless channel region. The annular ferroelectric dielectric layer forms the gate dielectric layer and the gate conductor layer forms the gate electrode of the ferroelectric field-effect crystal.

[0010] The details of these and other advantages, features and novel characteristics of the invention, as well as the specific examples illustrated herein, will be more fully understood from the following description and drawings. Simple Explanation of the Diagram

[0011] Various specific examples of the invention are disclosed in the following detailed description and accompanying drawings. Although the drawings depict various examples of the invention, the invention is not limited to the depicted examples. It should be understood that in the drawings, the same element symbols designate the same structural elements. Furthermore, it should be understood that the depictions in the drawings are not necessarily drawn to scale.

[0012] [Figure 1(a)], [Figure 1(b)] and [Figure 1(c) are perspective views of a memory structure comprising a three-dimensional array of ring-channel ferroelectric memory transistors including NOR memory strings in a specific embodiment of the present invention.

[0013] [Figure 1(d)] and [Figure 1(e)] are cross-sectional views of various parts of the memory structure of ferroelectric memory transistors in Figures 1(a) and 1(c) in some specific examples.

[0014] [Figure 2] is a transistor-level schematic diagram of a memory device including a three-dimensional array of NOR memory strings in a specific embodiment of the present invention.

[0015] [Figure 3(a)] and [Figure 3(b)] are cross-sectional views of the memory structure of Figures 1(a) and 1(c) in two different planes, including specific examples of the present invention.

[0016] [Figure 4(a)] and [Figure 4(b)] are unfolded perspective views of the memory structure shown in Figures 1(a) to 1(c) in a specific embodiment of the present invention.

[0017] [Figure 5] is a top view of a memory structure including a pre-charged transistor and a stepped structure in a specific embodiment of the present invention.

[0018] [Figure 6] is a cross-sectional view of the memory structure of Figure 5, including the pre-charged transistor and the stepped structure, in a specific embodiment of the present invention.

[0019] [Figure 7] is an unfolded cross-sectional view of a memory stack including a local character line structure in a specific embodiment of the present invention.

[0020] [Figure 8] is an unfolded cross-sectional view of a memory stack including a local character line structure in an alternative specific embodiment of the present invention.

[0021] [Figure 9(a)] and [Figure 9(b)] are unfolded cross-sectional views of a memory stack including a local character line structure in an alternative specific embodiment of the present invention.

[0022] [Figure 10] is a top view of a memory structure including a stepped structure connected to a common bit line and a common source line, according to a specific example of the present invention.

[0023] [Figure 11] is a cross-sectional view of the memory structure of Figure 10, which includes a stepped structure connected to a common bit line and a common source line, in a specific embodiment of the present invention.

[0024] [Figure 12] is a flowchart of a manufacturing process for forming a memory structure including a ring channel ferroelectric memory transistor in a specific example of the present invention.

[0025] Figures 13(a) through 13(n) (including 13(j1)) illustrate memory structures during intermediate process steps in the manufacturing process of Figure 12 in some specific examples.

[0026] [Figure 14] A cross-sectional view of the memory structure of a ring-channel ferroelectric memory transistor, including an alternative specific example of the present invention.

[0027] [Figure 15] is a top view of a memory structure including a stepped structure connected to a common bit line and a common source line, in an alternative specific embodiment of the present invention.

[0028] [Figure 16] is a cross-sectional view of the memory structure of Figure 15, which includes a stepped structure connected to a common bit line and a common source line, in a specific embodiment of the present invention.

[0029] [Figure 17(a)] and [Figure 17(b)] are respectively a top view and a cross-sectional view of a memory structure including a single-layer global character line in some specific examples.

[0030] [Figure 18(a)] and [Figure 18(b)] are respectively a top view and a cross-sectional view of a memory structure including a double-layer global character line in some specific examples.

[0031] [Figure 19(a)], [Figure 19(b)] and [Figure 19(c)] are respectively a top view, a cross-sectional view and an unfolded cross-sectional view of the memory structure including the top-bottom layer of the global character line in some specific examples.

[0032] [Figures 19(d)] to [Figures 19(k)] are cross-sectional views of the memory structures shown in Figures 19(a) to 19(c) in some specific examples illustrating the manufacturing process used to form the top-bottom layer of the global character line.

[0033] [Figure 20(a)] and [Figure 20(b)] illustrate some specific examples of using single-mask, single-exposure photolithography to pattern the column openings in a hard mask layer.

[0034] [Figure 21(a)] and [Figure 21(b)] illustrate some specific examples of using double masking, double exposure photolithography to pattern the column openings in a hard mask layer.

[0035] [Figure 22] illustrates some specific examples of the application of the memory device of the present invention as an embedded memory device.

[0036] [Figure 23] illustrates the detailed structure of the memory transistor formed in the memory structure in an alternative specific example of the present invention. Implementation

[0037] In a specific embodiment of the present invention, the memory structure includes a ring-channel ferroelectric memory transistor organized as horizontal NOR memory strings for random access. The NOR memory strings are formed over a semiconductor substrate within a plurality of scalable memory stacks of thin-film ferroelectric memory transistors. The three-dimensional memory stack is fabricated in a process including forming holes for forming local word line structures and forming slit trenches in a multilayer film stack to divide the film stack into memory stacks including the local word line structures formed therein. The memory structure of the ring-channel ferroelectric memory transistor enables scalable constructions for high-density, high-capacity memory devices.

[0038] In some specific examples, the ferroelectric memory transistor is a thin-film ferroelectric field-effect transistor (FeFET) having a ferroelectric polarization layer as the gate dielectric layer. The ferroelectric polarization layer (also referred to as the "ferroelectric gate dielectric layer" or "ferroelectric dielectric layer") is formed adjacent to an oxide semiconductor layer serving as the channel region. The ferroelectric memory transistor includes a source region and a drain region, both formed of a metallic conductive material in electrical contact with the oxide semiconductor channel region. The resulting ferroelectric memory transistors are each junctionless transistors without p / n junctions in the channel, where the threshold voltage is modulated by the polarization of the mobile carriers in the ferroelectric polarization layer. In the memory structure of this invention, the ferroelectric memory transistors in each NOR memory string are individually controlled by a gate electrode to allow each memory transistor to be individually addressed and accessed. In some specific examples, the ferroelectric polarization layer is formed of a hafnium oxide-doped material, and the oxide semiconductor channel region is formed of an amorphous metal oxide semiconductor material.

[0039] In this specification, the term "storage transistor" is used interchangeably with "memory transistor" to refer to the transistor device formed in the memory structure described herein. In some examples, the memory structure disclosed herein, including a NOR memory string and a random-access memory transistor (or storage transistor), can be used as main memory in a computing system, wherein the memory location can be directly accessed by the processor of the computer system, for example, by conventional random-access memory (RAM) (such as dynamic RAM (DRAM) and static RAM (SRAM)) in the prior art. For example, the memory structure of the present invention can be applied in a computing system to act as random access memory to support the operation of microprocessors, graphics processors, and artificial intelligence processors. In other examples, the memory structure disclosed herein is also suitable for forming storage systems, such as solid-state drives, or replacing hard disk drives, for providing long-term data storage in a computing system.

[0040] In the description of this invention, the term "oxide semiconductor layer" (sometimes also referred to as "semiconductor oxide layer" or "metal oxide semiconductor layer") as used herein refers to a thin-film semiconductor material made of conductive metal oxides (such as zinc oxide and indium oxide) or any suitable conductive metal oxide having charge carriers having mobility that can be altered or modulated by suitable formulations or by including suitable impurities.

[0041] In this description of the invention, for ease of reference to the figures, a Cartesian coordinate reference frame is used, wherein the Z direction is orthogonal to the flat surface of the semiconductor substrate, and the X and Y directions are orthogonal to the Z direction and to each other, as indicated in the figures. Furthermore, the figures provided herein are idealized representations for illustrating specific examples of the invention and are not intended to be actual views of any particular component, structure, or device. The figures are not drawn to scale, and for clarity, the thickness and dimensions of some layers may be enlarged. Variations in the shapes depicted are expected. For example, areas depicted as box shapes may typically have rough and / or non-linear characteristics. Acute angles depicted may be rounded. The same numbers throughout refer to the same components or elements.

[0042] Figures 1(a), 1(b), and 1(c) are perspective views of a three-dimensional array of ferroelectric memory transistors (FCMTs) comprising NOR memory strings, according to specific embodiments of the present invention. Figures 1(d) and 1(e) are cross-sectional views of various portions of the memory structures of Figures 1(a) and 1(c) illustrating ferroelectric memory transistors in some specific embodiments. For simplicity, the memory structure in Figure 1(b) is shown with the dielectric layer omitted to illustrate the ferroelectric memory transistor elements in the three-dimensional structure.

[0043] Referring to Figures 1(a) and 1(b), the memory structure 10 includes memory stacks 17 formed on a semiconductor layer 12 (sometimes referred to as a semiconductor substrate), wherein each memory stack includes a plurality of NOR memory strings formed in a vertical direction with one on top of the other. An insulating layer 14 may be disposed between the semiconductor substrate 12 and the memory stacks. Each memory stack 17 is separated from its directly adjacent memory stack in the X direction by a trench 19, also referred to herein as a "slit trench". The slit trench 19 is a narrow trench with a width in the X direction much smaller than the width of the memory stack 17. In some specific embodiments, the memory stacks of NOR memory strings are formed by groups of thin films continuously deposited on a flat surface of the semiconductor substrate 12, each group of thin films referred to herein as an active layer 16. The active layers 16 in each memory stack of the NOR memory string are configured to be one on top of the other, and each active layer 16 is separated from adjacent active layers by an interlayer isolation layer 15. The interlayer isolation layer 15 may be a dielectric layer or may be implemented as an air gap isolation layer. In some specific examples, the interlayer isolation layer 15 is an oxygen-containing dielectric layer. Each active layer 16 includes a common drain line (or bit line) 22 and a common source line (or source line) 24 configured to be spaced apart in the vertical direction (Z direction) by a channel spacer isolation layer 23. The common drain line 22 and common source line 24 in each active layer 16 extend in the horizontal Y direction to form the memory transistors of the NOR memory string. The memory transistors in each NOR memory string share the bit line 22 (common drain line) and the source line 24 (common source line).

[0044] In a specific embodiment of the present invention, pillar-shaped local word line structures 13 are formed in each memory stack and extend through the memory stack in the Z direction. When configured in this way, each local word line structure 13 is surrounded by bit lines 22 and source lines 24. Each pillar-shaped local word line structure 13 includes a concentric layer of a channel layer, a ferroelectric gate dielectric layer, and a gate conductor layer, formed from the outer circumference of the pillar to its inner center. In some specific embodiments, the interface layer may optionally be formed as a concentric layer between the channel layer and the ferroelectric gate dielectric layer. In a specific embodiment of the present invention, the channel layer is an oxide semiconductor layer.

[0045] In a specific embodiment of the invention, the annular channel layer 26 is separated between adjacent active layers 16. That is, the channel layer 26 is disposed along each local character line structure 13 in each active layer 16 between the bit line 22 and the source line 24 of each active layer 16 and is in contact with the bit line 22 and the source line 24. The channel layer 26 is not present in the region of the interlayer isolation layer 15 or is at least partially removed in the region of the interlayer isolation layer 15 to separate the channel layers between adjacent active layers 16. In the region of the interlayer isolation layer 15, the exposed layer of the local character line structure 13 may be an interface layer 25 (if used), as shown in Figures 1(a) and 1(b). Alternatively, if the local character line structure 13 does not include an interface layer or if an optional interface layer is completely or partially removed during the channel layer removal process, the exposed layer of the local character line structure 13 in the interlayer isolation layer 15 is a ferroelectric gate dielectric layer. The presence or absence of the interface layer 25 in the interlayer isolation region is not important for practicing this invention. In an alternative specific embodiment, the ferroelectric gate dielectric layer is also at least partially removed between adjacent active layers 16. At least partially removing the ferroelectric gate dielectric layer in the region of the interlayer isolation layer 15 has the effect of restricting the lateral migration of polarization regions between memory transistors on adjacent planes in the memory stack, or restricting the migration of oxygen atoms between adjacent active layers.

[0046] In this configuration, the channel layer 26 of the memory transistor is a ring-shaped layer formed on the circumference outside the local word pillar to realize a ring-shaped channel transistor structure. The bit line 22 (common drain line) and source line 24 (common source line) surround and contact the ring-shaped channel layer 26. The ring-shaped channel layer is formed adjacent to the ferroelectric gate dielectric layer and is also formed as a ring. The inner central portion of the local word pillar is the gate conductor layer. In the case of an interface layer, the interface layer is another ring-shaped layer formed between the ring-shaped channel layer and the ring-shaped ferroelectric gate dielectric layer. Ferroelectric memory transistors are formed at the intersection points of the active layer 16 and the local word line structure 13. Therefore, in each memory stack 17, the memory transistors are formed in multiple parallel planes of the memory stack in the vertical direction. In each active layer 16 of the memory stack 17, memory transistors 20 are formed at the intersection points of the common source line and the common drain line with the local word line structure to form memory strings. As mentioned above, the term "vertical" refers to a direction orthogonal to the surface of the semiconductor substrate, and the term "horizontal" refers to any direction parallel to the surface of the semiconductor substrate.

[0047] Figure 1(d) illustrates the detailed structure of a memory transistor 20 formed in the memory structure 10 of Figures 1(a) and 1(b) in some specific examples. Specifically, Figure 1(d) shows a pair of memory transistors 20-1 and 20-2 in two adjacent planes of the memory stack 17. Referring to Figure 1(d), the memory transistor 20 includes a first conductive layer 22 forming bit lines (or common drain lines) and a second conductive layer 24 forming source lines (or common source lines), these conductive layers being separated by channel spacer layers 23. The memory transistor 20 further includes an annular channel layer 26 formed vertically along the sidewalls of local word line pillars and in contact with the first conductive layer 22 and the second conductive layer 24. An annular ferroelectric gate dielectric layer 27 and a gate conductor layer 28 are formed adjacent to the annular channel layer 26. Specifically, a portion of the annular channel layer 26 is disposed in the XY plane between the bit line 22 and the annular ferroelectric gate dielectric layer 27; and a portion of the annular channel layer 26 is disposed in the XY plane between the source line 24 and the annular ferroelectric gate dielectric layer 27. In a specific embodiment of the invention, an annular interface layer 25 is disposed between the channel layer 26 and the ferroelectric gate dielectric layer 27. The memory transistor 20 is isolated from adjacent memory transistors in the stack by an interlayer isolation layer 15. When configured in this way, memory transistors sharing a common source line and a common bit line along each active stripe (in the Y direction) form a NOR memory string (also referred to herein as a "horizontal NOR memory string" or "HNOR memory string").

[0048] In the specific examples shown in Figures 1(a), 1(b), and 1(d), the interlayer isolation layer 15 is implemented as air gap isolation. For example, air gap isolation is implemented by forming an air gap liner 15b on the exposed surface of the interlayer isolation region between active layers, wherein the remaining air gap cavities 15a remain unfilled to form air gap isolation. The air gap liner 15b may be a silicon oxide layer, a silicon nitride layer, or other suitable dielectric layer. Furthermore, in the specific example shown in Figure 1(a), air gap isolation is also formed in slot trenches 19 between adjacent memory stacks 17. In the specific example shown in Figure 1(a), the air gap isolation between adjacent memory stacks 17 includes a dielectric liner 36 that liner the sidewalls of the slot trenches 19 and covers the openings of the interlayer isolation layer 15. Next, a nonconformal dielectric layer 38 is deposited to form a cap on the top of the slit trench 19, thereby enclosing the cavities of each slit trench to form an air gap isolation. In some specific examples, the dielectric layer 38 is a nonconformal deposited silicon dioxide (SiO2) layer.

[0049] In alternative specific examples, the memory structure can be formed using a dielectric-filled isolation layer instead of an air gap isolation layer. Figure 1(c) illustrates a memory structure 10a constructed in a similar manner to the memory structure 10 of Figure 1(a), but using a dielectric-filled isolation layer. Referring to Figure 1(c), in the memory structure 10a, the interlayer isolation layer 15 is formed as a dielectric layer. In some specific examples, the interlayer isolation layer 15 is an oxygen-containing dielectric layer. In one example, the interlayer isolation layer 15 is a silicon dioxide layer. Figure 1(e) illustrates the detailed construction of the memory transistor 20 formed in the memory structure 10a of Figure 1(c) in some specific examples. Except for the interlayer isolation layer 15 formed as a dielectric layer or a dielectric-filled layer, the memory transistor 20 in Figure 1(e) is constructed in a similar manner to the memory transistor 20 in Figure 1(d).

[0050] Furthermore, in the specific example shown in Figure 1(c), the memory structure 10a includes a slot trench 19 filled with a dielectric layer 39 to provide isolation between adjacent memory stacks 17. In an alternative specific example, the memory structure 10a may have a dielectric-filled interlayer isolation layer 15 and use air gap isolation for the slot trench 19. More specifically, the memory structure of the present invention may be implemented using a series of isolation elements or materials between active layers and between active stacks to achieve the desired isolation of the memory transistors formed therein.

[0051] In the specific examples shown in Figures 1(d) and 1(e), the interlayer isolation layer 15 is shown to extend to the ferroelectric gate dielectric layer 27. As described above, the exposed layer of the local character line structure in the region of the interlayer isolation layer 15 may be the interface layer 25 (if used). In other specific examples, the exposed layer of the local character line structure in the interlayer isolation layer 15 may be the ferroelectric gate dielectric layer. The interface layer 25 (if used) may be completely or partially removed in the interlayer isolation region.

[0052] In a specific embodiment of the present invention, the memory transistor in the NOR memory string is a ferroelectric field-effect transistor (FeFET), which includes a ferroelectric thin film as a gate dielectric layer, also referred to as a ferroelectric polarization layer, ferroelectric gate dielectric layer, or ferroelectric dielectric layer. In a ferroelectric field-effect transistor (FeFET), the polarization direction in the ferroelectric gate dielectric layer is controlled by an electric field applied between the transistor drain terminal (bit line 22) and the transistor gate electrode (gate conductor 28), wherein the change in polarization direction alters the threshold voltage of the FeFET. In some specific embodiments, the electric field is applied relative to both the transistor drain terminal and the source terminal. For example, the FeFET can be programmed to have either of two threshold voltages, wherein each threshold voltage of the FeFET can be used to encode a given logic state. For example, the two threshold voltages of the FeFET can be used to encode a "programmed" state and an "erase-encoded" state, each representing a specified logic value. In one example, programmed states are associated with higher threshold voltages, and erased states are associated with lower threshold voltages. In some specific instances, more than two threshold voltages can be established to represent more than two memory states at each FeFET.

[0053] Referring again to Figures 1(a) and 1(b), in a specific embodiment of the present invention, each memory stack 17 includes local word line structures 13 configured as a two-dimensional array in the XY plane. Specifically, the local word line structures 13 are configured as two rows extending and intersecting in the Y direction. Memory transistors 20 are formed at each intersection point of the bit lines 22 / source lines 24 and the local word line structures 13. When configured in this way, in each active layer 16 of the memory stack 17, the bit lines 22 / source lines 24 intersect with multiple local word line structures 13 in the memory stack to form ferroelectric memory transistors 20 of NOR memory strings. The local word line structures 13 intersect with the active layers 16 in multiple planes to form NOR memory strings in multiple planes of the memory structure. When configured in this way, a three-dimensional array of NOR memory strings is formed to achieve a high-density and high-capacity memory structure. In each memory stack 17, each local word line structure 13 is connected to a separate global word line 30 extending in the X direction. Therefore, each memory transistor 20 in the NOR memory string is coupled to a different global word line 30. In operation, a global word line 30 is activated to select a local word line structure 13 in the memory string, and a bit line 22 is selected to access a memory transistor from a plurality of active layers 16 in the memory stack.

[0054] In the examples shown in Figures 1(a) and 1(b), memory structure 10 is illustrated as two memory stacks separated by slot trenches 19: memory stack 0 and memory stack 1. Referring to Figure 1(b), the memory stacks are illustrated as including two active layers: active layer 0 including bit lines BL0 and SL0, and active layer 1 including bit lines BL1 and SL1. Active layer 0 and active layer 1 are separated by an interlayer isolation layer 15. In the example shown in Figure 1(b), each memory stack is illustrated as having four local word line structures 13. For memory stack 0, four local word line structures LWL0-0, LWL1-0, LWL2-0, and LWL3-0 are provided. For memory stack 1, four local word line structures LWL0-1, LWL1-1, LWL2-1, and LWL3-1 are provided. In each memory stack, each local character line structure 13 is connected to a separate global character line 30. That is, the local character line structures LWL0-x, LWL1-x, LWL2-x, and LWL3-x are connected to different global character lines, so that by activating each global character line, only one local character line structure in the memory stack is selected at a time. In this embodiment of the invention, four global character lines 30 are configured and extend in the X direction: GWL0, GWL1, GWL2, and GWL3. Global character line GWL0 is connected to local character lines LWL0-0 and LWL0-1. Global character line GWL1 is connected to local character lines LWL1-0 and LWL1-1. Global character line GWL2 is connected to local character lines LWL2-0 and LWL2-1. Global character line GWL3 is connected to local character lines LWL3-0 and LWL3-1. When configured in this way, each global character line selects one local character line structure in each memory stack. In a specific embodiment of the invention, in order to facilitate the connection between each local character line structure and each individual global character line, the arrays of pillar-shaped local character line structures in each memory stack are formed in an interleaved configuration in the Y direction, so that each global character line is connected to only one local character line structure in the memory stack.

[0055] In the illustration shown in Figure 1(b), via 29 is used to illustrate the connection between the local character line structure and the individual global character lines, with the darkened top cover illustrating the connection formed between the local character line structure and the global character lines. Via 29 is illustrative only and is not intended to represent an actual physical element of the memory structure. In some specific examples, the global character lines 30 are formed using a dummy process, and the global character line material is in contact with the exposed gate conductor layer in the top portion of the local character line structure.

[0056] In a specific embodiment of the present invention, the memory transistors 20 in the memory structure 10 are junctionless ferroelectric memory transistors. Therefore, each memory transistor 20 includes only conductive layers as source and drain regions, without any semiconductor layers. The bit-line conductive layer and source-line conductive layer are formed using a low-resistivity metallic conductive material. In some specific embodiments, the bit-line conductive layer and source-line conductive layer are metal layers, such as a tungsten (W) layer lined with titanium nitride (TiN), a tungsten (W) layer lined with tungsten nitride (WN), a molybdenum (Mo) layer lined with molybdenum nitride (MoN), or an unlined tungsten layer, molybdenum layer, or cobalt layer, or other metal layers. The channel spacer isolation layer 23 between the first conductive layer and the second conductive layer can be a dielectric layer, such as silicon dioxide (SiO2), and is sometimes referred to herein as the "channel spacer dielectric layer". The channel layer 26 is an oxide semiconductor layer. In some examples, channel layer 26 is formed using amorphous oxide semiconductor materials, such as indium gallium zinc oxide (InGaZnO or IGZO), indium zinc oxide (IZO), indium tungsten oxide (IWO), or indium tin oxide (ITO), or other such oxide semiconductor materials. Oxide semiconductor channel regions offer the advantage of high mobility for greater switching efficiency without the need to consider electron or electrical tunneling. For example, depending on the relative composition of indium, gallium, zinc, and oxygen, IGZO films have electron mobilities ranging from 10.0 to 100.0 cm² / V.

[0057] To form a ferroelectric memory transistor, the memory transistor 20 includes a ferroelectric polarization layer in contact with the channel layer. The ferroelectric polarization layer (or "ferroelectric dielectric layer") acts as the storage layer of the memory transistor. In some specific examples, an interface layer 25 may be disposed between the oxide semiconductor channel layer and the ferroelectric polarization layer. The interface layer is a thin layer and may be 0.5 nm to 3.0 nm thick. In some specific examples, the interface layer is formed using a material with a high dielectric constant (K) (also referred to as a "high-K" material). In some specific examples, the interface layer 25 may be a silicon nitride (Si3N4) layer, a silicon oxynitride layer, or an aluminum oxide (Al2O3) layer. In one example, when the ferroelectric polarization layer has a thickness of 4 to 5 nm, the interface layer (if present) may have a thickness of 1.5 nm. The inclusion of the interface layer 25 in Figures 1(a) to 1(e) is illustrative only and is not intended to be limiting. Interface layer 25 is optional and may be omitted in other embodiments of the invention. In other embodiments, interface layer 25 (when included) may be formed as a multilayer of different dielectric materials. In the description of the invention, a material having a high dielectric constant or "high-K material" refers to a material with a dielectric constant greater than that of silicon dioxide or greater than 3.9.

[0058] In some specific examples, the ferroelectric polarization layer is formed of a doped hafnium oxide material such as zirconium-doped hafnium oxide (HfZrO or "HZO"). In other specific examples, the hafnium oxide may be doped with silicon (Si), iridium (Ir), or lanthanum (La). In some specific examples, the ferroelectric polarization layer is a material selected from: zirconium-doped hafnium oxide (HZO), silicon-doped hafnium oxide (HSO), aluminum-zirconium-doped hafnium oxide (HfZrAlO), aluminum-doped hafnium oxide (HfO2:Al), lanthanum-doped hafnium oxide (HfO2:La), hafnium oxyzirconium oxynitride (HfZrON), hafnium-zirconium aluminum oxide (HfZrAlO), and any hafnium oxide including zirconium impurities.

[0059] The ferroelectric polarization layer is an annular layer that contacts the channel layer on its outer circumference and the gate conductor layer on its inner circumference. In some specific examples, the gate conductor layer includes a conductive liner and a low-resistivity conductor. The conductive liner may serve as an adhesive layer for the gate conductor layer. In some examples, the conductive liner is a titanium nitride (TiN) layer, a tungsten nitride (WN) layer, or a molybdenum nitride (MoN) layer, and the conductor is formed using tungsten, molybdenum, or other metals. In some cases, a conductive liner is not required, and the gate conductor layer only includes a low-resistivity conductor, such as a tungsten or molybdenum layer without a liner. In other examples, the gate conductor layer may be a heavily doped n-type or p-type polycrystalline silicon layer, which can be used with or without a conductive liner. The gate conductor layer forms the control gate electrode of the memory transistor and acts as a local word line in the memory structure. In some specific instances, the gate conductor layer is a heavily doped N+ or heavily doped P+ polycrystalline silicon layer, in which the heavily doped polycrystalline silicon layer affects the work function of the global word line and thus also shifts the threshold voltage of the ferroelectric memory transistor.

[0060] When constructed in this way, the oxide semiconductor channel layer 26 forms an N-type unipolar channel region, in which the bit line / source line conductive layers 22, 24 forming the drain and source terminals directly contact the channel region. The resulting ferroelectric memory transistor is a depletion-mode device, in which the transistor is normally on (i.e., conductive) and can be turned off (i.e., non-conductive) by depleting the N-type carriers in the channel region. The threshold voltage of the ferroelectric memory transistor varies with the thickness of the annular oxide semiconductor channel layer 26 in the XY plane. That is, the threshold voltage of the ferroelectric memory transistor is the voltage required to deplete the carriers within the thickness of the oxide semiconductor channel region to turn off the ferroelectric memory transistor. In a specific embodiment of the invention, the ferroelectric memory transistor has a channel length in the Z direction between the bit line 22 and the source line 24, defined by a channel spacer isolation layer 23. Furthermore, in a specific embodiment of the invention, the ferroelectric memory transistor has a channel width defined by the circumference of the annular channel layer 26.

[0061] In a specific embodiment of the present invention, a three-dimensional array of ferroelectric memory transistors in a NOR memory string can be applied to implement non-volatile memory devices or quasi-volatile memory devices. For example, quasi-volatile memory has an average retention time greater than 100 ms, such as about 10 minutes or several hours, while non-volatile memory devices can have a minimum data retention time of more than 5 years. As quasi-volatile memory, the ferroelectric memory transistor 20 may need to be updated from time to time to restore the desired programmed polarization state and erased polarization state. For example, the ferroelectric memory transistor 20 in memory structure 10 may be updated every few minutes or hours. In particular, the ferroelectric memory transistors of this disclosure can form quasi-volatile memory devices, wherein the update interval can be about several hours, which is significantly longer than the update interval of DRAM, which requires more frequent updates (such as within tens of milliseconds).

[0062] A key feature of the ferroelectric memory transistor 20 is that it can have extremely short channel lengths. This allows for increased voltage separation between different threshold voltages and thus enables large memory windows, while simultaneously allowing the memory structure 10 to be fabricated to achieve short channel lengths without the need for expensive lithography techniques. Specifically, the channel length of the ferroelectric memory transistor 20 is determined by the thickness L1 of the channel spacer dielectric layer 23 (Figures 1(b), 1(d), and 1(e)). The thickness L1 can be precisely controlled during the deposition of sublayers forming the initial thin film stack. The ability to control the thickness L1 of the dielectric layer 23 along with extremely low channel leakage of the oxide semiconductor channel layer via the deposition process makes it possible to provide ferroelectric memory transistors 20 with extremely short channel lengths (e.g., 5 nm) without employing expensive lithography techniques, such as the extreme ultraviolet (EUV) scanners required for short channels in patterned planar transistors. In some specific instances, the channel length L1 of the memory transistor 20 can be between 5 nm and 20 nm, or between 5 and 7 nm.

[0063] Another advantage of the extremely short channels achieved in the memory transistor of this invention is that, during memory programming or erasure operations, the scattered electric fields at the source-channel intersection and drain-channel intersection can overlap, resulting in rapid programming or erasure of the entire length of the channel corresponding to the polarization or depolarization of the ferroelectric dielectric layer. This has the effect of forming a wide memory operation window. More specifically, in the case of short channel lengths, the ferroelectric memory transistor is operated such that the applied voltage and scattered field cause the ferroelectric gate dielectric layer to polarize across the entire channel. Alternatively, a wide memory operation window can be utilized by operating programming and erasure operations with only partial polarization or partial depolarization to reduce stress on the oxide semiconductor layer of the ferroelectric memory transistor. In this invention description, partial polarization refers to biasing a ferroelectric memory transistor to achieve a polarization level in the ferroelectric dielectric layer between a positive and negative polarization state, associated with the respective erased and programmed states of the ferroelectric memory transistor. In this invention description, the term "polarization state" is used herein to refer to the polarization direction of the ferroelectric dielectric layer, which can be a positive or negative polarization state, such as associated with the erased or programmed states of the ferroelectric memory transistor. Furthermore, in this invention description, the term "polarization level" refers to different amounts of polarization achieved in the ferroelectric dielectric layer, which are related to different threshold voltage values ​​induced by polarization. In a specific embodiment of the invention, the ferroelectric memory transistor can generate threshold voltage values ​​within the full memory window capability of the ferroelectric memory transistor by operating a bias voltage that induces only partial polarization. In other specific examples, the wide memory window of the memory transistor enables lower voltage operations for programming and erasing operations, thereby reducing stress on the ferroelectric memory transistor and increasing durability.

[0064] Another prominent feature of the ferroelectric memory transistor 20 is that it has a large channel width to increase the transistor's "on" current without increasing the chip size of the memory structure. The channel layer of the memory transistor is formed as a ring layer on the circumference outside the cylindrical local word line structure. For memory transistors with sidewall channel layers of similar planar dimensions, the ring-shaped channel layer provides a channel width nearly four times larger than that of sidewall channels of the same size. The larger "on" current on the memory transistor helps compensate for the larger bit line capacitance that can be caused by the increased channel width.

[0065] In a specific embodiment of the present invention, the memory structure includes a memory array portion constructed as described above to form a three-dimensional array of NOR memory strings. To complete the memory device, the memory structure includes a stepped portion disposed at the end (in the Y direction) of the memory string. Thin-film memory transistors of the NOR memory string are formed in the memory array portion, and the stepped portion on the opposite side of the array portion includes a stepped structure to provide connections through conductive vias to the common bit lines and, if necessary, common source lines of the NOR memory string. In some specific embodiments, the common source line is pre-charged during programming, read, and erase operations to act as a virtual voltage reference source, thereby avoiding the need for continuous electrical connections to the supporting circuitry during such operations. In the description of the present invention, the common source line is described as electrically floating to indicate the absence of continuous electrical connections to the common source line. In a specific embodiment of the present invention, various processing steps for forming a stepped structure in the memory structure can be used. The processing steps used to form the ladder structure can precede, follow, or overlap with the processing steps used to form the memory array portion.

[0066] Figures 1(a) to 1(c) illustrate the construction of a memory array comprising a three-dimensional array of NOR memory strings. In Figures 1(a) and 1(c), memory structure 10 is shown as having two memory stacks, eight active layers, and five local word lines. In Figure 1(b), for simplicity, memory structure 10 is shown as having two memory stacks, two active layers, and four local word lines. Figures 1(a) to 1(c) are illustrative only and are not intended to be limiting. In practice, the memory structure may include 8, 16, 20, or more active layers, 1,000 to 2,000 memory stacks, and 2,000 to 4,000 local word lines. For example, memory structure 10 / 10a may have a suitable number of active layers, memory stacks, and local word line structures to form a modular memory cell of 64 million memory transistors, representing 64Mb of data. Memory structure 10 can be used as a building block for forming a high-capacity, high-density memory device. In a specific embodiment of the invention, memory structure 10 / 10a represents a modular memory cell referred to as a "tile," and the memory device is formed using an array of modular memory cells. In an exemplary embodiment, the memory device is organized as a two-dimensional array of tiles arranged along the X and Y directions, wherein each tile comprises a three-dimensional array of ferroelectric memory transistors, wherein support circuitry for each tile is formed beneath each tile. More specifically, the memory device comprises a plurality of memory arrays of thin-film ferroelectric memory transistors, which are organized as a two-dimensional array of "tiles" formed on a planar semiconductor substrate (i.e., the tiles are arranged in columns and rows). Individual tiles can be configured for individual and independent addressing, or larger memory segments (e.g., rows of tiles or 2D blocks of tiles) can be created and configured for collective addressing. In some examples, rows of tiles ("tile rows") can be configured to form operational units called "memory groups." A group of memory groups then forms a "memory group cluster." In this configuration, memory groups within a memory group can share data input and output buses in a multiplexing manner. Alternatively, the memory device may include a large tile array that is accessed individually to maximize tile access frequency and minimize tile access conflicts, thereby increasing memory access bandwidth. When configured in this way, tiles are modular units that allow flexible configuration of memory modules to meet application requirements.

[0067] Figure 2 is a transistor-level schematic diagram of a memory device comprising a three-dimensional array of NOR memory strings according to a specific embodiment of the present invention. In some specific embodiments, the memory device of Figure 2 is constructed using one of the memory structures of Figures 1(a) to 1(e). That is, the memory device of Figure 2 is constructed using the ring-channel ferroelectric memory transistors described in Figures 1(a) to 1(e). Referring to Figure 2, the memory device 200 includes a plurality of NOR memory strings organized into a three-dimensional array to form a high-density memory structure. The three-dimensional array of NOR memory strings is organized into a stack 215 of NOR memory strings 212, wherein the NOR memory strings 212 are formed such that one is on top of another in a third direction (e.g., the Z direction). In Figure 2, three memory stacks 215 are shown: stack 0, stack 1, and stack 2. The three-dimensional array of NOR memory strings is also organized as a series of NOR memory strings arranged in a first direction (e.g., the X direction) of the forming plane, wherein the series of NOR memory strings are arranged in one or more parallel planes extending upward in a third direction. Each memory string 212 includes a series of memory transistors 202 organized in a NOR configuration, wherein the memory transistors are connected in parallel between each other between a common bit line 204 and a common source line 206. Memory transistors are formed in horizontal NOR memory strings (also referred to as "HNOR memory strings") extending in a second direction (e.g., the Y direction). In a specific embodiment of the invention, the memory transistor 202 is a thin-film ferroelectric field-effect transistor (referred to herein as a "ferroelectric memory transistor"). Furthermore, in some specific embodiments, the memory transistor 202 is a junctionless ferroelectric memory transistor with oxide semiconductor channels formed thereon.

[0068] Each ferroelectric memory transistor 202 in each memory string includes a drain terminal coupled to each bit line BLx (e.g., BL0, BL1, BL2...) and a source terminal coupled to each source line SLx (e.g., SL0, SL1, SL2...). The ferroelectric memory transistors 202 in memory string 212 are thus connected in parallel to a common bit line 204 and a common source line 206, thereby forming a NOR memory string. Each ferroelectric memory transistor 202 in each memory string further includes a gate terminal coupled to each word line WLx (e.g., WL0, WL1, WL2...). Ferroelectric memory transistors 202 vertically aligned across several memory strings in the memory stack 215 are connected to a common word line 208, referred to herein as local word line 208. Local character lines 208 that cross the horizontally aligned memory transistor in the first direction (X direction) are connected to common global character lines GWLx (e.g., GWL0, GWL1, GWL2, etc.).

[0069] In some specific instances, the common source line 206 is electrically floating (i.e., without a continuous electrical connection), and a pre-charged transistor (not shown) is used to apply a source voltage from the common bit line. For example, one or more pre-charged transistors are positioned across the common bit line and the common source line. A voltage is applied to the common bit line, and the pre-charged transistors are turned on to electrically short-circuit the common bit line to the common source line, thereby charging the common source line to the voltage on the common bit line. The pre-charged transistors are then turned off, and the voltage on the common source line is maintained by the charge in associated capacitors ("virtual ground"), such as the parasitic capacitance of the common source line. In other specific instances, both the common bit line 204 and the common source line 206 are electrically biased or driven by hard-wired connections via control circuitry associated with the memory device 200. Implementing an electrically floating source line has the advantage of eliminating hard-wired connections, thus reducing congestion of connector wires that may be required in the stepped structure (not shown) of a three-dimensional array.

[0070] As described herein, ferroelectric memory transistors offer high endurance, long data retention, and relatively low voltage operation for erase (e.g., at a gate-to-source voltage of 3.0 volts) and programmable (e.g., at a gate-to-source voltage of -3.0 volts). By combining ferroelectric or polarization characteristics with a three-dimensional structure (e.g., thin-film NOR memory strings as described herein), the memory devices of the ferroelectric memory transistors of this invention achieve the additional benefits of high-density, low-cost memory arrays, as well as the advantage of high-speed, random-access memory circuitry with low read latency.

[0071] In a specific embodiment of the present invention, a three-dimensional array of NOR memory strings in memory device 200 is formed on a semiconductor layer, also known as a semiconductor substrate. To complete the memory circuitry, various types of circuit systems can be formed in or on the surface of the semiconductor substrate to support the operation of the NOR memory strings formed on the semiconductor substrate. Such memory control circuitry is called "circuit under array" (CuA) and may include digital and analog circuit systems such as decoders, drivers, sense amplifiers, sequencers, state machines, logic gates, memory caches, multiplexers, voltage level shifters, voltage sources, latches and registers, and connectors, which perform repetitive local operations, such as processing random addresses and executing boot, erase, program, read, and update commands via the memory array formed above the semiconductor substrate. In some specific embodiments, the transistors in CuA utilize process architectures optimized for memory control circuitry, such as advanced manufacturing processes optimized for forming low-voltage and faster logic circuits. In some specific instances, CuA is constructed using fin field-effect transistors (FinFETs) or gate-all-around field-effect transistors (GAAFETs) to achieve dense circuit layers and enhanced transistor performance.

[0072] In some specific instances, the memory device 200 is formed on a semiconductor substrate on which no circuitry is constructed, and the memory device 200 is bonded, for example, using hybrid bonding to a separate semiconductor substrate containing a memory control circuitry. In one specific instance, hybrid bonding is formed on the top side of the memory array opposite the semiconductor layer on which the memory array is constructed, to connect to a mating hybrid bonding formed on a separate semiconductor layer containing control circuitry for operating the memory array. The semiconductor layer or semiconductor substrate on which the memory device 200 is formed may be configured differently depending on the degree of integration with the memory control circuitry.

[0073] In some specific instances, the CuA provides a data path to and from the memory array and further to a memory controller that can be built on the same semiconductor substrate as the CuA. Alternatively, the memory controller may reside on a separate semiconductor substrate, in which case the CuA and associated data paths are electrically connected to the memory controller using various integration techniques, including, for example, hybrid bonding, through-silicon vias (TSVs), exposed contacts, and other suitable interconnect technologies. In one example, the memory controller may be connected to the CuA using an electro-photonic interconnect system.

[0074] In some examples, the memory controller includes control circuitry for accessing and manipulating memory transistors in the memory array connected to it, performing other memory control functions such as data routing and error correction, and providing interface functionality to systems interacting with the memory array. In one example, the memory controller typically provides commands such as erase, program, and read commands to the array-behind circuitry (CuA) via accompanying information such as memory cell addresses and write data for write operations. The memory array autonomously performs memory operations in response to the received commands using the array-behind circuitry.

[0075] In memory device 200, each transistor in a NOR memory string is read, programmed, or erased by appropriately biasing its associated word line 208 (WLx) and common bit line 204 (BLy), which are shared with other transistors in the NOR memory string 212. The associated word line of the transistor is shared by other NOR memory strings on the same plane along a third direction (Z-direction or "vertical direction") with the transistor aligned with it. In some specific instances, the common source line is normally electrically floating, i.e., not hardwired to any potential. During read, programmed, or erase operations, the common source line of the NOR memory string is typically provided with a relatively constant voltage, which is maintained by a voltage source or by the charge in an associated capacitor ("virtual ground"), such as the parasitic capacitance of the common source line. For example, the common source line of a NOR memory string can be biased to a given voltage by a precharge operation, wherein the desired voltage is provided on the common bit line, and the common source line is charged to the voltage on the common bit line by one or more precharge transistors. To program or erase selected memory transistors, for example, a sufficient voltage difference (e.g., 1.5 V to 3 V for ferroelectric memory transistors) is applied across the word line and at least the common bit line. To mitigate interference with unselected memory transistors, a predetermined voltage difference significantly smaller than the voltage required for programming or erasing can be applied across the associated word line and common bit line of the unselected memory transistors to suppress unintended erasure or programming of the unselected memory transistors. To read a selected memory transistor, a read voltage (e.g., 1V for a ferroelectric memory transistor) is applied to the word line, and the bit line is biased to a positive voltage (e.g., ~0.05V to ~0.9V) to induce a current (if present) between the drain and source terminals of the selected memory transistor. The bit line current is sensed by a sense amplifier via a bit line selector to determine the logic state or stored data of the selected memory transistor.

[0076] In some specific instances, to erase a selected memory transistor, the selected word line is biased to 2 to 3 V, and the selected location cell line is biased to 0 V, with the source line set to 0 V (e.g., through a precharge operation). A suppression voltage of 1.1 to 1.5 V is applied to the unselected word line, bit line, and source line. In some specific instances, to program a selected memory transistor, the selected word line is biased to 0 V, and the selected location cell line is biased to 1.8 to 2 V, with the source line set to 0.5 to 0.8 V (e.g., through a precharge operation). A suppression voltage of 0.5 to 0.8 V is applied to the unselected word line, bit line, and source line. In some specific instances, to read a selected memory transistor, the selected word line is biased to 0.7 to 1 V, and the selected location cell line is biased to 0.5 V, with the source line set to 0 V (e.g., through a precharge operation). Apply a 0 V suppression voltage to the unselected word line, bit line, and source line.

[0077] In some specific examples, the annular channel ferroelectric memory transistor with an annular channel layer enables the use of different voltage values ​​for programming and erasing operations. Specifically, the programming voltage applied across the word line and common bit line to program the memory transistor to a first logic group has a first voltage value. Simultaneously, the erasing voltage applied across the word line and common bit line to erase the memory transistor to a second logic group has the opposite voltage polarity to the programming voltage and has a second voltage value. The annular channel layer enables the use of different voltage values ​​for programming and erasing voltages.

[0078] Figures 3(a) and 3(b) are cross-sectional views of the memory structures of Figures 1(a) and 1(c) in specific embodiments of the present invention in two different planes. Each of Figures 3(a) to 3(b) includes two views: view (i) is a horizontal cross-sectional view along line A-A' in view (ii) (i.e., in the XY plane), and view (ii) is a vertical cross-sectional view along line A-A' in view (i) (i.e., in the XZ plane). Furthermore, the memory structure is shown in Figures 3(a) and 3(b) in expanded cross-sectional views to illustrate the detailed construction of the memory structure. In particular, Figure 3(a) shows a cross-sectional view of two memory stacks in the memory structure 10 of Figure 1(a), and Figure 3(b) shows a cross-sectional view of two memory stacks in the memory structure 10a of Figure 1(c).

[0079] Referring to Figure 3(a), memory structure 10 includes a pair of adjacent memory stacks 17 (referred to herein as memory stack 0 and memory stack 1) separated by slot trenches 19. View (i) of Figure 3(a) illustrates a cross-sectional view at bitline layer BL1 in the XY plane. In a specific embodiment of the invention, each memory stack 17 includes two rows of local wordline structures 13 configured to extend in the Y direction. In each memory stack, the local wordline structures 13 in the two rows are staggered in the Y direction such that no two local wordline structures are aligned in the X direction. The staggering of the local wordline structures enables global wordline connections to be made for only one local wordline structure in each memory stack across several memory stacks.

[0080] In a specific embodiment of the invention, each local character line structure 13 is formed in a hole formed in the memory stack during the manufacturing process. The hole is circular in this specific embodiment, but may have other shapes in other embodiments. A concentric layer of the channel layer, ferroelectric layer, and gate conductor layer is deposited into the hole, for example, using a damascene process and atomic layer deposition (ALD). For instance, each local character line structure 13 includes a channel layer 26 formed as an annular layer around the outer circumference of the hole, a ferroelectric dielectric layer 27 formed as an annular layer on the channel layer, and a gate conductor layer 28 filling the remaining cavity of the hole. In some embodiments, an interface layer 25 may be disposed between the channel layer 26 and the ferroelectric dielectric layer 27. As shown in view (i) of FIG3(a), each local character line structure 13 is surrounded by a conductive layer forming a bit line 22 (common drain line) and a source line 24 (common source line). Referring to view (ii) of Figure 3(a), in each memory stack 17, the bit line conductive layer 22 and the source line conductive layer 24 in each active layer surround and contact the annular channel layer 26 of each local word line structure 13 in the memory stack 17. Specifically, a portion of the annular channel layer 26 is disposed in the XY plane between or overlaps with the bit line 22 and the annular ferroelectric gate dielectric layer 27; and a portion of the annular channel layer 26 is disposed in the XY plane between or overlaps with the source line 24 and the annular ferroelectric gate dielectric layer 27.

[0081] View (ii) of Figure 3(a) shows a cross-sectional view of a portion of the word line structure spanning two memory stacks 17 in the XZ plane. In this illustration, two active layers 16 of the memory structure 10 are shown, wherein the active layers are separated or isolated from each other by an interlayer isolation layer 15, which in this example is an air gap isolation. Each active layer 16 includes a first conductive layer 22 serving as a common drain line or bit line 22 and a second conductive layer 24 serving as a common source line or source line 24. Within the active layer 16, the first and second conductive layers are separated by a channel spacer dielectric layer 23 defining the channel length of the memory transistor 20. When constructed in this way, the first conductive layer 22 and the second conductive layer 24 (BL and SL) are formed to contact and surround the channel layer 26 to form a ring-shaped channel ferroelectric memory transistor 20.

[0082] The cross-sectional view in view (ii) of Figure 3(a) spans the local character line structures LWL0-0 of memory stack 0 and LWL0-1 of memory stack 1. The local character line structures LWL1-0 and LWL1-1 are staggered in the Y direction and can be observed through the interlayer isolation layer 15. In the illustrations of this invention, the channel spacer dielectric layer 23 is shown to be transparent to expose the local character line structures LWL1-0 and LWL1-1 formed behind or staggered in the Y direction. In practice, when the channel spacer dielectric layer 23 is a silicon dioxide (SiO2) layer, the channel spacer dielectric layer 23 will be transparent to visible light.

[0083] In memory structure 10, each memory transistor 20 is isolated from adjacent memory transistors along the memory stack (in the Z direction) by an interlayer isolation layer 15. In a specific example shown in Figure 3(a), the interlayer isolation layer 15 is an air gap isolation formed by an air gap cavity 15a and an optional air gap liner 15b. The air gap liner 15b is a dielectric layer used to cover or passivate the exposed surface of the air gap cavity 15a. In some specific examples, the air gap liner 15b is a silicon nitride layer or an aluminum oxide (Al2O3) layer. The air gap liner 15b can be 1 nm to 3 nm thick. In Figure 3(a), the size of the components is sometimes enlarged for illustrative purposes only. It should be understood that the depictions in this and other figures are not necessarily drawn to scale. The air gap cavity 15a forming the interlayer isolation layer 15 provides effective isolation between adjacent memory transistors 20 along the memory stack 17. In a specific embodiment of the present invention, the interlayer isolation layer 15 is also used to provide physical separation between the channel layer 26 of one memory transistor in the same memory stack and the channel layer of the memory transistor above or below the memory transistor, thereby providing isolation between the memory transistors in the memory stack. In particular, the channel layer 26 is removed in the interlayer isolation region between two adjacent active layers, such that the channel layer 26 is formed only in the active layer between the first conductive layer and the second conductive layer that form the bit line 22 and the source line 24 and is in contact with the first conductive layer and the second conductive layer.

[0084] In an alternative specific example, the interlayer isolation layer 15 is formed as a dielectric layer, as shown in Figure 3(b). In some examples, after the channel layer separates in the interlayer isolation region between two adjacent active layers, a dielectric layer, such as a silicon dioxide (SiO2) layer, is deposited, for example by atomic layer deposition (ALD), to fill the cavity of the interlayer isolation region. The deposition process also deposits the dielectric layer on the sidewalls of the slot trench 19, as indicated by sidewall portion 34. The remaining cavity of the slot trench 19 may remain unfilled for use as an air gap isolation, as shown in Figure 3(b), or be filled with a dielectric layer, as shown in Figure 1(c).

[0085] During intermediate processing steps, a dielectric liner 32 may be disposed on the sidewalls of the via openings to provide a smooth surface for deposition of subsequent channel layers and ferroelectric dielectric layers. The dielectric liner 32 is removed during the metal replacement process to allow contact between the bit-line conductive layer and the source-line conductive layer and the channel layer 26. Furthermore, the dielectric liner 32 is also removed between the active layers 16 to facilitate separation of the channel layers 26 between adjacent active layers. Therefore, in the resulting memory structure 10 / 10a shown in Figures 3(a) and 3(b), only a residue of the dielectric liner 32 remains. Specifically, a portion of the dielectric liner 32 remains on the local word-line sidewalls adjacent to the channel spacer isolation layer 23. In some specific examples, the dielectric liner 32 is a silicon dioxide layer (SiO2) and may have a thickness of approximately 2 to 3 nm in the X direction.

[0086] In a specific embodiment of the present invention, the memory structure 10 / 10a is formed by a multilayer film stack of sacrificial material and dielectric layer. After forming the local word line structure, slot trenches 19 are formed in the multilayer film stack to divide the film stack into multiple memory stacks 17. Subsequently, the slot trenches 19 are used in a metal replacement process to replace certain sacrificial layers with a first conductive layer and a second conductive layer, thereby forming bit lines 22 and source lines 24. The slot trenches 19 are also used in a channel separation process to remove channel layers in the interlayer isolation region between active layers. After the memory structure is completed, the slot trenches 19 may be filled with a dielectric layer such as silicon dioxide, or the trench region may remain unfilled to serve as air gap isolation. The manufacturing process for fabricating the memory structure 10 / 10a will be described in more detail below.

[0087] In some specific examples, the active layer of memory structure 10 may be formed with a thin film having a thickness of 15 nm to 25 nm in the Z direction. In one specific example, the first conductive layer and the second conductive layer have a thickness of 20 nm in the Z direction, and the channel spacer dielectric layer has a thickness of 25 nm in the Z direction. In one specific example, each local word line structure has a diameter of 55 nm and is spaced 55 nm apart from adjacent local word line structures in the Y direction. In other specific examples, the local word structures have a diameter of 40 to 70 nm. The memory stack and slot trench have a pitch of 224 nm in the X direction, wherein the slot trench may have a width of 50 to 75 nm in the X direction. The annular oxide semiconductor channel layer 26 has a thickness in the X or Y direction ranging from 5 to 10 nm. The annular ferroelectric dielectric layer 27 has a thickness in the X or Y direction ranging from 3 to 7 nm. In one example, the annular oxide semiconductor channel layer 26 has a thickness of 7 nm, and the annular ferroelectric dielectric layer 27 has a thickness of 5 nm. The gate conductor layer fills the remaining volume of the local word line structure. In some specific instances, the gate conductor layer includes a conductive liner layer, such as titanium nitride (TiN), with a thickness of 2 to 3 nm.

[0088] Figures 4(a) and 4(b) are unfolded perspective views of the memory structures of Figures 1(a) to 1(c) in specific embodiments of the present invention. Specifically, Figure 4(a) illustrates an unfolded view of the annular channel ferroelectric memory transistor 20 formed at a pillar-shaped local word line structure 13 connected to the associated global word line 30. Figure 4(b) is a cross-sectional view through the local word line structure 13. The perspective views in Figures 4(a) and 4(b) are shown with the dielectric layer omitted to better illustrate the memory transistor structure. Referring to Figures 4(a) and 4(b), the bit line conductive layer 22 and the source line conductive layer 24 surround the pillar-shaped local word line structure 13, and the oxide semiconductor channel layer 26 has an annular shape formed around the ferroelectric gate dielectric layer 27 and the gate conductor layer 28. In the vertical direction, the oxide semiconductor channel layer 26 is formed between and in contact with the bit line conductive layer 22 and the source line conductive layer 24. The channel layer 26 is removed or separated in the interlayer region between two adjacent active layers (i.e., between the source line 24 and the next bit line 22). In an example of the invention, the local bit line structure 13 includes an interface layer, and the interface layer 25 is exposed in the interlayer region. Alternatively, the interface layer 25 may be completely or partially removed. As explained in Figures 3(a) and 3(b), the cavities and slit trench cavities in the interlayer region may be filled with a dielectric layer, such as silicon dioxide (SiO2). Alternatively, an air gap dielectric liner may be formed to passivate the exposed surface, wherein the remaining cavities are retained to form air gap isolation.

[0089] Figure 5 is a top view of a memory structure including a pre-charged transistor and a stepped structure according to a specific embodiment of the present invention. Figure 6 is a cross-sectional view of the memory structure of Figure 5 including a pre-charged transistor and a stepped structure according to a specific embodiment of the present invention. Referring to Figures 5 and 6, the memory structure 40 includes a three-dimensional array of NOR memory strings of ring-channel ferroelectric memory transistors formed in a multilayer memory stack. The memory structure 40 includes a plurality of memory stacks 44 arranged in the X direction and separated from each other by slot trenches 45. Each memory stack 44 includes a plurality of active layers 50 separated by interlayer isolation layers 51. In an example of the present invention, the memory stack 44 includes eight active layers L0 to L7. Each active layer 50 includes a first conductive layer as a common drain line or bit line, a second conductive layer as a common source line or source line, and a channel spacer dielectric layer located between the first conductive layer and the second conductive layer.

[0090] Each memory stack 44 includes a memory array portion 42, which includes pillar-shaped local word line structures 56 for forming ring-channel ferroelectric memory transistors at each intersection with the active layer 50. Each memory stack 44 further includes a pre-charge array portion 43, which includes pillar-shaped pre-charge local word line structures 58 for forming ring-channel non-memory transistors at each intersection with the active layer 50. As explained above with reference to FIG2, the non-memory pre-charge transistor is used to set the common source line voltage while maintaining electrical float within the memory structure. In some specific instances, the pre-charge transistor is formed using the same channel layer and the same gate conductor layer as the memory transistor. The pre-charge transistor is formed using a non-polarizable gate dielectric layer to form the non-memory transistor.

[0091] Each memory stack 44 further includes a stepped structure formed in the Y direction at both ends of the memory stack. More specifically, each memory stack 44 includes an odd-numbered stepped portion 46a and an even-numbered stepped portion 46b. In each stepped portion, a conductive via 47 is provided to contact the common drain line (bit line) of the active layer, and a conductive via 48 is provided to connect to a circuit system formed in the semiconductor substrate 52. A metal line 49 connects the conductive via 47 to the conductive via 48 in each stepped step, thereby connecting the common drain line from an active layer to the circuit system formed in the semiconductor substrate. In a specific embodiment of the invention, the conductive via 48 is formed aligned with the individual conductive via 47 in the Y direction and is formed by a multilayer memory stack. Therefore, each conductive via 48 is surrounded by a dielectric spacer layer 53 to prevent the conductive via from short-circuiting to the conductive layer in the active layer.

[0092] When configured in this way, memory structure 40 includes odd-numbered staircase portions 46a connecting to bit lines of an odd number of active layers (e.g., active layers L1, L3, L5, and L7), and even-numbered staircase portions 46b connecting to bit lines of an even number of active layers (e.g., active layers L0, L2, L4, and L6). By using staircase portions 46a and 46b connected to every other active layer, the manufacturing process for forming the staircase portions is greatly simplified.

[0093] Figure 7 is an unfolded cross-sectional view of a memory stack including local word line structures according to a specific embodiment of the present invention. Referring to Figure 7, a portion of a memory stack 60 having local word line structures 64 is shown in the XY plane. The cross-sectional view of Figure 7 is taken across the bit line layer 62 in the memory stack. The memory stack 60 is defined by slot trenches 66, both of which extend in the Y direction. Global word lines 65 for connecting to individual local word line structures extend in the X direction.

[0094] In the specific example shown in Figure 7, the memory stack 60 includes two rows of local word line structures 64 arranged in the X direction and extending in the Y direction. In other words, the local word line structures 64 are arranged as a two-dimensional array in the XY plane. The local word line structures 64 are staggered in the Y direction, such that each global word line 65 extending in the X direction is connected to a single local word line structure in each memory stack. In Figure 7, the dotted circle 68 indicates the connection between the gate conductor layer in the local word line structure 64 and the individual global word line 65.

[0095] In the example shown in Figure 7, each pillar-shaped local character line structure 64 has a diameter of 55 nm and is spaced 55 nm apart from adjacent local character line structures. The slot trench 66 is 55 nm, and the pitch between the memory stack and the slot trench is 224 nm. The local character line structure 64 has a margin of approximately 20 nm from the edge of the memory stack. In this configuration, the global character lines 65 have a pitch of 55 nm, and each global character line 65 has a width of 27.5 nm in the Y direction. In one specific example, the global character lines 65 are formed using double-patterned lithography or self-aligned double-patterned lithography. In other specific examples, the global character lines 65 can be formed using a single patterned lithography.

[0096] Figure 8 is an unfolded cross-sectional view of a memory stack including local word line structures in an alternative embodiment of the present invention. Referring to Figure 8, a portion of a memory stack 70 having local word line structures 74 is shown in the XY plane. The cross-sectional view of Figure 8 is taken across the bit line layer 72 in the memory stack. The memory stack 70 is defined by slot trenches 76, both of which extend in the Y direction. Global word lines 75 for connecting to individual local word line structures extend in the X direction.

[0097] In the specific example shown in Figure 8, the memory stack 70 includes a single row of local word line structures 74 extending in the Y direction. Global word lines 75 extending in the X direction connect to the individual local word line structures in each memory stack. In Figure 8, the dotted circle 78 indicates the connection between the gate conductor layer in the local word line structure 74 and the individual global word line 75. When using a single row of local word line structures 74, the pitch of the global word lines 75 can be widened. The memory stack 70 narrows in the X direction, which reduces the parasitic capacitance of the active layer. The length of the memory stack 70 in the Y direction can be extended to accommodate the desired number of local word line structures, thereby forming the desired number of memory transistors.

[0098] Figures 9(a) and 9(b) are unfolded cross-sectional views of a memory stack including a local character line structure in an alternative embodiment of the present invention. In the embodiment described above, the cylindrical local character line structure is formed using a circular opening in the XY plane. In other embodiments, the cylindrical local character line structure may be formed using an elliptical shape or have a rectangular shape, as shown in Figures 9(a) and 9(b).

[0099] Referring first to Figure 9(a), a portion of a memory stack 80 with local word line structures 84 in the XY plane is shown. The cross-sectional view of Figure 9(a) is taken across the bit line layer 82 in the memory stack. The memory stack 80 is delimited by slot trenches 86, both of which extend in the Y direction. Global word lines 85, used to connect to the individual local word line structures, extend in the X direction.

[0100] In the specific example shown in Figure 9(a), the memory stack 80 includes two rows of local character line structures 84 arranged in the X direction and extending in the Y direction. Each local character line structure 84 has a rectangular shape, wherein the longer dimension is parallel to the Y direction and the shorter dimension is parallel to the X direction. The local character line structures 84 are staggered in the Y direction, such that each global character line 85 extending in the X direction connects to a single local character line structure 84 in each memory stack. In Figure 9(a), the dotted circle 88 indicates the connection between the gate conductor layer in the local character line structure 84 and the individual global character line 85.

[0101] Referring now to Figure 9(b), a portion of a memory stack 90 with local word line structures 94 in the XY plane is shown. The cross-sectional view of Figure 9(b) is taken across the bit line layer 92 in the memory stack. The memory stack 90 is delimited by slot trenches 96, both of which extend in the Y direction. Global word lines 95, used to connect to the individual local word line structures, extend in the X direction.

[0102] In the specific example shown in Figure 9(b), the memory stack 90 includes two rows of local character line structures 94 arranged in the X direction and extending in the Y direction. Each local character line structure 94 has a rectangular shape, wherein the longer dimension is parallel to the X direction and the shorter dimension is parallel to the Y direction. The local character line structures 94 are staggered in the Y direction, such that each global character line 95 extending in the X direction connects to a single local character line structure 94 in each memory stack. In Figure 9(b), the dotted circle 98 indicates the connection between the gate conductor layer in the local character line structure 84 and the individual global character line 85.

[0103] In a specific embodiment of the invention, the column-shaped local character line structure can be formed using circular, elliptical, or rectangular shapes. Regardless of the column shape, the channel layer and ferroelectric dielectric layer are formed as concentric ring layers within the column. Considering the size of the global character lines to be formed above the memory stack to connect to the local character line structure, a specific shape of the column of the local character line structure can be selected to optimize the placement or density of the local character line structure that can be formed in the memory stack.

[0104] In the specific examples described in Figures 5 and 6 above, the memory structure is formed such that only hardwires are connected to the bit lines, while the source lines remain electrically floating; that is, there are no hardwires or continuous electrical connections. A pre-charge transistor is used to set the source lines to the required voltage for each given memory operation. In an alternative specific example, the memory structure of the present invention can be configured to connect both the bit lines (common drain lines) and the source lines (common source lines) via a stepped structure or hardwires.

[0105] Figure 10 is a top view of a memory structure including a stepped structure connected to a common bit line and a common source line, according to a specific embodiment of the present invention. Figure 11 is a cross-sectional view of the memory structure of Figure 10 including a stepped structure connected to a common bit line and a common source line, according to a specific embodiment of the present invention. Referring to Figures 10 and 11, the memory structure 40a includes a three-dimensional array of NOR memory strings of ring-channel ferroelectric memory transistors formed in a multilayer memory stack. The memory structure 40a includes a plurality of memory stacks 44 arranged in the X direction and separated from each other by slot trenches 45. Each memory stack 44 includes a plurality of active layers 50 separated by interlayer isolation layers 51. In an example of the present invention, the memory stack 44 includes eight active layers L0 to L7. Each active layer 50 includes a first conductive layer as a common drain line or bit line, a second conductive layer as a common source line or source line, and a channel spacer dielectric layer located between the first conductive layer and the second conductive layer. In the cross-sectional view of Figure 11, the common source line of the active layer 50 is given a cross-hatching pattern to distinguish the source line from the bit line in the active layer. The use of different patterns in the cross-sectional view of Figure 11 does not necessarily indicate that the common source line and common drain line are formed of different conductive materials. In most cases, the common source line and common drain line are formed of the same conductive material. Similarly, in Figures 6 and 11 (and Figure 16 described below), the channel spacer dielectric layer in the active layer 50 and the interlayer isolation layer 51 are shown using different patterns to distinguish the two layers. The use of different patterns in the cross-sectional views of Figures 6, 11, and 16 does not necessarily indicate that the channel spacer dielectric layer and the interlayer isolation layer 51 are formed of different materials. In some specific examples, both the channel spacer dielectric layer and the interlayer isolation layer 51 are formed of the same dielectric material, such as a silicon dioxide layer. In other specific examples, the channel spacer dielectric layer is a silicon dioxide layer, and the interlayer isolation layer 51 may be implemented as an air gap isolation.

[0106] Each memory stack 44 includes a memory array portion 42, which includes a pillar-shaped local word line structure 56 for forming a ring-shaped channel ferroelectric memory transistor at each intersection point with the active layer 50. In the memory structure 40a, a non-memory pre-charge transistor is not required because the source lines are hardwired. Each memory stack 44 includes a stepped structure formed in the Y direction at both ends of the memory stack. In a specific embodiment of the invention, each memory stack 44 includes a bit line stepped portion 46 and a source line stepped portion 54. In the bit line stepped portion 46, a conductive via 47 is provided to contact the common drain line (bit line) of each active layer 50, and a conductive via 48 is provided to connect to a circuit system formed in the semiconductor substrate 52. Metal lines 49 connect the conductive via 47 to the conductive via 48 at each step, thereby connecting the common drain line of each active layer to the circuit system formed in the semiconductor substrate. In the source line step portion 54, conductive vias 47 are provided to contact the common source line (source line) of each active layer 50, and conductive vias 48 are provided to connect to the circuit system formed in the semiconductor substrate 52. Metal lines 49 connect the conductive vias 47 to the conductive vias 48 at each step, thereby connecting the common source line of each active layer to the circuit system formed in the semiconductor substrate.

[0107] In a specific embodiment of the present invention, the conductive vias 48 of both stepped portions 46 and 54 are formed to be aligned with the respective conductive vias 47 in the Y direction and are formed by stacking multiple layers of memory. Therefore, each conductive via 48 is surrounded by a dielectric spacer layer 53 to prevent the conductive via from being electrically short-circuited to the conductive layer in the active layer.

[0108] When configured in this way, the memory structure 40a includes bit line step portions 46 connected to the bit lines of all active layers (i.e., active layers L0 to L7), and source line step portions 54 connected to the source lines of all active layers (i.e., active layers L0 to L7). By using step portions 46 and 54, the memory transistor in the memory structure 40a has hard-wired connections to both the bit lines and source lines of the circuit system in the semiconductor substrate. Therefore, the source lines can directly have a bias voltage to realize memory operation.

[0109] Figure 12 is a flowchart of a manufacturing process for forming a memory structure including a ring-channel ferroelectric memory transistor, according to a specific embodiment of the present invention. Figures 13(a) to 13(n) (including Figure 13(j1)) illustrate memory structures during intermediate process steps in the manufacturing process of Figure 12, according to some specific embodiments. The following description refers to Figures 12, 13(a) to 13(n), and 13(j1). Each figure in Figures 13(a) to 13(b) and 13(j1) includes two views: view (i) is a horizontal cross-sectional view along line A-A' in view (ii) (i.e., in the XY plane), and view (ii) is a vertical cross-sectional view along line A-A' in view (i) (i.e., in the XZ plane).

[0110] Referring to Figure 12, the fabrication process 300 for forming a ring-channel ferroelectric memory transistor in a memory structure begins at 302 with the formation of a multilayer film stack on a semiconductor substrate. As shown in Figure 13(a), initially, a semiconductor substrate 102 is set, and any circuitry to be formed in or on the substrate 102, such as CuA and interconnect conductors, is fabricated. An insulating layer 104 is disposed on top of the semiconductor substrate to cover and protect the circuitry formed on and in the semiconductor substrate 102. In some specific examples, the insulating layer 104 may also serve as a dielectric layer for use as an etch stop layer in subsequent processing steps. In some specific examples, the insulating layer 104 is a silicon carbide (SiOC) layer or an aluminum oxide (Al2O3) layer. The insulating layer 104 may be formed using any material with suitable selectivity for the subsequent etching processes to be performed.

[0111] Subsequently, a multilayer film stack is formed by sequentially depositing (i) a multilayer 101 and (ii) an interlayer sacrificial layer 120 on the flat surface of the semiconductor substrate 102, or particularly on the insulating layer 104 formed on the substrate 102. In an example of the invention, the interlayer sacrificial layer 120 is deposited on the insulating layer 104 before the deposition of the first multilayer 101. The multilayer 101 comprises three sublayers in the Z direction in this order: (a) a first sacrificial layer 122; (b) a channel spacer dielectric layer 113; and (c) a second sacrificial layer 124. FIG13(a) shows the memory structure 100 after the deposition of the initial thin film layers. The multilayer 101 is also referred to as the "active layer" in this detailed description. View (i) in FIG13(a) shows a horizontal cross-section along line A-A' in view (ii) of the first sacrificial layer 122. View (ii) in Figure 13(a) illustrates a vertical cross-section of the memory structure 100 along line A-A' shown in view (i). The first sacrificial layer 122 and the second sacrificial layer 124 will be replaced by their respective conductive layers in subsequent processing. The interlayer sacrificial layer 120 (also referred to herein as the third sacrificial layer) will be replaced by an insulating material in subsequent processing to form an interlayer isolation layer providing separation between the active layers, as described in more detail below. In one specific example, each sublayer in the multilayer 101 and the interlayer sacrificial layer 120 typically has a thickness of 30 nm or less. In another specific example, the sublayers in the multilayer 101 and the interlayer sacrificial layer 120 do not have the same thickness. Dimensions are provided for illustrative purposes only and are not intended to be limiting in this description. In practical implementation, any suitable thickness or size may be used.

[0112] In some specific examples, memory structure 100 may include a bottommost sublayer and a topmost sublayer designated as dummy layers, which do not necessarily form part of the active layers or part of the memory transistors. Furthermore, in specific examples of the invention, memory structure 100 includes a topmost interlayer sacrificial layer 120 and an etch-stop layer 126 formed on the topmost interlayer sacrificial layer 120. The topmost interlayer sacrificial layer 120 will subsequently be replaced by an interlayer isolation layer. The etch-stop layer 126 serves as a stop layer for subsequent chemical mechanical polishing (CMP) processes. In some specific examples, the etch-stop layer 126 is a silicon carbide (SiOC) layer or a silicon nitride (Si3N4) layer. In the example shown in FIG13(a), the multilayer stack includes four active layers. In other examples, the multilayer stack may be formed using any suitable number or number of active layers.

[0113] In some specific examples, the first sacrificial layer 122 and the second sacrificial layer 124 are each silicon nitride (Si3N4) layers. The channel spacer dielectric layer 113 is an insulating dielectric material, such as silicon dioxide (SiO2). The interlayer (or third) sacrificial layer 120 is a sacrificial material selected from carbon, amorphous silicon (aSi), or silicon-germanium (SiGe). In one specific example, the interlayer sacrificial layer 120 is an amorphous silicon (a-Si) layer.

[0114] After a desired number of active layers 101 are formed by multilayer film stacking, manufacturing process 300 can continue to form a stepped structure on opposite sides of the memory structure (Figures 12, 303). Various methods for forming stepped structures are known in the art and can be applied to form stepped structures for at least contacting the common drain line in the memory structure to be formed. For example, the stepped structure can be formed by successively masking and etching each multilayer of the film stack. The detailed stepped process will not be described herein, and the stepped structure is not shown in Figure 13(a). After the stepped structure is formed, the memory structure is filled with a dielectric layer, and stepped contact openings are formed leading to the circuit system formed in the substrate 102, wherein one contact opening is provided for each step. In a specific example disclosed herein, manufacturing process 300 can form contact openings in the stepped structure, such as by means of a dry etching process. The contact openings are made to pass through the multilayer film stack to reach the semiconductor substrate for connection to the circuit system formed in the semiconductor substrate. A dielectric spacer layer is formed in the contact opening. For example, the dielectric spacer layer may be a silicon dioxide layer (SiO2). A stamping process is performed through the bottom portion of the dielectric spacer layer, and a conductive layer is deposited to fill the contact opening. In this way, a contact with the circuitry formed in the semiconductor substrate is formed. In some specific examples, the conductive layer is a tungsten layer with a titanium nitride liner (TiN / W). After the deposition step, excess material can be removed from the top of the memory structure 100 using, for example, chemical mechanical polishing (CMP), wherein the CMP process terminates at the etch stop layer 126. In this description, the stepped contact with the circuitry in the semiconductor substrate is sometimes referred to as a "CC contact".

[0115] In the case where the memory structure uses a precharged transistor to set the common source line voltage, manufacturing process 300 can continue to form a precharged transistor (PCH) portion of the memory structure (Figures 12, 304). The precharged transistor is optional and can be omitted in other embodiments of the invention. For example, the memory structure may be provided as a hardwired connection to the common source line, and therefore a precharged transistor is not required to set the source line voltage. In one embodiment, to form the precharged transistor, via openings are formed in the PCH portion of the multilayer film stack. A device layer for the precharged transistor is then deposited into the via openings, such as by using an atomic layer deposition (ALD) process. In some embodiments, the device layer for the precharged transistor includes a dielectric liner layer, a channel layer, a non-memory gate dielectric layer, and a gate conductor layer. In one specific example, the dielectric liner is a silicon dioxide layer with a thickness of 2 nm, the channel layer is an oxide semiconductor layer (e.g., IGZO) with a thickness of 5 nm, the non-memory gate dielectric layer is an aluminum oxide (Al2O3) layer with a thickness of 5 nm, and the remaining volume is filled with a tungsten layer with a titanium nitride liner.

[0116] In specific embodiments of the invention, the processing steps for forming the stepped structure and / or pre-charged transistors (if present) may precede, follow, or alternate with the processing steps for forming the memory transistors. The order of the manufacturing process steps described herein is illustrative only and is not intended to be limiting.

[0117] Manufacturing process 300 continues to form memory transistors in the memory array portion of the memory structure. Referring to Figure 13(a), a masking layer 128 is applied to the memory structure (on the etch-stop layer 126) and patterned to have aperture openings 129. In some specific instances, the masking layer 128 is an amorphous hard mask, such as an amorphous carbon hard mask. The masking layer 128 is patterned, for example, using a photolithography patterning step (by using a mask and a patterned layer), followed by a mask opening process to form the openings 129, in which the apertures will be formed in the multilayer film stack. It is noteworthy that the masking layer 128 is not drawn to scale in Figure 13(a), and it should be understood that an amorphous hard mask of sufficient thickness is used in the high aspect ratio etching process of the multilayer film stack of the memory structure 100. Furthermore, it should be understood that the photolithography process and the mask opening process may involve an additional masking layer (not shown) to form a hole pattern in the masking layer 128, as would be understood by those skilled in the art.

[0118] With the hole pattern thus defined in the masking layer 128, the fabrication process 300 continues to form holes in the multilayer film stack using a high aspect ratio etching process (Figures 12, 306). For example, a selective anisotropic dry etching process is applied to form holes in the multilayer film stack using the masking layer 128. After the hole etching process, the remainder of the masking layer 128 is removed, and the resulting structure is shown in Figure 13(b). In the example shown in Figure 13(b), two sets of hole openings 129 representing memory transistors to be formed in two memory stacks are fabricated. In each set, the hole openings are arranged in two rows in the X direction and staggered in the Y direction. In some specific examples, the diameter of the hole openings is between 55 and 70 nm. In one specific example, the hole openings have the dimensions, spacing, and pitch as described above with reference to Figure 7. As will be described in more detail below, the slit trenches to be formed will divide the memory structure into individual mesa, each mesa accommodating a set of via openings and memory transistors to be formed within the via openings. In this invention description, the via opening 129 is sometimes referred to as an LWL via.

[0119] In some specific instances, the manufacturing process uses a mask with a mask pattern having aperture openings to form LWL apertures, these aperture openings having a first diameter. After printing the aperture openings onto a patterned layer (such as a photoresist layer) and transferring the mask pattern onto a masking layer, the size of the aperture openings in the masking layer 128 is further adjusted or enlarged, for example, by additional etching. In this way, a larger aperture size with a smaller pitch can be achieved, exceeding the limitations of photolithography. The enlarged masking layer is then used to etch the multilayer film stack using a high aspect ratio etching process.

[0120] The manufacturing process 300 then continues to form a device layer for a memory transistor in the LWL via 129 (Figures 12, 308). The memory transistor device layer is deposited into the LWL via 129, for example, using an atomic layer deposition (ALD) process. In some specific examples, the device layer for the memory transistor includes a dielectric liner layer, a channel layer, a ferroelectric gate dielectric layer, and a gate conductor layer. In some specific examples, an interface layer may be included between the channel layer and the ferroelectric gate dielectric layer. First, referring to Figure 13(c), a dielectric liner layer 131 is deposited on the sidewall of the LWL via 129. For example, the dielectric liner layer 131 is conformally deposited on the sidewall of the LWL via 129. In one specific example, the dielectric liner layer 131 is deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or a combination thereof. In a specific embodiment of the invention, the dielectric liner 131 is a silicon dioxide layer (SiO2). In other embodiments, the dielectric liner 131 may be another dielectric material that has etch selectivity for the materials used in the first sacrificial layer 122 and the second sacrificial layer 124 and for the channel layer to be formed. In one example, the dielectric liner 131 has a thickness of 1 to 5 nm in the X direction. For example, in one embodiment, the dielectric liner 131 may have a thickness of 2 nm in the X direction. The dielectric liner 131 has the advantage of providing a uniform and flat surface for subsequent deposition of memory transistor device layers.

[0121] The manufacturing process 300 then continues to form a local word line (LWL) structure in the LWL vias lined with a dielectric liner layer. One or more deposition steps are performed to deposit the device layer of the ferroelectric memory transistor. In some specific examples, the deposition of the device layer of the memory transistor includes depositing an oxide semiconductor channel layer 116 in the LWL vias and then depositing a ferroelectric gate dielectric layer 117 as a conformal annular concentric layer. For example, the channel layer 116 and the gate dielectric layer 117 can be deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), or a combination thereof. The remaining cavity of the LWL vias is then filled with a gate conductor layer 118, for example, using ALD technology. In some specific examples, an interface layer 125 is deposited between the channel layer and the ferroelectric gate dielectric layer, for example, using atomic layer deposition (ALD) technology. After the deposition step, excess material can be removed from the top of the memory structure using, for example, chemical mechanical polishing (CMP). Figure 13(d) illustrates the resulting memory structure.

[0122] In one specific example, the oxide semiconductor channel layer 116 is an IGZO layer, and the ferroelectric gate dielectric layer 117 is a zirconium-doped hafnium oxide (HZO) layer. In some specific examples, the oxide semiconductor channel layer 116 and the ferroelectric gate dielectric layer 117 are deposited in the same process chamber without disrupting the vacuum between deposition processes. In some specific examples, the gate conductor layer 118 is a metal layer and may include a thin conductive liner 118a and a conductive filler material 118b. The thin conductive liner 118a may be a titanium nitride (TiN) liner or a tungsten nitride (WN) liner. The conductive filler material 118b may be a metal, such as a tungsten (W) layer or molybdenum (Mo), or heavily doped n-type or p-type polycrystalline silicon. In one specific example, the gate conductor layer 118 is a tungsten layer (TiN / W) with a titanium nitride liner. The interface layer 125 (if present) is an aluminum oxide (Al2O3) layer. In one specific example, the oxide semiconductor channel layer 116 has a thickness of 5 to 10 nm in the X direction, and in one example, it may have a thickness of 7 nm in the X direction. In one specific example, the ferroelectric gate dielectric layer 117 has a thickness of 3 to 6 nm in the X direction, and in one example, it may have a thickness of 5 nm in the X direction. The gate conductor layer 118 fills the remaining volume of the LWL via.

[0123] In some specific examples, the optional interface layer 125 may have a thickness of 1.5 to 3 nm in the X direction, and in one example, it may have a thickness of 2 nm in the X direction. In one specific example, the interface layer 125 is an alumina (Al2O3) layer, which is annealed to produce an amorphous film with the desired properties. In some specific examples, the alumina (Al2O3) layer may be annealed in oxygen (O2), ozone (O3), nitrous oxide (N2O), synthesis gas (H2N2), or argon (Ar). The interface layer 125 is optional and may be omitted in other specific examples of the invention. In some specific examples, the interface layer 125 may be deposited in the same process chamber as the ferroelectric gate dielectric layer without disrupting the vacuum between the deposition of the two layers.

[0124] In a specific embodiment of the present invention, the memory structure 100 is used to form a ferroelectric memory transistor, and the gate dielectric layer 117 is a ferroelectric material forming the ferroelectric gate dielectric layer. For example, the ferroelectric gate dielectric layer is deposited using atomic layer deposition (ALD) technology. After deposition, thermal annealing is performed to crystallize the deposited ferroelectric material into a ferroelectric phase. In some specific embodiments, the ferroelectric gate dielectric layer is a doped hafnium oxide material, such as zirconium-doped hafnium oxide (HfZrO or "HZO"). The ferroelectric phase of HZO is an orthorhombic phase of the material. In some specific embodiments, the HZO ferroelectric gate dielectric layer is annealed in the presence of a conductive capping layer to crystallize the deposited HZO film into the desired orthorhombic phase. In a specific embodiment of the present invention, the manufacturing process 300 performs thermal annealing on the ferroelectric gate dielectric layer after the conductive capping layer is deposited on it. In one specific embodiment, the conductive capping layer is a titanium nitride layer. In one specific example, the conductive capping layer forms a conductive liner layer over the gate conductor layer. Following an annealing process, a conductive filler material for the gate conductor layer is deposited onto the conductive liner layer. In another specific example, the conductive capping layer is a sacrificial capping layer and is removed after an annealing process, such as by using an etching process selectively applied to the ferroelectric gate dielectric layer 117. The gate conductor layer, comprising a thin conductive liner (e.g., TiN) and a conductive filler material (e.g., W), is then deposited onto the annealed ferroelectric gate dielectric layer.

[0125] In one specific example, manufacturing process 300 forms an LWL structure in an LWL via by depositing an oxide semiconductor channel layer 116 on a dielectric liner layer 131 and a ferroelectric gate dielectric layer 117 on the oxide semiconductor channel layer 116. An optional interface layer 125 may be deposited on the oxide semiconductor channel layer 116 prior to the deposition of the ferroelectric gate dielectric layer 117, such as within the same process chamber, without disrupting the vacuum. Subsequently, a conductive capping layer, such as a titanium nitride (TiN) layer, is deposited on the ferroelectric gate dielectric layer 117. In some specific examples, the oxide semiconductor channel layer 116, the ferroelectric gate dielectric layer 117, and the conductive capping layer are deposited within the same process chamber without disrupting the vacuum between deposition processes. In some specific examples, the conductive capping layer also serves as a thin conductive liner 118a for the gate conductor layer. In other specific examples, the conductive capping layer is a sacrificial capping layer removed after an annealing process. After depositing the ferroelectric gate dielectric layer 117 and the conductive capping layer, the manufacturing process then performs an annealing process to crystallize the ferroelectric gate dielectric layer 117. In one specific example, a rapid thermal annealing (RTARTA) process is used, wherein the annealing temperature is between 400 and 500°C for a duration of 30 seconds to 15 minutes in a nitrogen (N2) environment. In one specific example, in the case of a 4 nm HZO layer and a 3 nm TiN conductive capping layer as the ferroelectric gate dielectric layer, an RTA process with an annealing temperature of 475°C for a duration of 8 to 10 minutes is used. In one specific example, after the annealing process, the manufacturing process deposits a conductive filler material 118b (e.g., W) of the gate conductor layer 118 onto the conductive liner 118a (e.g., TiN). In another specific example, following the annealing process, a manufacturing process such as removing the sacrificial capping layer by using an etching process selectively applied to the ferroelectric gate dielectric layer 117. The manufacturing process then deposits a gate conductor layer 118 onto the annealed ferroelectric gate dielectric layer 117. As described above, the gate conductor layer 118 may include a thin conductive liner 118a (e.g., TiN) and a conductive filler material 118b (e.g., W).

[0126] After forming the LWL structure, fabrication process 300 continues to form slot trenches in the multilayer film stack (Figures 12, 310). Referring to Figure 13(e), a top cover oxide layer 142 is formed on the memory structure 10. The memory structure is then patterned by a masking layer (not shown) to define the areas where slot trenches will be formed to define the memory stack. A selective anisotropic dry etching process is performed to etch through the multilayer film stack (including the top cover oxide layer 142) to form slot trenches 119, thereby dividing the memory structure into mesa corresponding to the memory stack for forming NOR strings of memory transistors. Notably, the slot trench etching process is performed only through the multilayer film stack and does not interact with any conductive or metal layers. For example, the slot trench etching process is performed between stepped contacts at stepped structures that may have been formed but do not intersect with the stepped contacts themselves. In one specific example, the slot trench etching process is a high aspect ratio dry etching process.

[0127] With the slot trench 119 thus formed to separate the memory stack, the manufacturing process 300 continues until metal replacement is performed through the slot trench to form a common drain line (bit line) and a common source line (source line) (Figures 12, 312). Referring first to Figure 13(f), the metal replacement process begins by removing the first sacrificial layer and the second sacrificial layer in each active layer. The first sacrificial layer 122 and the second sacrificial layer 124 can be removed using, for example, selective dry etching or selective wet etching processes, thereby creating a cavity 133 between the channel spacer dielectric layer 113 and the interlayer sacrificial layer 120. The first dielectric liner layer 131 acts as an etch stop layer for removing the first sacrificial layer 122 and the second sacrificial layer 124. In this way, the removal of the first sacrificial layer 122 and the second sacrificial layer 124 terminates on the first dielectric liner layer 131, and the channel layer 116 is protected during the etching process. Subsequently, the first dielectric liner 131 is removed through cavity 133 to expose the back side of channel layer 116. In one example, the first sacrificial layer 122 and the second sacrificial layer 124 are silicon nitride layers removed using a selective wet etching process using hot phosphoric acid. In another example, the first dielectric liner 131 is a silicon dioxide layer and can be removed using a wet etching process such as using hydrofluoric acid (HF). It is noteworthy that when the etch stop layer 126 is also a silicon nitride layer, care should be taken to avoid etching or removing the silicon nitride etch stop layer 126. For example, a capping layer can be formed on the sidewalls of the silicon nitride etch stop layer 126 after a slot trench etching process. For example, the capping layer can be a silicon dioxide layer. In this way, the removal of the first and second silicon nitride sacrificial layers will not remove the silicon nitride etch stop layer 126.

[0128] The remaining layers 113 and 120 are typically 30 nm or less in thickness and 30 nm to 60 nm in length; they are held in place by attachment to the first dielectric liner 131, channel layer 116, ferroelectric layer 117, and conductive liner 168. Layers 113 and 120 are supported by rigid metal vertical local word structures that repeat at a given pitch along the entire length of each metal stack in the Y direction (as shown in Figure 13(f)(i)). The strong mechanical support provided by the metal local word line structure spanning the entire depth of the extremely high and narrow memory stack results in the physical stability of the stack, thereby enabling a proportional increase in the height of the memory stack even in the case of extremely high aspect ratio memory structures.

[0129] Next, as shown in Figure 13(g), a conductive layer 134 is deposited into the cavity 133 to replace the removed first and second sacrificial layers. For example, the conductive layer 134 can be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). Prior to the deposition process, any surface oxidation on the exposed back side of the channel layer 116 can be cleaned without damaging the channel layer. During the conductive layer deposition process, excess conductive material is formed on the sidewalls of the slot trench (part 135) and on the top of the memory structure (part 136). The excess conductive material is removed, for example, by dry etching and CMP. In one example, the excess material is removed by selective dry etching, and in some cases, the remaining metal residue or longitudinal material is subsequently removed by selective wet etching. Figure 13(h) illustrates the resulting memory structure. More specifically, a metal replacement process forms conductive layers 112 and 114 in the cavity 133. In one specific example, conductive layers 112 and 114 are each tungsten layers (TiN / W) lined with titanium nitride. As a result of the metal replacement process, the first conductive layer 112 and the second conductive layer 114 are formed in each active layer in contact with the oxide semiconductor channel layer 116 and are separated by a channel spacer dielectric layer 113. In each active layer 101, the first conductive layer 112 serves as the common drain layer (bit line) of the NOR memory string to be formed, and the second conductive layer 114 serves as the common source line (source line). In some specific examples, the first conductive layer 112 and the second conductive layer 114 are each metal layers and may be tungsten (W) layers lined with titanium nitride (TiN), tungsten (W) layers lined with tungsten nitride (W), molybdenum, or cobalt, or other conductive materials described above.

[0130] Following the metal replacement process, manufacturing process 300 continues to perform vertical channel separation via slot trenches (Figures 12, 314). Referring to Figure 13(i), the interlayer sacrificial layer 120 is removed, thereby creating a cavity 137. Various removal processes may be used depending on the material used for the interlayer sacrificial layer 120. For example, if the interlayer sacrificial layer 120 is a carbon layer, the carbon layer can be removed by ashing in an oxygen environment. If the interlayer sacrificial layer 120 is amorphous silicon or silicon-germanium, selective wet or dry etching processes can be used. Next, the dielectric liner layer 131 is also removed through the cavity 137, such as by a wet etching process. Thus, a portion of the oxide semiconductor channel layer 116 is exposed in the interlayer region. The exposed portion of the oxide semiconductor channel layer 116 is removed, such as by a dry etching process or a wet etching process. In one example, the exposed portion of the oxide semiconductor channel layer 116 is removed using an atomic layer etch (ALE) process. Figure 13(j) illustrates the resulting structure. The dotted circle 138 indicates the region where the channel layer 116 has been removed. By removing the channel layer 116 in the interlayer region, the channel layer is isolated from the memory transistors formed in the active layers. In other words, the channel layer 116 is separated from the active layers 101 in the Z direction.

[0131] In some specific examples, the channel layer 116 is an oxide semiconductor material, such as IGZO, and the fabrication process uses a wet etching process with substances such as sulfuric acid, citric acid, acetic acid, hydrochloric acid, or ammonium hydroxide (NH4OH) to selectively etch the exposed portions of the channel layer 116. In some specific examples, the memory structure 100 includes an interface layer 125, and the back-side etching of the channel layer 116 is selective to the interface layer 125, such that the interface layer acts as an etch termination layer for the back-side etching process. That is, the exposed portions of the channel layer 116 are etched through the slot trench 119 and the cavity 137, and the etching process terminates upon reaching the interface layer 125. In one specific example, the interface layer 125 is an aluminum oxide (Al2O3) layer. In another specific example, the back-side etching process may be implemented as a multi-step etching process, including an atomic layer etching step for removing the final 1 to 2 nm of the channel layer, wherein the atomic layer etching step terminates on the interface layer 125 or on the ferroelectric gate dielectric layer 117. In some specific instances, the interface layer 125 may be partially or completely removed during the etching process. The presence or absence of the interface layer 125 in the interlayer isolation region does not affect the performance of the memory transistor.

[0132] In an alternative specific instance, the exposed portion of the channel layer 116 between two adjacent active layers 101 in the memory stack (in the Z direction) can be partially removed, leaving a thin portion that does not effectively act as a parasitic channel conductor.

[0133] In the specific example shown in Figure 13(j), the channel separation process terminates when the exposed portion of the channel layer 66 is removed and the channel region is substantially separated (completely or partially) and isolated from the active layers 101 in each memory stack. In an alternative specific example, the channel separation process can be continued by changing the etchant chemical or process to remove the now exposed portion of the ferroelectric gate dielectric layer 117. Figure 13(j1) illustrates the resulting memory structure after the exposed portion of the ferroelectric gate dielectric layer 117 has been removed through the cavity 137. Separation of the ferroelectric gate dielectric layer 117 is optional and can be omitted in other specific examples of the invention. The dotted circle 139 indicates the area where the ferroelectric gate dielectric layer 117 and the interface layer 125 (if present) have been removed. Removing the ferroelectric gate dielectric layer 117 in the interlayer region has the benefit of preventing lateral migration of polarization regions or lateral migration of oxygen atoms between memory transistors in the vertical adjacent plane.

[0134] Manufacturing process 300 continues to passivate or isolate the memory structure thus formed (Figures 12, 316). Referring to Figure 13(k), in a specific embodiment of the invention, the cavity 137 in the interlayer region is filled with a dielectric layer to form an interlayer isolation layer 115 between each pair of active layers 101. In some specific embodiments, the interlayer isolation layer 115 is an oxygen-containing dielectric layer. In one specific embodiment, the interlayer isolation layer 115 is a silicon dioxide layer. In some specific embodiments, the interlayer isolation layer 115 is deposited using atomic layer deposition (ALD). The deposition of the dielectric layer in the interlayer cavity also results in the deposition of dielectric material 154 on the sidewalls of the slot trench 119. After the deposition of the interlayer isolation layer 115, excess material can be removed from the top of the memory structure using, for example, chemical mechanical polishing (CMP). In some examples, the CMP process removes the top cap oxide layer 142 and terminates on an etch stop layer 126, which serves as a CMP stop layer. Therefore, the memory stack is passivated or isolated by the deposition of the interlayer isolation layer 115.

[0135] Subsequently, as shown in Figure 13(l), the manufacturing process can continue by filling the slot trenches with dielectric layer 151. In this case, the memory structure 100 is completely filled with a dielectric layer, such as a silicon dioxide layer. After subsequent CMP processes of depositing dielectric layer 151 into the slot trenches and removing excess material from the top of the memory structure, a top cover oxide layer 152 is deposited on the memory structure to complete the isolation of the memory structure 100.

[0136] In other specific examples, the manufacturing process may form air gap isolation in the slot trench 119. Referring to FIG13(m), after depositing the interlayer isolation layer 115, sidewall portions 154 are deposited on the sidewalls of the slot trench 119. A non-conformal deposition process may be performed to deposit a dielectric layer, such as a silicon dioxide layer, onto the memory structure. Non-conformal deposition will form a dielectric layer 155 sealing the top of each slot trench 119, thereby leaving the remaining cavities of the trench unfilled for use as air gap isolation 153. A subsequent CMP process removes excess deposited material from the top of the memory structure, and a top cap oxide layer 152 is deposited on the memory structure 100b. In a specific example of the invention, the memory structure may form a dielectric-filled trench 151 (FIG. 3(l)) or an air gap isolation 152 for isolation between memory stacks (FIG. 3(m)). In the following description, the memory structure 100b, which includes air gap isolation between memory stacks, is used to describe the remaining process steps.

[0137] Following the vertical channel separation process, manufacturing process 300 can continue to form the contacts of the stepped structure and the common drain layer (bit line) (Figures 12, 317). In this invention description, the stepped contact with the common drain layer is referred to as the "CB contact". Specifically, manufacturing process 300 can form contact openings in the stepped structure, such as by means of a dry etching process. The contact openings are made to pass through the encapsulating oxide layer to reach each step of the stepped structure to contact the first conductive layer 112 in each active layer 101. The contact openings are then filled with a conductive layer. In some specific examples, the conductive layer is a tungsten layer with a titanium nitride liner (TiN / W). The CB and CC stepped contact structures are shown in Figure 6 above.

[0138] Manufacturing process 300 then proceeds to form a global word line (GWL) to contact the local word line structures in the memory structure (Figures 12, 318). Various methods for forming the global word line can be used. In a specific embodiment of the invention, the global word line is formed on the top of the memory structure 100b. In the example shown in Figure 13(n), a via 156 is formed in the top cover oxide layer 152 to contact the gate conductor layer in each LWL structure. Next, a conductive layer 158 is disposed on the top cover oxide layer to contact each via 156 to form the global word line. The global word line 158 extends in the X direction and is electrically connected to a local word line structure in each memory stack. In one specific embodiment, the via 156 is formed of tungsten, and the global word line 158 is formed of copper. In other specific instances, global character lines can be formed using an inlay process or a single patterning process or a dual patterning process, as will be described in more detail below. In some specific instances, the memory structure can be formed to include some global character lines formed at the bottom of the memory structure (such as in a substrate) and some global character lines formed on top of the memory structure, as will be described in more detail below.

[0139] In a specific embodiment of the present invention, manufacturing process 300 can simultaneously form stepped contact connectors with the global character lines (Figure 320). That is, the masking step used to form the global character lines can also define the areas in which connectors for each connection of stepped contact CC and stepped contact CB will be formed. A conductive layer for the global character lines can also be deposited simultaneously to connect each contact opening CC to CB. The stepped contact connection structure is shown in Figure 6 above.

[0140] Using the manufacturing process described above, a memory structure comprising a three-dimensional array of NOR memory strings including ring-channel ferroelectric memory transistors is formed. In the above description, only the manufacturing process flow relating to forming a stepped structure to connect to the common drain layer is described. It should be understood that the manufacturing process can be adapted to form a stepped structure to connect to the common drain layer and the common source layer, as depicted in Figures 10 and 11.

[0141] In specific embodiments of the present invention, the memory structure includes a ferroelectric memory transistor formed using an oxide semiconductor layer as a channel layer. In the specific embodiments described above, the oxide semiconductor channel layer is formed using a single oxide semiconductor material deposited in the aperture opening to form a pillar-shaped local word line structure. In some specific embodiments, the oxide semiconductor channel layer is formed as a double-layer channel, comprising a first oxide semiconductor layer formed on the sidewalls of the local word line pillars and a second oxide semiconductor layer formed between the first oxide semiconductor layer and a conductive layer forming drain and source lines. The second oxide semiconductor layer is electrically contacted with the first oxide semiconductor layer to serve as the double-layer channel region of the ferroelectric memory transistor. Simultaneously, the second oxide semiconductor layer is electrically contacted with the conductive layer forming drain and source lines to serve as a low-contact-resistance contact layer between the drain and source conductive layers and the first oxide semiconductor layer. Meanwhile, the first oxide semiconductor layer serves as the main channel layer providing the desired high mobility and high on-state current for the channel region of the ferroelectric memory transistor.

[0142] In some specific examples, the second oxide semiconductor is a metal oxide semiconductor material that provides a contact resistance to the bit line / source line (or source / drain) conductive layer that is lower than the contact resistance provided by the first oxide semiconductor layer. In one specific example, the first oxide semiconductor layer is an IGZO layer with a thickness of about 6 nm, and the second oxide semiconductor layer is, for example, an indium aluminum zinc oxide (InAlZnO or IAZO) layer, an indium oxide (InO) layer, or an indium tin oxide (ITO) layer with a thickness of less than 3 nm. In some specific examples, the thickness of the second oxide semiconductor layer is about 1 nm to 2 nm. In other specific examples, other oxide semiconductor materials that provide a desiredly low contact resistance to the bit line / source line conductive layer can be used as the second oxide semiconductor layer. In some specific examples, a metal oxide semiconductor material is needed as the second oxide semiconductor layer that is highly immune to deoxygenation of the channel layer by the source / drain conductive layer and inhibits oxidation of the source / drain conductive layer during thermal processing.

[0143] Figure 14 is a cross-sectional view of a memory structure of a ring-channel ferroelectric memory transistor according to an alternative embodiment of the present invention. The memory structure in Figure 14 is substantially similar to the memory structure in Figure 3(b), except that it includes a second oxide semiconductor layer as a contact layer for the source / drain conductive layers. Identical elements in Figures 3(b) and 14 are given similar element references and will not be described in detail. Referring to Figure 14, the memory structure 400 includes a ring-channel ferroelectric memory transistor 20 formed at the intersection of the bit line conductive layer 22, the source line conductive layer 24, and the pillar-shaped partial word line structure 13. In an embodiment of the present invention, a second oxide semiconductor layer 35 is formed between the oxide semiconductor channel layer 26 and the bit line conductive layer 22 and the source line conductive layer 24. Specifically, the second oxide semiconductor layer 35 is in contact with the oxide semiconductor channel layer 26 on one side and with the bit line conductive layer 22 and the source line conductive layer 24 on the other side. When configured in this way, the second oxide semiconductor layer 35 serves as a contact layer between the oxide semiconductor layer 26 and the bit line conductive layer 22 and the source line conductive layer 24. The second oxide semiconductor layer 35 is formed of an oxide semiconductor material that provides a lower contact resistance to the conductive layers 22 and 24 than the oxide semiconductor channel layer 26.

[0144] In specific embodiments of the invention, the second oxide semiconductor layer 35 may be formed during a metal replacement process, such as step 312 (FIG. 12) in manufacturing process 300. More specifically, the second oxide semiconductor layer 35 is deposited on the memory structure into cavities exposed by the removal of the first and second sacrificial layers after the removal of the first and second sacrificial layers. In particular, the second oxide semiconductor layer 35 is conformally deposited above all exposed surfaces of the memory structure 400. Prior to the deposition process, any surface oxidation on the exposed back side of the channel layer 26 may be cleaned without damaging the channel layer. In some specific embodiments, the second oxide semiconductor layer 35 is deposited using an atomic layer deposition (ALD) process. In some specific embodiments, the second oxide semiconductor layer 35 is formed using an oxide semiconductor material different from that of the first oxide semiconductor layer 26. In some specific examples, the second oxide semiconductor layer 35 is an amorphous oxide semiconductor material, such as indium aluminum zinc oxide (InAlZnO or IAZO), or indium oxide (InO), indium zinc oxide (IZO), or indium tin oxide (ITO) or other suitable oxide semiconductor materials. In other specific examples, both the first oxide semiconductor layer 26 and the second oxide semiconductor layer 35 are indium gallium zinc oxide (IGZO) layers, but with different element ratios. That is, the first oxide semiconductor layer 26 is an indium gallium zinc oxide (IGZO) layer with a first element ratio of indium, gallium, and zinc, and the second oxide semiconductor layer 35 is an indium gallium zinc oxide (IGZO) layer with a second element ratio of indium, gallium, and zinc, wherein the first element ratio is different from the second element ratio. In some specific examples, the thickness of the second oxide semiconductor layer 35 is less than 3 nm, such as about 1 nm to 2 nm.

[0145] After depositing the second oxide semiconductor layer 35, a conductive layer is deposited on the memory structure 400 to form the bit line conductive layer 22 and the source line conductive layer 24. In some specific instances, the conductive layer is deposited using chemical vapor deposition or atomic layer deposition. After the conductive layer is deposited, excess material formed on the sidewalls of the slot trench 19 and the top surface of the memory structure is removed by dry selective etching, and in some cases, the remaining metal residue or longitudinal material is subsequently removed by selective wet etching. Simultaneously, excess material formed on the sidewalls of the second oxide semiconductor layer 35 on the slot trench 19 is also removed in the same process as the conductive material removal or in a separate removal process. Subsequent channel separation processes, passivation processes, and global word line formation can be performed as described above with reference to the manufacturing process 300 of FIG. 12. The resulting structure is shown in FIG. 14. When formed in this way, the bit line / source line conductive layer and the second oxide semiconductor layer are each separated and isolated from the other layers. In particular, in a specific embodiment of the present invention, by means of forming using an ALD process, each bit line / source line conductive layer is partially encapsulated by each of the second oxide semiconductor layers through isolation or separation.

[0146] In the memory structure 400, bit line conductive layer 22 and source line conductive layer 24 are formed and separated by channel spacer dielectric layer 23. Each separated portion of the second oxide semiconductor layer 35 is electrically contacted with the respective bit line or source line conductive layer 22, 24, but isolated from other portions of the second oxide semiconductor layer. Each separated portion of the second oxide semiconductor layer 35 is solid and electrically contacted with the corresponding portion of the first oxide semiconductor layer 26 to form a double-layer channel of ferroelectric memory transistor. In each active layer 16, bit line conductive layer 22 forms the common drain line of the NOR memory string to be formed, and source line conductive layer 24 forms the common source line. In some specific examples, bit line conductive layer 22 and source line conductive layer 24 are each metal layers, and may be titanium nitride (TiN) liner and tungsten (W) layer, tungsten nitride (WN) liner and tungsten (W) layer, molybdenum layer or cobalt layer, or other conductive materials described above.

[0147] In the specific examples described above with reference to Figures 5 and 6, the memory structure forms a memory stack extending over the entire distance between the stepped portions 46a and 46b. In an alternative specific example, each memory stack may be divided into two halves to form shorter common drain and common source lines. Figure 15 is a top view of a memory structure including a stepped structure connected to the common bit line and common source line in an alternative specific example of the present invention. Figure 16 is a cross-sectional view of the memory structure of Figure 15 including a stepped structure connected to the common bit line and common source line in an example of the present invention. Referring to Figures 15 and 16, the memory structure 40b includes a three-dimensional array of ring-channel ferroelectric memory transistors of NOR memory strings formed in a multilayer memory stack. The memory structure 40b includes a plurality of memory stacks arranged in the X direction and separated from each other by slot trenches 45. Each memory stack includes a plurality of active layers 50 separated by interlayer isolation layers 51. Each active layer 50 includes a first conductive layer serving as a common drain line or bit line, a second conductive layer serving as a common source line or source line, and a channel spacer dielectric layer located between the first and second conductive layers. In a specific embodiment of the invention, the memory stack is divided into a first memory stack portion 44a and a second memory stack portion 44b. The first memory stack portion 44a and the second memory stack portion 44b are separated by a slot trench 59. Therefore, the common drain line in the first memory portion 44a is separated and isolated from the common drain line in the second memory portion 44b. When configured in this way, each memory stack portion 44a or 44b includes a memory array portion 42a or 42b, which includes a pillar-shaped local word line structure 56 for forming a ring-shaped channel ferroelectric memory transistor at each intersection point with the active layer 50. Each memory stack portion 44a or 44b further includes a precharge array portion 43a or 43b, which includes a pillar-shaped precharge local character line structure 58 for forming annular channel non-memory transistors at each intersection with the active layer 50.

[0148] Separating the memory stack into a first part and a second part has the advantage of shortening the common drain line and common source line of the memory strings in each active layer, thereby reducing the resistance and capacitance of the common drain line (the bit line of the memory transistor). Therefore, the RC delay of the bit line is reduced, thus improving the access time of the memory transistor. In memory structure 40b, the memory strings in the first memory array portion 42a are accessed by the ladder structure 46a, while the memory strings in the second memory array portion 42b are accessed by the ladder structure 46b. Each ladder structure 46a, 46b provides access to the common drain line of each active layer.

[0149] In a specific embodiment of the present invention, the pillar-shaped local word line structure in the memory array is connected to the global word line to receive bias voltage from the circuit system in CuA, thereby performing memory operations. Several techniques can be used to provide the global word line in the memory structure of the present invention.

[0150] In the specific examples described above, global word lines are placed on top of the memory structure after the manufacturing process used to form the active layer and local word line structure of the memory stack. In the first specific example, the global word lines are formed in a single layer on top of the memory structure. In one specific example, when the pitch of the local word line structure is small or close to the limit of photolithography (e.g., about 55 nm), the single-layer global word lines can be formed using a self-aligned double patterning technique. Figures 17(a) and 17(b) are, respectively, top and cross-sectional views of memory structures including single-layer global word lines in some specific examples. Referring first to Figure 17(a), the memory structure is shown as having memory stacks 140a and 140b separated by slot trench 119. Each memory stack 140a, 140b includes two interleaved columns of NOR strings configured as local word line structure 103. Global character lines 158 are configured to traverse memory stacks 140a and 140b, such that each global character line 158 contacts a local character line structure 103 within the memory stack. When formed in a single layer, the global character lines 158 have a pitch P1, which is the pitch of the local character line structure. When the pitch P1 is small, such as at the photolithography limit, dual patterning techniques can be used to form the global character lines 158.

[0151] Figure 17(b) illustrates a cross-sectional view along line B-B' of the memory stack. Referring to Figure 17(b), after forming the active layer 101, a double-patterned layer can be deposited and patterned to form a mandrel, which is then used to pattern an oxide layer 152 having openings for receiving conductive layers during the dummy process. For example, in some specific instances, the conductive layer is a copper layer. In this way, a single-layer global word line 158 is formed to contact individual local word line structures 103 in the memory stack.

[0152] In a second specific example, global word lines are formed as two conductive layers on top of the memory structure. Figures 18(a) and 18(b) are, respectively, a top view and a cross-sectional view of a memory structure including two layers of global word lines in some specific examples. Referring first to Figure 18(a), the memory structure is shown as memory stacks 140a and 140b separated by slot trench 119. Each memory stack 140a, 140b includes two staggered columns of NOR strings configured as local word line structures 103. The lower global word line 163 is configured to traverse memory stacks 140a, 140b and contact the alternating local word line structures 103 in each memory stack. The upper global word line 167 is configured to traverse memory stacks 140a, 140b and contact other local word line structures 103 in each memory stack. In a two-layer global character line configuration, the pitch P2 of the global character line can become greater than the pitch P1 of the global character line in a single layer.

[0153] Figure 18(b) illustrates a cross-sectional view along line B-B' of the memory stack. Referring to Figure 18(b), after the formation of the active layer 101, a dielectric layer 152 is formed on top of the memory structure, and a shallow via 161 is formed in the dielectric layer 152 to contact the first set of local character line structures 103. Next, an additional patterning layer is formed on top of the memory structure to form the lower global character line 163. In one specific example, the lower global character line 163 is formed by a dummy process. In another specific example, dielectric spacers (not shown) are formed on the lower global character line 163 before the formation of the filler dielectric layer 162. Next, an interlayer dielectric layer 164 is formed on the lower global character line 163. A via 165 is then formed in the interlayer dielectric layer 164 to connect to the second set of local character line structures 103. Next, an additional patterned layer is formed on top of the memory structure to form the upper global character line 167. In one specific example, the upper global character line 167 is formed by an dummy process. In some specific examples, the shallow vias 161 and 165 are both tungsten-filled vias. The lower global character line 163 and the upper global character line 167 are conductive layers, such as copper. When configured in this way, the lower global character line 163 contacts the first set of local character line structures, and the upper global character line 167 contacts the second set of local character line structures. This allows for a larger pitch between the lower and upper global character lines, simplifying the manufacturing process and improving the electrical characteristics of the electrical connections.

[0154] In a third specific example, the global word line is formed as top and bottom conductive layers, one layer located below the memory array and the other layer located above the memory array. Figures 19(a), 19(b), and 19(c) are, respectively, top views, cross-sectional views, and unfolded cross-sectional views of memory structures including the top-bottom layers of the global word line in some specific examples. Figures 19(d) to 19(k) are cross-sectional views of the memory structures of Figures 19(a) to 19(c) illustrating the manufacturing process for forming the top-bottom layers of the global word line in some specific examples. Referring first to Figure 19(a), the memory structure is shown as memory stacks 140a and 140b separated by slot trench 119. Each memory stack 140a and 140b includes two interleaved columns of NOR strings configured as a local word line structure 103. According to the top view in Figure 19(a), the top global character line 176 is configured to traverse memory stacks 140a and 140b and contact the alternating local character line structures 103 in each memory stack. Other local character line structures 103 are contacted by the bottom global character line formed in the substrate. In this case, the pitch P2 of the global character line can be greater than the pitch P1 of the global character line in a single layer.

[0155] Figure 19(b) shows a cross-sectional view along line B-B' of the memory stack. Figure 19(c) shows a detailed view of the bottom global word line in some specific examples. Referring to Figures 19(b) and 19(c), the substrate 102 initially has a bottom global word line 170. That is, when manufacturing the circuit system of CuA in the substrate 102, the bottom global word line 170 forms the wiring to be connected by the global word line. Subsequently, such as when starting to manufacture the memory array on the substrate 102, one or more dielectric layers are formed on the substrate 102 and on the bottom global word line 170. Vias 172 are formed to connect to the bottom global word line 170. Next, conductive landing pads 174 are formed, which are positioned to correspond to the local word line structure to be formed and are also aligned with the vias 172. In a specific embodiment of the invention, conductive landing pads 174 are configured for all local character line structures, even if only a subset of the local character line structures will be connected to the bottom global character line. Therefore, a subset of conductive landing pads is positioned to align with vias 172 for connection to the bottom global character line 170. Conductive landing pads 174 not connected to any bottom global character line are dummy landing pads. However, landing pads 174 serve as an etch stop layer for the local character line via etching process.

[0156] The memory array is then fabricated as described above. During the fabrication process of the local character line structure, openings in the multilayer film stack are formed to lead to landing pads 174, which act as etch stop layers, as shown in Figure 19(d). Next, memory transistor device layers are deposited. In some specific instances, a dielectric liner layer (not shown in this figure) is first deposited in the via openings. Channel layer 116 and ferroelectric gate dielectric layer 117 are then deposited in the via openings, as shown in Figure 19(e). In some specific instances, after depositing channel layer 116 and ferroelectric gate dielectric layer 117 (with or without optional interface layer 125), a conductive capping layer is deposited on ferroelectric gate dielectric layer 117, as shown in Figure 19(e), and annealing is performed on ferroelectric gate dielectric layer 117. In some specific instances, the annealing process is a rapid thermal annealing process using an annealing temperature between 400 and 500°C for a duration of 30 seconds to 15 minutes in a nitrogen (N2) atmosphere. Following annealing, a through-etch process is performed to etch a conductive overlay layer through the bottom of the LWL via, as illustrated by the dotted circle in Figure 19(f). Next, the local word line device layer, including the ferroelectric dielectric layer, interface layer (if present), oxide semiconductor channel layer, and dielectric liner layer, is removed from the bottom of the local word line via, for example, by an isotropic etching process, as illustrated in Figure 19(g). In some specific instances, a conductive overlay layer remains on the annealed ferroelectric gate dielectric layer 117 to act as a protective layer for the ferroelectric dielectric layer during the etching process. All local word line structures are treated in the same manner to form openings leading to the conductive landing pad 174. After forming the opening to the conductive landing pad 174, the conductive capping layer can be removed, for example, by using an etching process selectively applied to the ferroelectric gate dielectric layer 117. Next, a gate conductor layer 118, comprising a gate conductor liner layer 118a and a gate conductor filler layer 118b, is deposited into the local word line structure, as shown in FIG19(h). The gate conductor layer 118 extends to the conductive landing pad 174. In other specific embodiments, the conductive capping layer may be retained and act as a gate conductor liner layer, and the gate conductor layer 118 may consist only of a conductive filler layer, as shown in FIG19(i). For example, the conductive capping layer may be a titanium nitride (TiN) layer and may have a thickness of 2 to 3 nm, and the gate conductor layer 118 may include a tungsten layer filling the remaining volume. With the conductive landing pad 174 connected to the via 172, the local word line structure is thus connected to the bottom global word line 170. Otherwise, the local character line structure is connected to the dummy conductive landing pad.

[0157] The manufacturing process of the memory structure continues the slit opening, metal replacement, and channel replacement processes described above. The resulting structure is shown in Figure 19(j). After forming the active layer of the memory structure, a top global word line 176 is then formed on top of the memory structure to connect to a subset of local word line structures that are not connected to the bottom global word line, as shown in Figure 19(k). For example, in the dummy process, the oxide layer 152 is patterned to have openings for receiving conductive layers. For example, in some specific instances, the conductive layer is a copper layer. In this way, the top global word line 176 is formed as a subset of the local word line structures 103 in the memory stack. In this way, a first set of alternating local word line structures is connected to the top global word line 176, and a second set of alternating local word line structures is connected to the bottom global word line 170. This allows for a larger pitch between the top and bottom global word lines, simplifying the manufacturing process and improving the electrical characteristics of the electrical connections.

[0158] In specific embodiments of the present invention, memory devices are manufactured by forming closely spaced pillars in a multilayer film stack, as described above with reference to FIG. 13(a). For example, a masking layer, such as an amorphous hard masking layer, is patterned using photolithography and a mask opening process to define aperture openings in the hard masking layer, wherein the aperture openings correspond to LWL vias to be formed in the memory structure. In some specific embodiments, single-exposure photolithography can be used to define aperture openings in the masking layer. FIG. 20(a) and FIG. 20(b) illustrate examples of patterning pillar aperture openings in a hard masking layer using single-mask, single-exposure photolithography. In particular, FIG. 20(a) illustrates examples of a mask with a mask pattern that can be used to define aperture openings in the masking layer using single-mask, single-exposure photolithography. FIG. 20(b) illustrates examples of aperture openings formed on the masking layer using the mask in FIG. 20(a). Referring first to Figure 20(a), the mask 502 has a defined aperture pattern 506 for patterning apertures in a patterned layer such as a photoresist layer. The aperture pattern 506 is configured in two staggered rows and has a dimension of 55 nm and a spacing of 55 nm in the Y direction. The aperture pattern 506 is formed in a region 504 corresponding to the area where the memory structure to be formed of the memory stack will be located.

[0159] Figure 20(b) illustrates a masking layer 512, such as an amorphous hard masking layer, formed on the memory structure 510 during an intermediate processing step. The masking layer 512 is patterned using a mask 502 to form apertures corresponding to the aperture pattern 506. Referring to both Figures 20(a) and 20(b), during the manufacturing process, after forming a multilayer film stack of the memory structure 510 (such as the multilayer film stack shown in Figure 13(a)), a first masking layer 512, such as an amorphous hard masking layer, is formed on the multilayer film stack. Additional masking layers, such as an antireflective coating (e.g., SiON), additional carbon-containing masking layers (e.g., SOC or spin-coated carbon), and / or additional silicon-containing masking layers (e.g., SOG or spin-coated glass), may be formed on the first masking layer 512. Finally, a patterned layer, such as a photoresist layer, is formed on the masking layer. Mask 502 is used in photolithography processes to print mask pattern 506 onto a photoresist layer, such as by exposing the photoresist layer with mask 502 and developing the photoresist layer after exposure. In one example, immersion lithography can be used. The mask pattern is then transferred to one or more masking layers using developed or patterned photoresist layers until the mask pattern 506 is transferred to the first masking layer 512 (hard mask layer). This process is sometimes referred to as the mask opening process.

[0160] As a result of the mask opening process, aperture 516 is formed in the first masking layer 512. It is noteworthy that although the aperture pattern 506 drawn on the mask 502 is square, the pattern printed onto the patterning layer using a photolithography process will be circular. Therefore, the mask pattern transferred to the masking layer and down to the first masking layer 512 will be a circular aperture 516 corresponding to the square aperture pattern 506 in the mask 502. Using a photolithography process and a mask opening process, the first masking layer 512 is patterned to have a circular aperture 516. The patterned hard masking layer 512 can then be used in a high aspect ratio etching process to form LWL vias in a multilayer film stack as described above with reference to FIG13(b).

[0161] In the example shown in Figure 20(a), the aperture openings have a size of 55 nm and a spacing of 55 nm in the Y direction. The memory stack and slit trenches to be formed have a pitch of 224 nm in the X direction. The positioning of the aperture openings can pose a challenge to photolithography because the spacing "d1" between adjacent staggered aperture patterns can be as small as 17 nm. Small spacing makes it difficult to accurately print the aperture patterns using common photolithography techniques.

[0162] In other specific embodiments of the invention, multiple patterned photolithography is used to define aperture openings in memory structures. Multiple patterned photolithography enables the formation of high-density patterns (e.g., 35 nm pitch or lower) with less process complexity. Figures 21(a) and 21(b) illustrate examples of using double-mask, double-exposure photolithography to pattern pillar aperture openings in a hard mask layer. Specifically, Figure 21(a) illustrates examples of two masks with mask patterns that can be used to define aperture openings in a masking layer using double-mask, double-exposure photolithography. Figure 21(b) illustrates examples of aperture openings formed on a masking layer using the mask in Figure 21(a). In one specific embodiment, a multiple patterned photolithography technique known as litho-freeze-litho-etch (LFLE) is used. Referring first to Figure 21(a), a first mask 522 has a line space pattern 526 defined thereon, and a second mask 523 has a line space pattern 528 defined thereon. The two masks are shown overlapping in Figure 21(a). The line space patterns of the first and second masks are each oriented at a 45° angle relative to the central axis ("Y-axis") along the Y direction. More specifically, the first mask 522 includes a line space pattern 526 oriented at a 45° counterclockwise direction relative to the Y-axis; and the second mask 523 includes a line space pattern 528 oriented at a 45° clockwise direction relative to the Y-axis (or 135° counterclockwise direction relative to the Y-axis). Thus, the line space patterns 526 and 528 of masks 522 and 523 are perpendicular or 90° to each other, wherein the line space patterns of masks 522 and 523 intersect to define the desired aperture opening 530.

[0163] By using multi-patterned photolithography, tight spacing between aperture patterns can be avoided. In the example shown in Figure 21(a), the line space pattern can have a linewidth of 45 nm and a spacing of 33 nm. Aperture openings of 45 nm size can be formed without considering tight spacing between aperture patterns. In some specific instances, multi-patterned photolithography can be applied to pattern conductive landing pads in semiconductor layers beneath memory arrays for forming bottom global word lines. In the following description, multi-patterned photolithography is described with reference to forming pillar vias in a multilayer film stack for forming LWL vias.

[0164] Figure 21(b) illustrates a masking layer 542, such as an amorphous hard masking layer, formed on the memory structure 540 during an intermediate processing step. The masking layer 542 is patterned using masks 522 and 523 to form apertures corresponding to line space patterns 526 and 528. Referring to both Figures 21(a) and 21(b), during the manufacturing process, after forming a multilayer film stack of the memory structure 540 (such as the multilayer film stack shown in Figure 13(a)), a first masking layer 542, such as an amorphous hard masking layer, is formed on the multilayer film stack. Additional masking layers, such as an anti-reflective coating (e.g., SiON), additional carbon-containing masking layers (e.g., SOC or spin-coated carbon), and / or additional silicon-containing masking layers (e.g., SOG or spin-coated glass), may be formed on the first masking layer 542.

[0165] In some examples, the mask patterns of masks 522 and 523 can be printed onto the masking layer as follows. A first patterned layer (such as a photoresist layer) is formed on the masking layer. The first mask 522 is used in a photolithography process to print the line space mask pattern 526 onto the first patterned layer, such as by exposing the photoresist layer using the mask 522 and developing the photoresist layer after exposure. In one example, immersion lithography can be used. Next, a second patterned layer (such as a photoresist layer) is formed on the developed first photoresist layer. The second mask 523 is used in a photolithography process to print the line space mask pattern 528 onto the second patterned layer, such as by exposing the photoresist layer using the mask 523 and developing the photoresist layer after exposure. As a result of the photolithography process using the first and second masks, an aperture pattern is formed at the overlapping area 530 of the line space mask patterns 526 and 528. That is, the pattern obtained from the two developed photoresist layers is the aperture opening pattern at the overlapping region 530. Next, in a process called the mask opening process, the aperture opening pattern is transferred to one or more masking layers using the developed photoresist layer until the aperture opening pattern is transferred to the first masking layer 542 (hard masking layer).

[0166] As a result of the mask opening process, aperture 546 is formed in the first masking layer 542. As described above, although the overlapping region 530 of the line space patterns 526, 528 is square, the pattern printed onto the patterned layer using a photolithography process will be circular. Therefore, the masking layer 542 has a circular aperture 546 corresponding to the square overlapping region 530. The patterned hard masking layer 542 can then be used in a high aspect ratio etching process to form LWL apertures in a multilayer film stack as described above with reference to FIG13(b).

[0167] In specific embodiments of the present invention, the memory structure can be incorporated as embedded memory into logic integrated circuits. For example, memory structures using one, two, four, or eight active layers can be used to form embedded memory circuits. Furthermore, by using smaller tile sizes, i.e., fewer memory transistors in the memory strings and very few memory strings per tile, the memory structure can be adapted for embedded memory circuits. In particular, the ferroelectric memory transistors in specific embodiments of the present invention can operate at low bias voltages, such as voltage levels less than 2 V, making the memory structure suitable for use as embedded memory circuits.

[0168] Figure 22 illustrates some specific examples of the application of the memory device of the present invention as an embedded memory device. Referring to Figure 22, the memory device 600 is constructed in the manner described above with reference to Figures 1(a) to 1(c) and includes a two-dimensional array of tiles 602, wherein each tile comprises a memory array as a three-dimensional array of contactless ferroelectric memory transistors. The memory array in the tiles 602 is formed above a semiconductor substrate 606. An insulating layer 604 may be disposed between the semiconductor substrate 606 and the memory array (tiles 602) formed on the substrate. A support circuit system (CuA) for operating the memory transistors in the memory array may be formed in the semiconductor substrate 606. In some examples, the support circuit system for the ferroelectric memory transistors of each tile is provided with modularity in a portion of the semiconductor substrate below each tile.

[0169] In some specific instances, the memory device interacts with a memory controller to perform memory operations. As described above, the memory controller includes control circuitry for accessing and operating the ferroelectric memory transistors in the memory device, performing memory control functions, and managing interface functions for host access. In some specific instances, the memory module is formed having a memory device formed on a single semiconductor die and a memory controller formed on a separate semiconductor die. The memory die and memory controller die can be integrated using various integration technologies, such as TSV, hybrid bonding, exposed contacts, through-holes, printed circuit boards, and other suitable interconnect technologies, especially those for high-density interconnects.

[0170] In a specific embodiment of the invention, the memory controller is embedded in the semiconductor substrate of the logic integrated circuit 620. Specifically, the logic integrated circuit 620 may have digital or analog logic circuits 622, such as a core processor, formed thereon. The memory controller circuit 624 is integrated into the logic integrated circuit 160 and formed in a portion of the semiconductor substrate of the logic integrated circuit 620. The memory device 600 is bonded to and electrically connected to the memory controller circuit 624 using various bonding techniques. In this illustration, the memory device 600 includes an array of connectors 608 that are bonded to corresponding mating connectors 610 formed on the logic circuit 620. In some specific embodiments, the connectors 608 and 610 are hybrid integrated bonding, such as copper-to-copper bonding, and may have a pitch of less than 2 micrometers or less than 1 micrometer.

[0171] When configured in this way, the memory device 600 operates as an embedded memory circuit within the logic integrated circuit 620 via the embedded memory controller 624. The memory controller circuit 624 can be directly connected to the digital or analog circuitry 622 on the logic integrated circuit 620 via interconnects 626 formed in the logic integrated circuit, without any interface circuitry. Therefore, the ferroelectric memory transistors in the memory device 600 can be used with minimal latency in the circuitry of the logic integrated circuit 620. That is, the memory transistors can be accessed with low latency via the direct connector 626 between the memory controller circuit 624 and the logic circuitry 622. This configuration is sometimes referred to as "in-memory compute." In-memory compute is particularly needed in artificial intelligence and machine learning applications, which are data-intensive and require large amounts of memory very close to the CPU and GPU core processors, which can be formed as logic circuitry 622 within the logic integrated circuit 620. In a specific embodiment of the present invention, a memory device 150 comprising a three-dimensional array of ferroelectric memory transistors (FETs) of NOR memory strings can be used to form an embedded memory circuit to achieve low latency and high capacity in a memory computing system for data-intensive applications. Notably, because ferroelectric memory transistors have a higher operating temperature, the memory device 600 of the ferroelectric memory transistor can be embedded with the logic integrated circuit 620 by being disposed on the logic integrated circuit rather than on one side of the logic integrated circuit. The embedded memory circuit of the present invention improves latency by eliminating the RC delay caused by the selection signal passing through the insert.

[0172] In some specific instances, the memory device 600 may be directly constructed on top of the logic integrated circuit 620 on the same semiconductor substrate. For example, the memory device 600 may be constructed on top of an insulating layer formed on the logic integrated circuit to protect the manufactured circuit system. For example, the insulating layer may be a silicon oxide layer or a passivation layer, such as a polyimide layer. Electrical connections between the memory device 600 and memory control circuitry or direct electrical connections to other application-specific logic circuitry are provided through vias formed in the insulating layer. In this case, the connection of the memory device through connectors 608 and 610 is avoided.

[0173] In the specific examples described above, such as referring to Figures 1(d) and 1(e), the ferroelectric memory transistor 20 formed in the memory structure 10 may include an interface layer 25 disposed between the oxide semiconductor channel layer 26 and the ferroelectric polarization layer 27. Optionally, the interface layer 25 is a thin dielectric layer and may be configured to act as a barrier layer or an adhesion layer. In some specific examples, the memory structure of the present invention includes a ferroelectric memory transistor formed to include an interface dielectric layer formed between the ferroelectric dielectric layer and the gate conductor layer. Figure 23 illustrates a detailed construction of a memory transistor formed in a memory structure in an alternative specific example of the present invention. In particular, Figure 23 illustrates a memory structure 700 including one pair of memory transistors 720-1 and 720-2 located in two adjacent planes of a memory stack. Except for the placement of the interface dielectric layer, the memory structure 700 is constructed in the same manner as the memory structure described above.

[0174] Referring to Figure 23, the memory transistor 720 includes a first conductive layer 22 forming a drain region (common drain line or common bit line) and a second conductive layer 24 forming a source region (common source line), the conductive layers being separated by a channel spacer dielectric layer 23. The memory transistor 720 further includes an annular channel layer 26 formed vertically along the sidewall of a local word line post and in contact with the first conductive layer 22 and the second conductive layer 24. An annular ferroelectric gate dielectric layer 27 and a gate conductor layer 28 are formed adjacent to the annular channel layer 26. Specifically, a portion of the annular channel layer 26 is disposed in the XY plane between or overlapping the bit line 22 and the gate conductor layer 28; and a portion of the annular channel layer 26 is disposed in the XY plane between or overlapping the source line 24 and the gate conductor layer 28. In a specific embodiment of the invention, the channel layer 26 is an oxide semiconductor layer, such as an IGZO layer. In some specific instances, the gate conductor layer 28 may include a conductive liner 28a serving as an adhesive layer (e.g., TiN) and a low-resistivity conductor 28b (e.g., W). The memory transistor 720 is isolated from adjacent memory transistors in the memory stack by an interlayer isolation layer 15. When configured in this way, memory transistors sharing a common source line and a common bit line form NOR memory strings (also referred to herein as "horizontal NOR memory strings" or "HNOR memory strings") in each memory stack.

[0175] To form a ferroelectric memory transistor, the memory transistor 720 includes a ferroelectric dielectric layer or a ferroelectric polarization layer as a gate dielectric layer 27, also referred to as the ferroelectric gate dielectric layer 27. For example, the ferroelectric gate dielectric layer 27 can be formed using a doped hafnium oxide material such as a zirconium-doped hafnium oxide (HfZrO or "HZO") layer. The ferroelectric polarization layer 27 serves as the storage layer of the memory transistor. In a specific embodiment of the invention, the memory transistor 720 includes an interface dielectric layer 755 formed between the ferroelectric gate dielectric layer 27 and the gate conductive layer 28. For example, the interface dielectric layer 755 can be formed during a local word line formation process, such as by using a damascene process and atomic layer deposition (ALD), when a concentric layer of the channel layer, ferroelectric layer, interface dielectric layer, and gate conductive layer is deposited into a hole. More specifically, after depositing the ferroelectric polarization layer 27 and before depositing the gate conductor layer 28, the interface dielectric layer 755 is conformally deposited onto the annular ferroelectric polarization layer 27.

[0176] In some specific examples, the interface dielectric layer 755 is a thin layer, and can be from 0.5 nm to 3 nm thick. In some specific examples, a material with a high dielectric constant (K), i.e., a high-K material with a dielectric constant greater than that of silicon dioxide (SiO2), is used to form the interface dielectric layer 755. In some specific examples, the interface dielectric layer 755 can be a silicon nitride (Si3N4) layer, or a silicon oxynitride layer, an aluminum oxide (Al2O3) layer, or a zirconium oxide (ZrO2) layer. In one example, when the ferroelectric dielectric layer 27 has a thickness of 4 to 5 nm, the interface dielectric layer 755 can have a thickness of 2 nm. The interface dielectric layer 755 acts as a barrier layer for the gate dielectric layer of the ferroelectric memory transistor 720. The interface dielectric layer 755 is optional and can be omitted in other specific examples of the invention. In other specific instances, the interface dielectric layer 755 (when included) may be formed as a multilayer of different dielectric materials.

[0177] According to another aspect of the present invention, a vertical ferroelectric field-effect transistor is formed using the structure and process described above. In a specific embodiment of the present invention, the integrated circuit includes a vertical ferroelectric field-effect transistor formed above a flat surface of a semiconductor substrate. For example, the vertical ferroelectric field-effect transistor is formed in the same manner as the ferroelectric memory transistor described above, such as with reference to any of the figures described above. In one specific embodiment, referring to Figures 1(a) to 1(e) as an example, the vertical ferroelectric field-effect transistor 20 includes: a gate conductor layer 28 configured as a pillar extending in a first direction (e.g., the Z direction); an annular ferroelectric dielectric layer 27 formed adjacent to the pillar of the gate conductor layer 28; and an annular oxide semiconductor layer 26 formed adjacent to the annular ferroelectric dielectric layer 27. The vertical ferroelectric field-effect transistor 20 further includes a first conductive layer 22 and a second conductive layer 24, each configured as a plane parallel to the flat surface of the semiconductor substrate. The first conductive layer 22 and the second conductive layer 24 surround the outer circumference of the annular oxide semiconductor layer 26 and are in contact with the annular oxide semiconductor layer 26.

[0178] In some specific instances, the first conductive layer 22 and the second conductive layer 24 are configured such that one is on top of the other along a first direction (e.g., the Z direction) and are spaced apart by a first insulating layer 23.

[0179] In this configuration, a vertical ferroelectric crystal is formed at the intersection of the first conductive layer 22 and the second conductive layer 24 with the annular oxide semiconductor layer 26. The first conductive layer 22 forms the drain region of the vertical ferroelectric crystal, and the second conductive layer 24 forms the source region. The oxide semiconductor layer 26 forms a junctionless channel region, and the annular ferroelectric dielectric layer 27 forms the gate dielectric layer of the vertical ferroelectric crystal. Finally, the gate conductor layer 28 forms the gate electrode of the vertical ferroelectric crystal. For example, each vertical ferroelectric crystal is formed in a memory structure, as shown in Figures 1(a) to 1(c), and further detailed in Figures 1(d) and 1(e).

[0180] In another specific example, the memory string array is formed as a plurality of vertical ferroelectric field-effect transistors formed above a flat surface of a semiconductor substrate. For example, each vertical ferroelectric field-effect transistor is formed in the same manner as the ferroelectric memory transistors described above, such as referring to any of the figures described above. In one specific example, referring to Figures 1(a) to 1(e) as an example, each ferroelectric field-effect transistor 20 includes: a gate conductor layer 28 configured as a pillar extending in a first direction (e.g., the Z direction) substantially orthogonal to the flat surface of the semiconductor substrate; an annular ferroelectric dielectric layer 27 formed adjacent to the pillar of the gate conductor layer 28; and an annular oxide semiconductor layer 26 formed adjacent to the annular ferroelectric dielectric layer 27. Each ferroelectric field-effect transistor 20 further includes a first conductive layer 22 and a second conductive layer 24, each configured as a plane parallel to the flat surface of the semiconductor substrate. The first conductive layer 22 and the second conductive layer 24 are configured such that one is on top of the other along a first direction (Z direction) and are spaced apart by a first insulating layer 23. The first conductive layer 22 and the second conductive layer 24 surround the outer circumference of the annular oxide semiconductor layer 26 and are in contact with the annular oxide semiconductor layer 26.

[0181] Each vertical ferroelectric crystal is formed at the intersection of the first conductive layer 22, the second conductive layer 24, and the annular oxide semiconductor layer 25. The first conductive layer 22 forms the drain region of the vertical ferroelectric crystal, and the second conductive layer 24 forms the source region. The oxide semiconductor layer 26 forms a junctionless channel region, and the annular ferroelectric dielectric layer forms the gate dielectric layer of the vertical ferroelectric crystal. The gate conductor layer 28 forms the gate electrode of the vertical ferroelectric crystal.

[0182] In some specific examples, the memory string array includes a stack of memory strings provided in a first direction (e.g., the Z direction) with one on top of the other, wherein each memory string in the stack is associated with a plurality of ferroelectric field-effect transistors extending in a second direction (e.g., the Y direction). The memory string array further includes a plurality of pillars of a gate conductor layer disposed in the second direction and associated with the ferroelectric field-effect transistors along each memory string. When configured in this way, vertical ferroelectric field-effect transistors spanning the memory string stack are formed and vertically aligned along the pillars of the gate conductor layer. The vertically aligned ferroelectric field-effect transistors are electrically isolated from one or more adjacent ferroelectric field-effect transistors by a second isolation layer.

[0183] For ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used herein to describe the relationship of one element or feature relative to another element or feature illustrated in the figures. It should be understood that, in addition to the orientation depicted in the figures, spatial relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as "below" or "under" other elements or features will then be oriented "above" other elements or features. Therefore, the illustrative term "below" can encompass both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein will be interpreted accordingly.

[0184] It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or an intervening element or layer may be present. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, no intervening element or layer is present.

[0185] In this detailed description, the process steps described for a specific instance may be used in different specific instances, even if such process steps are not explicitly described in different specific instances. When a method comprising two or more defined steps is referenced herein, the defined steps may be performed in any order or simultaneously, unless the context specifies or otherwise specifically instructed herein. Furthermore, unless the context specifies or otherwise explicitly instructed, the method may also include one or more other steps performed before any of the defined steps, between two of the defined steps, or after all the defined steps.

[0186] In this detailed description, various specific examples or embodiments of the invention may be implemented in numerous ways, including as processes; apparatus; systems; and compositions of matter. A detailed description of one or more specific examples of the invention is provided above together with the accompanying drawings illustrating the principles of the invention. The invention is described in conjunction with such specific examples, but the invention is not limited to any specific example. Numerous modifications and variations are possible within the scope of the invention. The scope of the invention is limited only by the claims, and the invention encompasses numerous alternatives, modifications, and equivalents. Numerous specific details are set forth in this description to provide a thorough understanding of the invention. These details are provided for illustrative purposes, and the invention may be practiced in the absence of some or all of these specific details, according to the claims. For clarity, technical material known in the art relating to the invention has not been described in detail so as not to unnecessarily obscure the invention. The invention is defined by the appended claims.

[0187] 10: Memory Structure 10a: Memory Structure 12: Semiconductor layer / semiconductor substrate 13: Local character line structure 14: Insulation layer 15: Interlayer isolation layer / air gap isolation layer / second isolation layer 15a: Air gap cavity 15b: Air gap lining 16: Active Layer 17: Memory Stacking 19: Trench 20: Memory transistors 20-1: Memory Transistor 20-2: Memory transistors 22: Common drain line / bit line / first conductive layer / bit line conductive layer [ ] 23: Channel spacer isolation layer 24: Common source line / source line / second conductive layer / source line conductive layer 25: Interface Layer 26: Channel layer / First oxide semiconductor layer 27: Ferroelectric gate dielectric layer 28: Gate conductor layer 28a: Conductive liner 28b: Low resistivity conductor 29: Through hole 30: Global Character Line 32: Dielectric inner liner 34: Side wall portion 35: Second oxide semiconductor layer 36: Dielectric inner liner 38: Dielectric layer 39: Dielectric layer 40: Memory Structure 40a: Memory Structure 40b: Memory Structure 42: Memory Array Section 42a: Memory Array Section 42b: Memory Array Section 43: Pre-charge array section 43a: Precharge array section 43b: Precharge array section 44: Memory Stacking 44a: First memory stack portion 44b: Second memory stack portion 45: Slit Groove 46: Bit-line staircase section 46a: Odd-numbered staircase section / staircase structure 46b: Even-numbered staircase section / staircase structure 47: Conductive via 48: Conductive via 49: Metal wire 50: Active Layer 51: Interlayer isolation layer 52: Semiconductor substrate 53: Dielectric spacer layer 54: Source line step section 56: Local character line structure 58: Precharged local character line structure 59: Slit Groove 60: Memory Stacking 62-bit line layer 64: Local character line structure 65: Global Character Line 66: Slit Groove 68: Dots, lines, circles 70: Memory Stacking 72-bit line layer 74: Local character line structure 75: Global Character Line 76: Slit Groove 78: Dots, Lines, Circles 80: Memory Stacking 82: Bitline layer 84: Local character line structure 85: Global Character Line 86: Slit Groove 88: Dots, Lines, Circles 90: Memory Stacking 92: Bitline layer 94: Local character line structure 95: Global Character Line 96: Slit Groove 98: Dots, Lines, Circles 100: Memory Structure 100b: Memory Structure 101: First Multilayer / Active Layer 102: Semiconductor substrate 103: Local character line structure 104: Insulation layer 112: First conductive layer 113: Channel spacer dielectric layer 114: Second conductive layer 115: Interlayer isolation layer 116: Oxide semiconductor channel layer 117: Ferroelectric gate dielectric layer 118: Gate conductor layer 118a: Thin conductive liner / gate conductor liner 118b: Conductive filler material / gate conductor filler layer 119: Slit Groove 120: Interlayer Sacrifice Layer 122: First Sacrifice Layer 124: Second Sacrifice Layer 125: Interface Layer 126: Etching stop layer 128: Shielding layer 129: Hole opening 131: Dielectric inner liner 133: Cavity 134: Conductive layer 135: Part 136: Part 137: Cavity 138: Dots, Lines, Circles 139: Dots, Lines, Circles 140a: Memory Stack 140b: Memory Stack 142: Top cover oxide layer 151: Dielectric layer 152: Top cover oxide layer / dielectric layer 153: Air gap isolation 154: Dielectric material / sidewall portion 155: Dielectric layer 156: Through hole 158: Conductive Layer / Global Character Line 161:Shallow through hole 162: Filler dielectric layer 163: Lower-level global character line 164: Interlayer dielectric layer 165: Through hole 166: Channel Layer 167: Upper-level global character line 170: Bottom Global Character Line 172: Through hole 174: Conductive Landing Pad 176: Top Global Character Line 200: Memory device 202: Memory Transistor 204: Common Pixel Line 206: Common source line 208: Common character line / Local character line 212: NOR memory string 215: Memory Stacking 300: Manufacturing Process 302: Steps 303: Steps 304: Steps 306: Steps 308: Steps 310: Steps 312: Steps 314: Steps 316: Steps 317: Steps 318: Steps 320: Steps 400: Memory Structure 502: Mask 504: District 506: Hole opening pattern / mask pattern 510: Memory Structure 512: First Shielding Layer 516: Hole opening 522: First Mask 523: Second Mask 526: Linear Space Pattern 528: Line Space Pattern 530: Hole opening / through overlapping area 540: Memory Structure 542: First Shielding Layer 546: Hole opening 600: Memory Device 602: Floor tiles 604: Insulation layer 606: Semiconductor substrate 608: Connector 610: Connector 620: Logic Integrated Circuit 622: Digital or Analog Logic Circuit 624: Memory controller circuit 626: Interconnector 700: Memory Structure 720: Memory Transistor 720-1: Memory Transistor 720-2: Memory Transistor 755: Interface dielectric layer A-A':line B-B': line BL: Bitline BL0: Bitline BL1: Bitline BL2: Bitline BL3: Bitline d1: Interval GWL0: Global Character Line GWL1: Global Character Line GWL2: Global Character Line GWL3: Global Character Line GWL4: Global Character Line GWL5: Global Character Line L0: Active Layer L1: Active Layer L1: Thickness / Channel Length L2: Active Layer L3: Active Layer L4: Active Layer L5: Active Layer L6: Active Layer L7 Active Layer LWL0-0: Local character line structure LWL0-1: Local character line structure LWL1-0: Local character line structure LWL1-1: Local character line structure LWL2-0: Local character line structure LWL2-1: Local Character Line Structure LWL3-0: Local character line structure LWL3-1: Local Character Line Structure P1: Pitch P2: Pitch SL: Source Line SL0: Source line SL1: Source Line SL2: Source Line SL3: Source Line WL0: Character Line WL1: Character Line WL2: Character Line WL3: Character Line WL4: Character Line WL5: Character Line X: First direction Y: Second direction Z: Third-party direction

Claims

1. An integrated circuit comprising a vertical ferroelectric field-effect transistor formed above a flat surface of a semiconductor substrate, the vertical ferroelectric field-effect transistor comprising: a gate conductor layer configured as a pillar extending substantially orthogonal to the flat surface of the semiconductor substrate; an annular ferroelectric dielectric layer formed adjacent to the pillar of the gate conductor layer; an annular oxide semiconductor layer formed adjacent to the annular ferroelectric dielectric layer; and a first conductive layer and a second conductive layer, each configured as a plane parallel to the flat surface of the semiconductor substrate, the first conductive layer and the second conductive layer being arranged along the first direction with one on top of the other and spaced apart by a first insulating layer, the first conductive layer and the second conductive layer surrounding the outer circumference of the annular oxide semiconductor layer and in contact with the annular oxide semiconductor layer. The vertical ferroelectric crystal is formed at the intersection of the first conductive layer, the second conductive layer, and the annular oxide semiconductor layer. The first conductive layer forms a drain region, the second conductive layer forms a source region, the annular oxide semiconductor layer forms a junctionless channel region, the annular ferroelectric dielectric layer forms a gate dielectric layer, and the gate conductor layer forms the gate electrode of the vertical ferroelectric crystal.

2. The integrated circuit of claim 1, wherein the annular oxide semiconductor layer includes an annular layer disposed in the region between the first conductive layer and the second conductive layer and the annular ferroelectric dielectric layer, a first portion of the annular oxide semiconductor layer is disposed between the first conductive layer and the annular ferroelectric dielectric layer in a second direction parallel to the flat surface of the semiconductor substrate, and a second portion of the annular oxide semiconductor layer is disposed between the second conductive layer and the annular ferroelectric dielectric layer in the second direction.

3. The integrated circuit of claim 2, wherein the vertical ferroelectric crystal comprises a first ferroelectric crystal among a plurality of ferroelectric crystals formed along the pillar of the gate conductor layer, the plurality of ferroelectric crystals being stacked such that one is on top of another in the first direction, each of the plurality of ferroelectric crystals being electrically isolated from one or more adjacent ferroelectric crystals of the plurality of ferroelectric crystals by a second isolation layer.

4. The integrated circuit of claim 3, wherein the plurality of ferroelectric crystals formed along the pillar share the gate conductor layer as a common gate electrode.

5. The integrated circuit of claim 3, wherein each of the plurality of ferroelectric field-effect transistors includes an annular oxide semiconductor layer disposed in the region between the first conductive layer and the second conductive layer of the respective ferroelectric field-effect transistor and overlapping the first conductive layer and the second conductive layer in the second direction, the annular oxide semiconductor layer not existing in the region between adjacent ferroelectric field-effect transistors in the plurality of ferroelectric field-effect transistors.

6. The integrated circuit of claim 3, wherein the second isolation layer between one pair of adjacent ferroelectric field-effect crystals in the plurality of ferroelectric field-effect crystals surrounds and contacts the annular ferroelectric dielectric layer.

7. The integrated circuit of claim 3, wherein each of the plurality of ferroelectric field-effect transistors includes an annular oxide semiconductor layer disposed in the region between the first conductive layer and the second conductive layer of the respective ferroelectric field-effect transistor and overlapping the first conductive layer and the second conductive layer in the second direction, wherein the annular oxide semiconductor layer in the region between adjacent ferroelectric field-effect transistors of the plurality of ferroelectric field-effect transistors is partially removed.

8. The integrated circuit of claim 3, wherein the annular ferroelectric dielectric layer extends across the plurality of ferroelectric field-effect crystals in the first direction.

9. The integrated circuit of claim 6, wherein each of the plurality of ferroelectric field-effect crystals further includes an annular ferroelectric dielectric layer disposed in the region between the first conductive layer and the second conductive layer of the respective ferroelectric field-effect crystal and overlapping the first conductive layer and the second conductive layer in the second direction, the annular ferroelectric dielectric layer not existing in the region between adjacent ferroelectric field-effect crystals in the plurality of ferroelectric field-effect crystals.

10. The integrated circuit of claim 3, wherein the vertical ferroelectric crystal further comprises an annular interface dielectric layer formed on the outer circumference of the annular ferroelectric dielectric layer and between the annular oxide semiconductor layer and the annular ferroelectric dielectric layer.

11. The integrated circuit of claim 10, wherein the second isolation layer between one pair of adjacent ferroelectric crystals in the plurality of ferroelectric crystals surrounds and contacts the annular interface dielectric layer.

12. The integrated circuit of claim 2, wherein the pillar of the gate conductor layer includes a first pillar of a plurality of pillars of the gate conductor layer formed on the semiconductor substrate, the pillars of the plurality of gate conductor layers being configured to extend upward in a third direction parallel to the flat surface of the semiconductor substrate and orthogonal to the second direction, each pillar of the plurality of gate conductor layer pillars being associated with the annular ferroelectric dielectric layer and the annular oxide semiconductor layer, each pillar having a plurality of ferroelectric field-effect transistors formed in a plurality of planes in the first direction, the first conductive layer and the second conductive layer in each of the plurality of planes surrounding the outer circumference of the annular oxide semiconductor layer of each of the plurality of gate conductor layer pillars and contacting the annular oxide semiconductor layer, wherein the plurality of ferroelectric field-effect transistors associated with the pillars of the plurality of gate conductor layers in the respective planes of the plurality of planes form a NOR string of ferroelectric field-effect transistors.

13. The integrated circuit of claim 12, wherein the ferroelectric field-effect transistors in each NOR string share a first conductive layer serving as a common drain line and a second conductive layer serving as a common source line, the annular oxide semiconductor layer overlaps and contacts the first conductive layer and the second conductive layer, and the first conductive layer and the second conductive layer serve as the junctionless channel region of each ferroelectric field-effect transistor in each NOR memory string.

14. The integrated circuit of claim 12, wherein the posts of the plurality of gate conductor layers are configured in a single row extending along the third direction.

15. The integrated circuit of claim 12, wherein the pillars of the plurality of gate conductor layers are arranged in two or more rows in the second direction orthogonal to the first direction and the third direction, each of the two or more rows extending along the third direction, and the pillars in each row being offset from the pillars in the adjacent row in the third direction.

16. The integrated circuit of claim 1, wherein the gate conductor layer comprises a first metal layer forming the inner portion of the pillar and a second metal layer as an annular metal layer formed on the first metal layer.

17. The integrated circuit of claim 1, wherein the channel length of the vertical ferroelectric crystal varies with the thickness of the first isolation layer in the first direction.

18. The integrated circuit of claim 1, wherein the channel width of the vertical ferroelectric crystal varies with the outer circumference of the annular oxide semiconductor layer.

19. The integrated circuit of claim 1, wherein the gate conductor layer is biased relative to the drain region to a first voltage value to program the vertical ferroelectric transistor to a first logic state, and the gate conductor layer is biased relative to the drain region to a second voltage value to erase the vertical ferroelectric transistor to a second logic state, the first voltage value and the second voltage value having opposite voltage polarities and different voltage magnitudes.

20. The integrated circuit of claim 1, wherein the drain region and the source region are biased to substantially the same voltage to program or erase the vertical ferroelectric effect transistor.

21. The integrated circuit of claim 19, wherein the gate conductor layer is biased relative to the drain region to a third voltage value to partially polarize the vertical ferroelectric transistor to represent the first logic state, the third voltage value being less than the first voltage value, and the gate conductor layer is biased relative to the drain region to a fourth voltage value to partially polarize the vertical ferroelectric transistor to represent the second logic state, the fourth voltage value being less than the second voltage value.

22. The integrated circuit of claim 15, wherein each of the pillars of the plurality of gate conductor layers has a circular shape in the plane in the second direction and the third direction.

23. The integrated circuit of claim 15, wherein each of the pillars of the plurality of gate conductor layers has a rectangular shape in the plane in the second direction and the third direction, and the rectangular shape of each pillar has a length longer than the width in the plane in the second direction and the third direction.

24. A memory string array, each memory string comprising a plurality of vertical ferroelectric crystals formed above a flat surface of a semiconductor substrate, each of the plurality of vertical ferroelectric crystals comprising: a gate conductor layer configured as a pillar extending in a first direction substantially orthogonal to the flat surface of the semiconductor substrate; an annular ferroelectric dielectric layer formed adjacent to the pillar of the gate conductor layer; an annular oxide semiconductor layer formed adjacent to the annular ferroelectric dielectric layer; and a first conductive layer and a second conductive layer, each configured as a plane parallel to the flat surface of the semiconductor substrate, the first conductive layer and the second conductive layer being arranged along the first direction with one on top of the other and spaced apart by a first insulating layer, the first conductive layer and the second conductive layer surrounding the outer circumference of the annular oxide semiconductor layer and in contact with the annular oxide semiconductor layer. The vertical ferroelectric crystal is formed at the intersection of the first conductive layer, the second conductive layer, and the annular oxide semiconductor layer. The first conductive layer forms a drain region, the second conductive layer forms a source region, the annular oxide semiconductor layer forms a junctionless channel region, the annular ferroelectric dielectric layer forms a gate dielectric layer, and the gate conductor layer forms the gate electrode of the vertical ferroelectric crystal.

25. The memory string array of claim 24, further comprising: a memory string stack configured such that one is on top of the other in the first direction, each memory string in the memory string stack being associated with a plurality of ferroelectric field-effect transistors extending in a second direction; a plurality of gate conductor layer pillars disposed in the second direction and associated with the plurality of vertical ferroelectric field-effect transistors along each memory string, wherein the plurality of ferroelectric field-effect transistors spanning the memory string stack are formed along each pillar of the plurality of gate conductor layer pillars and are vertically aligned, the vertically aligned plurality of ferroelectric field-effect transistors being electrically isolated from one or more adjacent ferroelectric field-effect transistors by a second isolation layer.

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