Method, machine readable medium, electronic device, system and computer program product for calculating parasitic parameters for wire structures defined in a semiconductor design

Abstract

Some embodiments provide a method for calculating parasitic parameters of a line structure defined in a semiconductor design. The method includes generating a second line structure for a first line structure in the semiconductor design, the first line structure including a plurality of straight line shapes, and the second line structure including a plurality of curved shapes; and generating a set of parasitic parameters using the second line structure, the set of parasitic parameters being associated with a set of parasitic effects caused by at least one wire in the first line structure of the semiconductor design.

Description

Technical Field

[0001] The field of this case is generally electronic design automation, especially parasitic parameter extraction. Prior Technology

[0002] Three common types of charged particle beam lithography are unshaped (Gaussian) beam lithography, shaped charged particle beam lithography, and multi-beam lithography. In all types of charged particle beam lithography, a charged particle beam emits energy toward a photoresist-coated surface to expose the photoresist.

[0003] Optical lithography is used in the production or manufacture of semiconductor devices such as integrated circuits. Optical lithography is a printing process that uses a photomask or lithography mask made from a photomask to pattern an integrated circuit on a substrate such as a semiconductor or silicon wafer. Other substrates may include flat panel displays or even other photomasks. Furthermore, extreme ultraviolet (EUV) or X-ray lithography is considered a type of optical lithography. A photomask or multiple photomasks may contain a circuit pattern corresponding to a single layer of the integrated circuit, and this pattern can be imaged onto an area of ​​the substrate that has been coated with a radiation-sensitive material layer called a photoresist or resist. Once the patterned layer is formed, it can undergo various other processes, such as etching, ion implantation (doping), metallization, oxidation, and polishing. These processes complete a single layer in the substrate. If multiple layers are required, the entire process or variations thereof are repeated for each new layer. Finally, a combination of multiple devices or integrated circuits appears on the substrate. These integrated circuits can be separated from each other by cutting or sawing, and then assembled into individual packages. More generally, patterns on the substrate can be used to define artifacts such as display pixels or magnetic recording heads.

[0004] Maskless direct write can also be used to fabricate semiconductor devices, such as integrated circuits. Maskless direct write is a printing process that uses beams of charged particles to create patterns on a substrate, such as a semiconductor or silicon wafer, to fabricate integrated circuits. Other substrates may include flat panel displays, imprinting masks for nanoimprinting, or even stencils. A desired pattern is written directly onto the surface, which in this case is also the substrate. Once the patterned layer is formed, it undergoes various other processes, such as etching, ion implantation (doping), metallization, oxidation, and polishing. These processes complete a single layer in the substrate. If multiple layers are required, the entire process or variations thereof are repeated for each new layer. Some layers can be written using optical lithography, while others can be written using maskless direct write to create the same substrate. Finally, a combination of multiple devices or integrated circuits will appear on the substrate. These integrated circuits can be separated from each other by dicing or sawing and can then be mounted into individual packages. More generally, patterns on a substrate can be used to define artifacts such as display pixels or magnetic recording heads.

[0005] Simulating parasitic effects is crucial in IC design. Parasitic effects refer to excess parasitic capacitance, resistance, and inductance on components (such as traces) in an IC design. Different parasitic effects affect circuit delay, energy consumption, and power distribution. They can also introduce noise sources and other effects that impact reliability. Accurate simulation of interconnect parasitic effects is necessary to evaluate their impact on circuit performance.

[0006] As manufacturing technologies become more complex, various techniques have evolved over time to simulate parasitic parameters that include excess capacitance, resistance, and inductance. However, in recent years, simulating and extracting parasitic parameters has become more challenging at smaller process geometries and newer process nodes. Many of these difficulties stem from the increasing impact of process variations and other types of manufacturability issues at smaller geometries. Existing techniques are also relatively slow in calculating parasitic parameters. Summary of the Invention

[0007] Some embodiments provide a method for calculating parasitic parameters of a line structure defined in a semiconductor design. The method includes generating a second line structure for a first line structure in the semiconductor design, the first line structure including a plurality of straight line shapes, and the second line structure including a plurality of curved shapes; and generating a set of parasitic parameters using the second line structure, the set of parasitic parameters being associated with a set of parasitic effects caused by at least one wire in the first line structure of the semiconductor design.

[0008] Some embodiments provide a machine-readable medium. The machine-readable medium stores a program, wherein when the program is implemented by at least one processing unit, the program implements the methods of some embodiments of the present invention.

[0009] Some embodiments provide an electronic device for calculating parasitic effects on a first wire defined in a semiconductor design. The electronic device includes a set of processing units and a machine-readable medium. The machine-readable medium stores a program that, when implemented by at least one processing unit, implements the methods of some embodiments of the present invention.

[0010] Some embodiments provide a system for calculating parasitic effects on a first wire defined in a semiconductor design. The system includes means for implementing the methods of some embodiments of the present invention.

[0011] Some embodiments provide a computer program product. The computer program product includes a plurality of instructions, wherein when these instructions are executed by a computer, the computer performs the methods of some embodiments of the present invention.

[0012] The foregoing summary is intended as a brief introduction to some embodiments of the invention. It is not intended to be a description or overview of all inventive subjects disclosed in this document. The following description of embodiments, along with the accompanying drawings, will further illustrate the embodiments described in the summary and other embodiments. Therefore, a thorough examination of the summary, embodiments, drawings, and claims is necessary to understand all the embodiments described in this document. Furthermore, the claimed subject matter is not limited to the illustrative details in the summary, embodiments, and drawings. Simple Explanation of the Diagram

[0013] The novel features of this invention are described in the claims. However, several embodiments of this invention are disclosed in the following figures for the purpose of explaining the invention.

[0014] [Figure 1] illustrates a digital design process known in the art. [Figure 2] illustrates an exemplary bus structure known in the art. [Figure 3] illustrates a detailed process for calculating parasitic parameters known in the art. [Figure 4A] and [Figure 4B] illustrate line structures known in the art. [Figure 5] illustrates the process for calculating parasitic parameters as known in the art. [Figure 6A] and [Figure 6B] illustrate the process of calculating parasitic parameters according to some embodiments. [Figure 7] illustrates the process of calculating parasitic parameters according to some embodiments. [Figure 8] illustrates a neural network architecture according to some embodiments. [Figure 9] illustrates the generation of training data according to some embodiments. [Figure 10] illustrates the process of calculating parasitic parameters using blocks according to some embodiments. [Figure 11] shows block data according to some embodiments. [Figure 12] illustrates the process of training a neural network to generate tiles according to some embodiments. [Figure 13] illustrates a neural network that uses tiles to calculate parasitic parameters according to some embodiments. [Figure 14] and [Figure 15] are schematic diagrams of a GPU system according to some embodiments. [Figure 16] shows the capacitor matrix of a 3x3 bus structure according to some embodiments. Implementation

[0015] The following embodiments set forth and describe many details, examples, and examples of the present invention. However, the present invention is not limited to the described embodiments and may be practiced without some of the specific details and examples discussed, as will be clear and apparent to those skilled in the art.

[0016] Semiconductor wiring (commonly referred to as interconnects) creates complex three-dimensional geometries that introduce redundant parasitic capacitances, resistances, and inductances. Effectively handling these redundant parasitic effects is a process that typically requires circuit and masking designers to iterate multiple times to create manufacturable designs that meet specifications, yields, and provide good reliability. Therefore, in electronic design automation (EDA), it is necessary to correctly extract and accurately simulate parasitic effects (e.g., redundant capacitance, inductance, and / or resistance effects) in IC designs. As manufacturing technologies become increasingly complex, different techniques have evolved over time to simulate parasitic parameters that include redundant capacitance, resistance, and inductance.

[0017] This extraction / simulation step is becoming increasingly difficult on smaller process geometries and newer process nodes. Many of these difficulties stem from the growing impact of process variability and other types of manufacturability issues on smaller geometries. Over the years, although advancements in processing technology have reduced resistive effects and low-k dielectric materials have reduced capacitive effects, parasitic effects continue to dominate or become increasingly dominant due to the continuous shrinking of feature sizes (linewidths, etc.).

[0018] Different parasitic effects can impact circuit delay, energy consumption, and power distribution. They can also introduce noise sources and other effects that affect reliability. Accurate simulation is required to evaluate the impact of interconnect parasitic effects on circuit performance. Figure 1 illustrates a simplified digital design flow commonly used, where parasitic parameters are extracted from the circuit placement in the later stages of the flow and considered in the gate simulation in the earlier stages. Typically, interconnect parasitic effects affect delay / timing, causing changes in the gate netlist and requiring another iteration through planar planning and / or place and route to modify the circuit placement. More complex digital design flows can replace the later stages with other steps, such as virtual prototyping, power-grid synthesis, placement, power routing, clock tree synthesis (CTS), post-clock tree synthesis optimization, routing, post-routing timing and signal integrity optimization, and finally, signoff extraction, timing and signal integrity, and power signoff. Parasitic effects must also be considered in these additional design steps.

[0019] The analog design process requires detailed simulation after the layout is completed and parasitic parameters have been extracted. These parasitic parameters affect the simulation results by altering the layout. More complex analog design processes involve a preliminary layout, planar planning, placement and routing, and attempting to account for layout-dependent effects (LDE) and density-gradient effects (DGE). In both analog and digital design processes, routing requires attention to multiple patterns. The impact of pattern density on printability is addressed by dividing the layout into lower-density sections for individual exposure. Similar to digital processes, each step in the analog design process needs to accurately account for parasitic effects.

[0020] In both analog and digital design flows, parasitic effects often necessitate multiple iterations until design constraints related to timing, power, performance, and area are met. Detailed simulations require not only parasitic parameters of the nominal process conditions but also repeated simulations representing parasitic variations at various process corners to ensure that these circuit-level metrics are met amidst process variations.

[0021] Although the following description focuses primarily on capacitance extraction techniques, the methods described herein are also applicable to the extraction of resistance and inductance.

[0022] FastCAP is an existing 3D capacitance extraction program that calculates the self-capacitance and mutual capacitance between ideal conductors of arbitrary shape, orientation, and size. Figure 2 provides an example illustrating the operation of this extraction program. As shown, bus architecture 200 contains four conductors, each with six faces represented as patches. The conductors are decomposed into blocks based on their overlapping positions. The FastCAP input file specifies the discretization of the conductor surfaces as flat plates, where the edges are finely interlocked for accuracy. For the example in Figure 2, FastCAP produces a 4x4 capacitance matrix, as shown in the table below. Capacitor matrix, Pifarad 1 2 3 4 1% group 1 1 247.8 -85.01 -48.53 -48.53 2% group 1 2 -85.01 247.8 -48.53 -48.54 3% group 1 3 -48.53 -48.53 247.9 -84.99 4% group 1 4 -48.53 -48.54 -84.99 247.9 After solving the Maxwell equations for a given structure, a symmetric capacitance matrix is ​​generated as the output by a field resolver, which lists the conductor self-capacitance along the main diagonal and the off-diagonal items are the coupling capacitances between various conductors.

[0023] Various methods can be used in technology pre-characterization, which uses a field resolver to simulate several structures and ultimately calculates the coupling capacitance coefficients from them. Figure 3 shows that at a higher order, a typical pre-characterization process begins by constructing several multilayer two-dimensional circuit line structures 300 containing various widths and spacings. These two-dimensional line structures are then coupled with line height information from the process technology file and extruded (by an extrusion process 302) to form a three-dimensional structure.

[0024] Then, the three-dimensional structure is transformed into a form for processing by the field resolver 304. For example, the three-dimensional structure is transformed into N conductors with a set of plates, which are then consumed by the field resolver 304 to generate NxN capacitance matrices 306. The capacitance matrices are filtered by a filtering process 308 to generate a set of self-capacitance values ​​and a set of coupling capacitance values. These capacitance values ​​are then post-processed into quantitative values, i.e., capacitance coefficients.

[0025] In the paper titled "Analysis and Justification of a Simple, Practical 2 1 / 2D Capacitance Extraction Methodology" by Cong et al., five fundamental principles of the capacitance extraction methodology were proposed. ● The first basis is that "grounding conductors and adjacent conductors on the same floor have a significant shielding effect. Therefore, both must be considered for accurate simulation." ● The second basis is that "when the metal density on layer i exceeds a certain threshold, the coupling between the conductors in layer I+1 and the conductors on layer i-1 is negligible". ● The third basis is that "during the capacitance extraction of conductors on layer i, layer i+ / -2 can be considered as a ground plane with negligible error. Layers beyond i+ / -2 do not need to be considered." ● The fourth basis is that "the coupling analysis of conductors on the same floor only needs to consider the nearest neighbor independently, with the width of the adjacent conductors on the same floor having a negligible effect on the coupling". ● The fifth and final basis is that the joint interaction between "layer i-1 and layer i+1 on layer i" is negligible, so orthogonal crossover and crossunder corrections can be performed incrementally.

[0026] These foundations and nomenclature from the aforementioned papers are used in the parasitic extraction methods of some embodiments of the present invention. For example, Figure 4A illustrates a single-layer structure that allows for the extraction of lateral capacitance (Cl), areal capacitance (Ca), and edge capacitance (Cf) for wires with adjacent spacing S and width W on layer i. The structure on the left shows three wires of the same width W, while the structure on the right shows three wires of slightly different widths W' (W-prime), i.e., these wires differ slightly in width from those in the structure on the left.

[0027] During pre-characterization, two-dimensional bus structures corresponding to the two patterns are established. Line heights from the process specification are used to generate a three-dimensional structure from the two-dimensional structure. The three-dimensional structure is then meshed to create a series of two-dimensional surface plates, and the plate information is used as input to a field resolver. The three-dimensional structure is simulated by a field resolver (e.g., FastCAP) and generates two capacitance matrices. Simultaneous equations are established by correlating the capacitance matrix values ​​with the capacitance component values ​​of Cl, Ca, and Cf, and solved to generate specific linewidths and spacings, i.e., the Cl, Ca, and Cf component values ​​for the W, S pair. This method is then repeated for different values ​​of W and S.

[0028] Figure 4B shows a planar view of the geometry for calculating the upper cross capacitance. The left side of the figure contains a 3x3 bus cross structure 420, and the right side contains a 3x2 bus cross structure 425. Both structures are extruded into three dimensions using the line height from the process specification document and then converted into surface plates. The surface plate information is then used as input and solved by a field resolver (FastCAP), which generates 3x3 and 3x2 capacitance matrices, respectively. The generated capacitance matrices are then post-processed to produce the values ​​for the upper cross capacitance.

[0029] In this approach, the process is repeated with different values ​​of the upper cross linewidth Wc and spacing Sc, and different values ​​of the layer width W and spacing S of interest. Then, the various capacitance matrices are post-processed to allow the upper cross capacitance coefficients to be determined as a function of a four-valued set (W, S, Wc, Sc). A similar method is used to determine the lower cross capacitance (using layer i-1 instead of layer i+1). Other methods may use a 3-layer bus cross structure or other structures, along with appropriate post-processing techniques, to determine the capacitance coefficients.

[0030] Various values ​​of W, S, Wc, and Sc are used, and then Cl, Ca, Cf, the upper cross capacitance coefficient Co, and the lower cross capacitance coefficient Cu are calculated using these values. These values ​​are then used to calculate a lookup table, which allows for the lookup of Cl, Ca, Cf, Co, and Cu as values ​​of W, S, Wc, and Sc in a later capacitance extraction stage. The lookup table is stored as part of the extractor's model library.

[0031] In the capacitance extraction stage, the geometric parameters of the line segments of the IC design of interest are determined, and lookup tables in the model library are checked to find the capacitance component coefficient values. When the wire values ​​encountered in the capacitance extraction stage do not perfectly match the values ​​used in the lookup tables generated in the pre-characterization stage, linear interpolation of W and 1 / S is used.

[0032] Note that this method, along with others, is already associated with geometric parameters. During pre-characterization, the model and tables, along with the model library, are stored as functions of geometric parameters, such as width and spacing. In the extraction stage, the layout is decomposed into a set of geometric parameters (more on width and spacing), and the model / table from the pre-characterization stage is consulted (using linear interpolation if necessary) to calculate capacitance values.

[0033] To simulate the impact of parasitic capacitance on process generations, methods for calculating parasitic capacitance from layout have evolved from one-dimensional, two-dimensional, and 2.5-dimensional to fully three-dimensional solutions to meet the required accuracy.

[0034] Regardless of the level of precision, capacitance extraction is typically performed in two stages. Figure 5 illustrates the traditional flow of capacitance extraction. The first stage, known as "pre-characterization," requires process technology information but not the layout of the actual IC to be extracted. This first stage is performed once for each process technology node. This first stage is depicted above the dashed line 500 in Figure 5. The second stage, known as the extraction stage, requires the actual IC layout design database of the chip to which parasitic parameters are to be extracted, as well as the information generated in the pre-characterization stage. This stage is shown below line 500 in Figure 5. This stage is required once for each IC design and produces a parasitic parameter file or database as output.

[0035] During pre-characterization, a CPU-intensive but highly accurate field resolver is used to determine the capacitance of a specific structure. The resulting capacitance is then post-processed using a specific capacitance model to generate various sets of model parameters or lookup tables representing the process technology. The models and / or lookup tables are then stored as the output of the pre-characterization stage. The parameterized models and / or lookup tables stored in the pre-characterization stage are then combined with geometric information about the IC design from the capacitance extraction stage.

[0036] Typical Reticle Enhancement Technology (RET) methods incorporate Optical Proximity Correction (OPC) verification to identify and correct hotspots. Hotspots are areas that require ideal conditions to print correctly and are therefore susceptible to manufacturing variations, or in some cases, cannot be printed correctly even under ideal conditions. Hotspots lead to poor yields. Inverse Lithography Technology (ILT) is a type of OPC technology. ILT is a process that directly calculates the pattern to be formed on a photomask from the pattern desired to be formed on a substrate such as a silicon wafer. This can involve using the desired pattern on the substrate in the opposite direction as input to simulate the optical lithography process. The photomask pattern calculated by ILT can be purely curvilinear—that is, completely non-linear—and can include circular, near-circular, toroidal, near-toroidal, elliptical, and / or near-elliptical patterns. Extensive research and wafer results show that ILT—especially unconstrained curvilinear ILT—can produce optimal results in terms of wafer pattern fidelity and process margin.

[0037] In critical or highly intensive IC designs, parasitic capacitance values ​​must be simulated as accurately as possible to fully account for any impact on timing (performance) and power consumption. Some implementations achieve this level of capacitance extraction accuracy by directly integrating a process simulator that incorporates proximity effects and can generate curve shapes into the pre-characterization and extraction stages of capacitance extraction.

[0038] Curved shapes more closely resemble the fabricated shapes of components (e.g., wires) in IC designs. Therefore, using curved shapes to perform parasitic parameter extraction improves the accuracy of the extracted parasitic parameter values. Figure 6A illustrates an example of a process simulator that generates and uses curved shapes during pre-characterization. In this example, the process simulator includes a RET 605 that uses information from an IC layout database and tells it how to generate the curved shape 610 to produce a two-dimensional curved shape 610 from a two-dimensional shape 600. The process simulator in this example also includes a semiconductor process model 615 describing a set of parameters for a semiconductor process. This semiconductor process model 615 includes process models such as the type of light source used for lithography and the wavelength of the light used.

[0039] The resulting two-dimensional curve shape 610 is then fed into a three-dimensional extrusion and meshing process 616, and these shapes, along with information from the process specification 618, are used to generate a precise meshed three-dimensional shape 620. This three-dimensional shape 620 is then provided as input to a field resolver 622. The description of the three-dimensional shape 620 is more accurate than that generated using conventional methods. This, in turn, results in the field resolver 622 generating a significantly more accurate capacitance value 624.

[0040] In some embodiments, process simulators simulate various detailed manufacturing defects, thereby allowing the generation of detailed planar views of the shape on silicon. These simulators can account for various proximity effects, line edge roughness, etc. Some embodiments combine the data generated by these simulators with process technology document information for technology stacking to produce highly accurate 3D models. These 3D models are then used as input to a field resolver to extract capacitance with high accuracy.

[0041] Where runtime is not critical, manufacturing simulation tools can fully account for process variability and curve design techniques, allowing for more accurate determination of curve interconnect variability across process corners. However, given that runtime is typically critical, some embodiments employ newer and better capacitance extraction techniques that are independent of traditional pattern libraries and traditional pattern matching, and simultaneously consider the impact of process variability and the increase in curve shape in manufacturing design. These embodiments, while taking process variability into account, can accurately extract parasitic capacitance for both the curve design shape and the manufactured curve interconnect shape.

[0042] Traditional capacitance extraction methods primarily rely on CPU-based processing using a Single Instruction, Single Data Stream (SISD) architecture. While the pre-characterization and extraction problem can be broken down into regional subproblems that can be solved in parallel using multiple CPU methods, the computation of these subproblems is still less refined than the overall problem. This computation is typically performed on Graphics Processing Units (GPUs) with a Single Instruction, Multiple Data (SIMD) architecture—for example, in graphics processing or deep learning applications. Therefore, traditional capacitance extraction methods require a large number of CPUs to achieve significant performance advantages.

[0043] Therefore, it is desirable to map the capacitance extraction problem to new SIMD architectures, such as GPUs or Tensor Processing Unit (TPU) devices, to achieve a finer degree of parallelism and to solve the capacitance extraction problem more efficiently. Some embodiments improve the speed of parasitic pre-characterization and extraction by performing these operations in the pixel domain, thereby allowing these operations to be performed by SIMD architectures, such as GPUs or Tensor Processing Unit (TPU) devices. These embodiments use machine-trained networks (e.g., neural networks) to process the pixel-wise definitions of IC design components (e.g., line structures) analyzed during pre-characterization and extraction.

[0044] For example, some embodiments of the systems and methods use a field resolver to determine capacitance values, where the input conductor structure, as input to the resolver, is curved (e.g., in a surface plot). Some embodiments use a trained curve shape prediction convolutional neural network (CNN). Some embodiments of the systems and methods perform technical pre-characterization of training the capacitance prediction CNN, and then store the capacitance prediction network architecture and trained weights in a model library. Some embodiments provide systems and methods for training a multitrack capacitance prediction CNN during technical pre-characterization and then storing the capacitance prediction CNN architecture and trained weights in a model library.

[0045] The use of a trained curve shape prediction CNN enables some implementations to quickly generate accurate 3D representations of the manufactured curve conductor shapes during extraction. These 3D manufactured curve conductor shapes are then provided as input to the field resolver. This method improves the accuracy of critical path extraction, especially under conditions of significant process variation.

[0046] Some embodiments use deep learning techniques instead of geometric methods to perform capacitance coefficient simulation in patterned extraction of non-critical circuitry. For example, in some embodiments, the capacitance component prediction CNN architecture predicts capacitance or capacitance coefficient values ​​by using a two-dimensional rasterized image of the conductor architecture as input instead of using geometric parameters. This eliminates some limitations of model-based or tabular methods (e.g., used in 2.5D and 3D pattern matching techniques). This ultimately expands the applicability and scope of patterned techniques.

[0047] Some embodiments perform full capacitance extraction by using a trained CNN instead of traditional pattern matching or field resolvers for parasitic parameter extraction. For example, in some embodiments, the design to be extracted is rasterized down to the pixel domain and segmented into patches. The capacitance of the conductor, represented as pixels in each patch, is rapidly inferred by a trained capacitance prediction CNN, and the patches associated with a given conductor are integrated to obtain the final capacitance value. Embodiments using neural networks can be executed quickly because they can be efficiently processed by the SIMD underlying architecture of today's GPU and TPU devices.

[0048] Figure 6B illustrates how, in the capacitance extraction process, a trained curve shape prediction neural network 650 is used to generate highly accurate parasitic capacitance values ​​for the conductors of the curves that will be produced after the IC is fabricated using the IC design. The neural network 650 is trained to generate several two-dimensional curve shapes 654 for several process variations of a two-dimensional shape 652 defined after the EDA stage (e.g., after wire winding). In some embodiments, the neural network processes the pixel definition of the two-dimensional shape 652 and generates the two-dimensional curve shape 654 in the pixel domain. Therefore, for the neural network, the input two-dimensional shape 652 is rasterized into the pixel domain.

[0049] As shown in Figure 6B, the resulting two-dimensional curve shape 654 with process variations is then fed into the three-dimensional extrusion and meshing process 656. These shapes, along with information from the process specification 658, are then used to generate a precise meshed three-dimensional shape 660 (defined by the three-dimensional surface description). To perform the extrusion, the definition of the two-dimensional curve shape is transformed from the pixel domain to the geometric contour domain, where the shape depends on the definition of its contour.

[0050] These three-dimensional shapes 660 are then provided as input to the field resolver 662. The description of the three-dimensional shapes 660 is far more accurate than that produced using conventional methods. This ultimately results in the resolver 662 producing a significantly more accurate capacitance value 364.

[0051] Other embodiments use multiple single-output neural networks operating in parallel, rather than running only one neural network 650, to generate several two-dimensional curve shapes 654 for several process variations, wherein each single-output neural network is used for a different process variation. These concurrently executing neural networks generate several process-angle-specific two-dimensional wafer profiles for several process variations. In some embodiments, each such neural network uses a predetermined set of weights corresponding to a process variation.

[0052] On the other hand, the neural network 650, which generates several two-dimensional curve shapes 654 for several process variations, takes a set of IC layout drawing shapes as input, but produces multiple rather than a single curve shape output, with one output for each process manufacturing corner. Examples of multiple two-dimensional curve shapes for multiple process variations (generated by a neural network 650 or multiple single process variation networks) include an average curve image, a maximum curve image, and a minimum curve image corresponding to different extreme values ​​in the process conditions.

[0053] These examples, and details of how a curve shape prediction neural network can be trained and subsequently used to generate detailed two-dimensional images of curved silicon wafer shapes (given a grating pattern from an IC design as input), are disclosed in U.S. Application Publication No. 2022 / 0128899, "Methods and Systems to Determine Shapes for Semiconductor or Flat Panel Display Fabrication," and U.S. Provisional Application No. 63 / 283,520, filed November 28, 2021, both of which are incorporated herein by reference.

[0054] As previously described, the two-dimensional curve shape 654 relative to process variations is extruded and meshed in parallel by a three-dimensional extrusion and meshing process 656 to form a set of angle-specific or extremum-specific three-dimensional surface meshes 660 subsequently input to the field resolver 662. In some embodiments, the field resolver is a single field resolver, while in others it is multiple field resolvers. The field solving operations performed by the field resolver produce a corresponding set of parasitic capacitance values ​​(e.g., a set of matrix values) relative to the process variations. In some embodiments, the parasitic capacitance values ​​are filtered and converted into DSPF / SPEF (Detailed Standard Parasitic Format / Standard Parasitic Exchange Format) or other industry-standard parasitic parameter representations, such as the Synopsys Galaxy Parasitic Database (GPD).

[0055] Therefore, modifications to curvature due to various process variations can be accurately captured from the capacitance values ​​generated by the resolver at various process angles. For each two-dimensional shape in the IC design being analyzed, the aforementioned embodiments calculate multiple two-dimensional curve shapes relative to multiple process variations. However, other embodiments use the flow and neural network shown in FIG6B to generate two-dimensional and three-dimensional shapes only for one process condition (a specific process variation), thus generating parasitic capacitance values ​​only for one process condition.

[0056] Figure 7 illustrates a novel non-geometric method 700 for generating capacitance coefficients for subsequent use during extraction, which replaces or supplements geometric methods used to calculate capacitance coefficients during pre-characterization processes. Geometric methods take a layout and simplify it into geometric features, such as line lengths, spacing, etc., as described above with reference to Figure 4.

[0057] On the other hand, during the pre-characterization phase, the method shown in Figure 7 replaces the simple capacitance model / lookup table with a trained capacitance prediction neural network 740, which is a more general function approximation. In this method, image rasterization 720 is performed on the line structure 710 to generate several two-dimensional images, hereinafter referred to as multi-channel two-dimensional images 730. Image rasterization 720 defines the multi-channel two-dimensional images 730 in the pixel domain (i.e., generates pixel-based definitions for the multi-channel two-dimensional images 730). Therefore, the method shown in Figure 7 uses the designed pixel representation to generate capacitance coefficients from which parasitic capacitance is calculated (e.g., after multiplying the coefficients by the line segment length and / or the line segment overlap length), instead of quantizing geometric properties and then using these properties along with the pre-characterized lookup table values ​​to calculate the capacitance.

[0058] In some embodiments, image rasterization produces white pixels that are fully filled (e.g., pixels completely covered by shapes, such as line segments), black pixels that are completely empty (e.g., pixels not covered by any shapes, such as line segments), and gray pixels that are partially filled. In some embodiments of these embodiments, fully filled pixels are represented by the value 1.0, completely empty pixels by the value 0.0, and partially filled pixels by values ​​within the range [0,1] representing the pixel region filled by the wire (e.g., a pixel filled by 50% would have a value of 0.5). Before rasterizing the line structure, some embodiments decompose the line structure into several components (e.g., several wires, line breaks, or line structure portions), and then rasterize them individually.

[0059] The multi-channel two-dimensional image 730 is then used as the primary input to a capacitance prediction neural network 740 that generates a capacitance vector 750. In some embodiments, the capacitance vector values ​​750 generated by the trained capacitance neural network 740 are further post-processed into capacitance coefficients. For this purpose, the capacitance vector 750 is provided to a post-processor 755, which generates capacitance coefficients 760 as output. As shown, in some embodiments, these capacitance coefficients include Cl, Ca, Cf, Co, and Cu, while in other embodiments, they are post-processed into other coefficients for other capacitance models.

[0060] To generate the capacitance coefficient 760, in some embodiments, the post-processor 755 constructs a simultaneous equation relating the capacitance matrix values ​​to the capacitance component values ​​of Cl, Ca, and Cf, and solves this equation to generate specific linewidths and spacings, i.e., the Cl, Ca, and Cf component values ​​for the W, S pair. This method is then repeated for various W, S values. In some embodiments, the generated capacitance coefficient 760 is a parasitic unit length. Therefore, during extraction, the generated capacitance coefficient 760 is subsequently used to calculate parasitic capacitances, for example, by multiplying these coefficients by the length of the overlapping line segments.

[0061] Using a trained neural network 740 as the mapping mechanism is advantageous because it eliminates the need for external linear interpolation during the extraction phase, when the linewidth and spacing differ from those used during training. This is because the neural network, after proper design and training, acts as a general function approximator and does not require such external interpolation when operating on previously unseen data. Another advantage of this method over conventional methods is that the multi-channel two-dimensional image 730 input to the neural network 740 can represent arbitrary conductor shapes, including curved shapes.

[0062] For example, in some embodiments, one or more of the line structures are generated from curve shapes using a second neural network trained on shape prediction (e.g., the curve shape prediction neural network of Figure 6B). In some embodiments, the input semiconductor design includes several line structures. Each of these line structures is rasterized, and the curve shape is calculated from each rasterized line structure. Rasterization of each line structure can produce several images; for example, in some embodiments, each image corresponds to a layer of wiring in the line structure. The resulting curve line structure may contain multiple intersecting line tracks and may be sub-segmented into smaller structures. Before rasterizing each line structure, some embodiments decompose the line structure into several components (e.g., several wires, segments, or sections of the line structure), and then rasterize them individually.

[0063] In Figure 7, the neural network output (i.e., capacitance vector 750) represents, in some embodiments, a vector of capacitance values ​​for a geometric structure. The input line structure 710 can be rasterized into a multi-channel two-dimensional image 730 representing three conductors, each conductor on the layer of interest i, above an upper cross layer i+1, and below a lower cross layer i-1. During rasterization 720, the line structure is rasterized into the multi-channel two-dimensional image 730. In some embodiments, different image channels represent different interconnect layers of an IC process.

[0064] For a 3x3 bus crossover structure, nine capacitors of interest are shown in Figure 16. These are the self-capacitance of the central conductor segment 5 in the central layer i (metal 2) and the eight capacitance values ​​of its eight nearest neighbors. These neighbors include (1) the lateral capacitances on the central layer i, from the central conductor to its adjacent segments 4 and 6 on its left and right sides, (2) the three upper crossover capacitances from the central conductor segment 5 on the central layer i to the three conductor segments 1, 2 and 3 on layer i+1 (i.e., the upper layer, "metal 3"), and (3) the three lower crossover capacitances from the central conductor segment 5 on the central layer i to the three conductor segments 7, 8 and 9 on layer i-1 (i.e., the lower layer, "metal 1").

[0065] To train neural network 740, some embodiments use a known set of inputs (e.g., known line structures) and a known set of outputs (e.g., known capacitance coefficients). To generate these known input / output sets, some embodiments use a field resolver method, which will be described below with reference to FIG9. During training, groups of known inputs are rasterized and fed through neural network 740 and post-processed (as shown in FIG7) to generate groups of outputs. The difference between each generated group of outputs and the known outputs of each group of known inputs is an error value, which is passed back through the neural network to train its trainable parameters (e.g., its weights). Some embodiments perform training once for each process technology and then perform the operations of FIG7 to perform one or more extractions during IC design.

[0066] In other embodiments, the capacitance prediction neural network can be trained to directly output the capacitance coefficient values ​​themselves, for example, the output could be the capacitance coefficients (Cl, Ca, Cf, Co, Cu). By this method, the post-processing steps themselves can also be learned by the neural network. Figure 8 illustrates the architecture of a CNN 800 in some embodiments that can be used to directly output capacitance coefficient values.

[0067] In this figure, the three-channel input image 805 is processed by a convolutional base 810, which contains two pairs of convolutional layers 815 and 820 (e.g., each with a 5x5 kernel). Each convolutional layer has a subsequent two-dimensional max-pooling 825 or 830 to downsample the image. Each convolutional layer uses a filter depth of 32. The input image size is 60x60 pixels, where each pixel represents 10 nanometers squared of IC design data. Therefore, each image represents a 600x600 nanometer area of ​​the IC design.

[0068] In the neural network model, the convolutional base 810 is followed by a 16-neuron wide fully connected bottleneck layer 835, which is used to reduce the total number of model parameters. The output of this narrow layer is then fed into a regression network 840, which contains a 100-neuron wide fully connected layer followed by a 9-neuron fully connected output layer.

[0069] All layers except the final output layer use ReLU activation, and all convolutional layers use zero-padding to ensure the output image size is the same as the input image size. Since this is a regression CNN application, the final output layer uses a linear activation function. The final output layer is as wide as the number of capacitances N to be predicted. Once training is complete, in some embodiments, a set of training weights for each process technique is saved for use in the neural network, e.g., capacitance prediction neural network 740. In other embodiments, the final output layer is as wide as the number of capacitance coefficients to be predicted. Those skilled in the art will understand that other embodiments use neural network architectures different from those shown in Figure 8 to generate parasitic parameter values.

[0070] To train a CNN 800 or other neural network to generate parasitic parameter values, some embodiments use a training dataset with known input and output values. These embodiments iteratively (1) feed multiple sets of known input values ​​into the neural network to generate multiple sets of output values, (2) calculate the error between each set of output values ​​and the known output values ​​corresponding to the input values, and (3) backpropagate each computational error value through the neural network to adjust the configurable parameters of the neural network (e.g., its weight values) to reflect the knowledge gained through training.

[0071] Figure 9 illustrates a data flow diagram of the training dataset (X and Y data) required to create a training neural network, such as a 3x3 bus crossover structure. The X training data represents the input to the rasterized line structure, while the Y training data represents the output of the capacitance vector. In this example, several three-layer, two-dimensional rectangular line crossover structures 900 with different linewidths and spacings are generated. Some embodiments use different linewidths, as small as 30 nanometers, with a unit line length of 90 nanometers. Spacing of up to four loop widths is also used because spacing beyond this range is generally considered to cause relatively insignificant changes in capacitance values.

[0072] Image rasterizer 910 performs a rasterization operation on each line structure 900 to produce a two-dimensional image defined for the line structure in a pixel domain. Each two-dimensional image has three channels, each channel containing a layer i representing a first preferred winding direction (e.g., vertical) and layers above and below representing a second preferred winding direction (e.g., horizontal) that are orthogonal. In some embodiments, a pixel size of 10 nanometers is used during rasterization, such that a wire, for example, 30 nanometers wide, appears as 3 pixels wide in the image. Fully filled pixels are represented by a value of 1.0, completely empty pixels by a value of 0.0, and partially filled pixels are represented by a value within the range [0,1] representing the pixel area filled by the wire (e.g., a pixel filled by 50% would have a value of 0.5).

[0073] Each line intersection structure input to the neural network in this manner is rasterized and then fed into an extrusion and mesh simulation process 920, which produces a three-dimensional representation of the structure. As previously described, in order to perform an extrusion operation using the contour definition of the shape, some embodiments convert the definition of the two-dimensional curved shape from the pixel domain to a geometric contour domain defined by the shape's contour definition.

[0074] The resulting three-dimensional representation is suitable for input to the field resolver 925. To create the input representation for the field resolver, the extrusion and mesh simulation process 920 uses two-dimensional line dimensions with various specific line heights and dielectric thicknesses specified in the process technology document 915 used for the process. This causes the two-dimensional line shape to form a three-dimensional volume in the "height" dimension. The process technology information set in the process technology document may include, for example, line height and dielectric information.

[0075] For each generated 3D interconnect volume, some embodiments calculate surface plates. In some embodiments, these plates are simply calculated as rectangles. In more complex embodiments, these plates are calculated by applying a more sophisticated meshing algorithm prior to extrusion, such as that described earlier regarding the shape of the 3D interconnect curves. For example, some embodiments produce triangular or quadrilateral meshes. The surface plates are then inserted above and below the top and bottom layers.

[0076] Then, the field resolver 925 solves for the three-dimensional surface plate representation of the grounding plates added above and below the layer of interest, producing an NxN capacitance matrix, where N is the total number of conductors. For a 3x3 bus crossover structure, there are a total of 9 conductors, and therefore the field resolver will produce a 9x9 matrix with 91 capacitance values. Filter 930 then filters these values ​​to only the main capacitance components of interest, such as, as shown in Figure 16, the self-capacitance of the central layer, the central conductor, and the capacitance between the conductor and each of its 8 neighbors.

[0077] For each candidate geometric line structure, the training data generation process in Figure 9 uses a range of widths and / or spacings to generate sample line structures. Each generated line structure is a known input X. To generate the corresponding known output Y for this input, the training data generation process (1) generates a three-channel rasterized image for each generated line structure, (2) generates a compressed 3D representation of this image, and then (3) generates a filtered capacitance vector output by the field resolver and filter. In accordance with best practices in deep learning, the large number of samples thus generated are divided into a training set (e.g., 80% of the samples) and a validation set (e.g., 20% of the samples).

[0078] Figure 10 shows a data flow diagram of the CNN-based full-capacitance extraction method. The shape of the IC design 1002, which contains two-dimensional layout shapes on multiple layouts, is rasterized by an image rasterizer 1003. The rasterized image (defined in the pixel domain) is then fed as input to a trained curve prediction neural network 1004 running on a GPU / TPU device (for simplicity, the curve shapes of a single corner-specific set are shown in the figure). The neural network 1004 performs a fast inference operation, which generates a set of process corner-specific curve two-dimensional shapes representing what will be fabricated on the substrate at each process corner.

[0079] The curve prediction network can be trained using the method disclosed in U.S. Application Publication No. 2022 / 0128899, which is incorporated above. The resulting wafer shape profile is calculated and stored in database 1006. For each specific set of curved wafer shapes stored in database 1006, the corresponding curved interconnect segments of the lines to be extracted are located through shape tracing process 1008. As shown, this process also uses the original wafer shapes drawn in the IC layout and their corresponding connectivity.

[0080] Process 1008 further divides the curved line segment into sub-segments, each representing a 2T+1 track width length of the interconnect, where T is the number of tracks. In some embodiments, the number of tracks T equals 4, but other embodiments use a different number of tracks (e.g., 5). Each sub-segment is then explored in the X and Y directions of the square region to find the nearest adjacent conductors on the same layer, as well as the upper / lower crossing conductors above and below the interconnect layer within the + / -T tracks of the interconnect of interest.

[0081] In some embodiments, process 1008 generates a square patch three-channel raster image 1012 to represent each interconnect sub-segment, its nearest neighbors in the same layer within the left and right + / -T tracks, and up to 2T+1 upper / lower cross conductors near the upper or lower layers. The capacitance matrix to be inferred will contain 2*(2T+1)+3 slots (e.g., 21 slots for 4 tracks). Each such sub-segment patch is presented as a three-channel two-dimensional image. In other embodiments, the patch image of the intermediate layers captures up to T lateral neighbors on either side of the conductor to be extracted, i.e., not just the two nearest lateral neighbors. In this case, the capacitance matrix to be inferred will contain 3*(2T+1) slots (i.e., 27 slots, nine slots per three layers when using 4 tracks).

[0082] The resulting segment patches representing interconnect segments are then fed into a trained capacitance prediction neural network 1014 that predicts / infers coupling capacitance values. In some embodiments, although the number of outputs differs (e.g., 23 or 27 outputs when using 4 tracks), neural network 1014 has an architecture similar to neural network 800 of FIG. 8. Neural network 1014 calculates all associated capacitances for each segment patch (hereinafter also referred to as segment region). In summary, FIG. 10 includes a first neural network 1004 for generating predicted curve shapes from rasterized images of IC design patterns, and a second neural network 1014 for calculating predicted parasitic capacitances of the curve shapes using a set of process information.

[0083] As shown in the figure, the output of the second neural network 1014 is provided as input to the sub-segment-specific capacitance 1016 of the integration process 1018. For each interconnect segment from the original layout, process 1018 collects the relevant sub-segment-specific capacitance of the segment and integrates all relevant sub-segment blocks. This process adds the calculated capacitances together based on interconnect connectivity. This integration will be further described below with reference to Figure 11. Process 1018 outputs the integrated capacitance values ​​of all interconnects to a standard parasitic format 1020, such as a DSPF / SPEF file, or a Synopsys GPD file, for example.

[0084] Figure 11 provides an example illustrating the tiled and rasterized processes used in some embodiments. This example illustrates the curved shapes of fabricated conductors of interest. In this example, the method extracts the capacitance with respect to the central vertical conductor 1102 on layer "1 / 0" of the design. Intuitively, conductor 1102 will have large lateral capacitances to its left and right same-layer neighbors 1104 and 1106, which extend substantially parallel to conductor 1102 despite having different spacing. Conductor 1102 will also have edge / overlap capacitances to the shapes on the upper layer (layer "2 / 0" of the design) and the lower layer (layer "0 / 0" of the design).

[0085] Therefore, in some embodiments, the tiled process divides the vertical conductor 1102 into multiple segments. In this embodiment, the tiled process produces three tiles 1112, 1114, and 1116, each containing a portion of the central vertical conductor. Each tile also contains two nearest-neighbor lateral conductor segments on the same layer. Furthermore, the conductor shapes within the four track windows also appear on the top and bottom orthogonal winding layers.

[0086] Then, each three-layer tile from the tiled process is rasterized into a three-channel, two-dimensional 60x60 pixel raster image 1120 with 10 nanometer pixels. Figure 11 shows the three-channel image of tile 1112. Here, the three-channel image is individually decomposed such that each channel image 1122-1126 displays pixels representing interconnect segments in the corresponding interconnect layers.

[0087] During the inference process, a three-channel two-dimensional patch raster image is input to a capacitance prediction convolutional neural network 1014, and up to 27 capacitance values ​​are predicted for each of the three patches. These values ​​represent the self-capacitance of the central conductor in the central layer, its coupling capacitance to conductors in laterally adjacent tracks, and its coupling capacitance to each upper / lower crossing track appearing in the top / bottom channels of the patch image. As previously stated, for the example described in Figure 10, a number other than 27 may be used in other embodiments.

[0088] After inference, the capacitances generated by all the tiles are then summed, i.e., summed together according to the connectivity of the interconnections. For example, in order to obtain the sum of the self-capacitances of each corner of the central vertical conductor 1102 on layer "1 / 0", the self-capacitances of the central conductors of each of the three tiles 1112-1116 are summed.

[0089] Figure 12 illustrates the process of generating training data for training neural networks using tile-based capacitance extraction. In this example, various multi-layer (e.g., three-layer) two-dimensional interconnect structures suitable for containing NxN squares, such as 9x9 track slots, are generated. This structure is stored in IC design database 1202 and divided into its individual layers. Image rasterizer 1204 then rasterizes the contents of each layer into a single-channel two-dimensional image, and then combines the individual layers across the three layers into a three-channel two-dimensional image.

[0090] These raster images are then consumed by curve prediction neural network 1206. An example of such a neural network is one of the aforementioned neural networks or one disclosed in U.S. Application Publication No. 2022 / 0128899. This neural network 1206 outputs curve images 1210 corresponding to the outputs of each process corner. Curves of the three interconnect layers for each process corner are collected for the two-dimensional wafer shape and provided to the extrusion process 1212.

[0091] This process 1212 uses the layer-specific line height and dielectric information in process technology document 1214 to extrude the curved two-dimensional wafer shape into three dimensions, and inputs the resulting three-dimensional interconnect structure into field resolver 1216. The field resolver generates an NxN capacitance matrix 1218 as output for each process corner, which is then filtered by filter 1222 to obtain the capacitance of interest, namely the coupling capacitance between the center conductor of the central layer of interest and the conductors on the other tracks of all three layers.

[0092] For each interconnect architecture sample, three-channel two-dimensional curve image patches of each corner used as the output of the curve shape prediction neural network 1206 and the corresponding corner capacitance vectors output by the filter 1222 are collected as input X and output Y, respectively, for use when training the capacitance prediction neural network.

[0093] During the creation of a two-dimensional, three-layer structure, each structure may contain line segments of various lengths appearing at any available track location. Conductors may extend to the entire width or height of the tile, or to a portion of its width or length. In some embodiments, conductors are placed at available track locations using a set range of line lengths. For any track location other than the central conductor of the central layer, conductor lengths may be as short as zero, meaning there may be no conductor at a particular track location. Non-zero conductor lengths may be very short (e.g., one track width) or extend to the entire track width of the structure. The start / end position of each conductor within its track can also be located to a set range of positions, such as a winding track intersection.

[0094] Some embodiments allow sampling of the training space in a structured grid-like manner. In other embodiments, a Monte Carlo method is used to fill the training space. Here, the start and end positions of each conductor are randomly generated for each track. Again, the line length at any track position (except for the central conductor of the central layer) may be as short as zero. Training samples with empty track positions are assigned a capacitance value of 0 at those positions, and the resolver generates capacitance values ​​for non-empty positions.

[0095] Figure 13 illustrates the training dataset used in some embodiments to train neural networks that generate parasitic capacitance values. As shown, these embodiments use the line shape of curves as the input value for each training set and the known capacitance value associated with the line shape of these curves as the output value for each training set. A set of training weights reserved for each process technology is generated using training samples based on a set of process technology information.

[0096] Figure 14 illustrates an example of a computing hardware device 1400 for performing the operations described herein. The computing hardware device 1400 includes a central processing unit (CPU) 1402 connected to main memory 1404. The CPU may include, for example, eight processing cores, thereby improving the performance of any part of the multitasking threaded computer software. The size of main memory 1404 may be, for example, 64 gigabytes. The CPU 1402 is connected to a high-speed peripheral component interconnect (PCIe) bus 1420. A graphics processing unit (GPU) 1414 is also connected to the PCIe bus. In the computing hardware device 1400, the GPU 1414 may or may not be connected to a graphics output device such as a video monitor. If not connected to a graphics output device, the GPU 1414 can be used purely as a high-speed parallel computing engine. Compared to using the central processing unit 1402 to handle all the calculations, the computing software can achieve significantly higher performance by using the graphics processing unit (GPU) to handle a portion of the calculations. The central processing unit 1402 communicates with the GPU 1414 via PCIe bus 1420. In other embodiments (not shown), the GPU 1414 may be integrated with the central processing unit 1402 instead of being connected to the PCIe bus 1420. A disk controller 1408 may also be connected to the PCIe bus, where, for example, two disks 1410 are connected to the disk controller 1408. Finally, a local area network (LAN) controller 1412 may also be connected to the PCIe bus, providing Gigabit Ethernet (GbE) connectivity to other computers. In some embodiments, the computer software and / or design data are stored on disk 1410. In other embodiments, the computer program or the design data, or both the computer program and the design data, may be accessed from other computers or file service hardware via GbE Ethernet.

[0097] Figure 15 illustrates another embodiment of a system for performing the computations described in this embodiment. System 1500, also referred to as CDP, includes a master node 1510, an optional view node 1520, an optional network file system 1530, and GPU-enabled computing nodes 1540. View node 1520 may be absent or have only one node, or may have other numbers of nodes. GPU-enabled computing nodes 1540 may comprise one or more GPU-enabled computing nodes forming a cluster. Each GPU-enabled computing node 1540 may include, for example, a GPU, a CPU, a pair of GPUs and CPUs, multiple GPUs for a CPU, or other combinations of GPUs and CPUs. The GPU and / or CPU may reside on a single chip, such as a GPU chip with a CPU accelerated by a GPU on that chip, or a CPU chip with a GPU accelerating a CPU. The GPU may be replaced by another coprocessor.

[0098] Master node 1510 and view node 1520 can be connected to network file system 1530 and GPU-enabled compute node 1540 via switches and high-speed networks, such as networks 1550, 1552, and 1554. In one example embodiment, network 1550 may be a 56Gbps network, network 1552 may be a 1Gbps network, and network 1554 may be a management network. In various embodiments, there may be fewer or more of these networks, and there may be combinations of network types such as high-speed and low-speed. Master node 1510 controls CDP 1500. External systems can connect to master node 1510 from external network 1560. In some embodiments, a job can be started from an external system. Data for the job is loaded into network file system 1530 before the job is started, and a program is used to dispatch and monitor tasks on GPU-enabled compute node 1540. The progress of the task can be viewed through a graphical interface, such as node 1520, or by a user on master node 1510. The CPU uses a script that runs an appropriate executable on the CPU to perform the task. The executable connects to the GPU, runs various computational tasks, and then disconnects from the GPU. Master node 1510 can also be used to disable any faulty GPU-enabled compute node 1540 and then operate as if that node does not exist.

[0099] Although the specification has been described in detail with reference to specific embodiments, it should be understood that those skilled in the art will readily conceive of alternatives, variations, and equivalents to these embodiments upon understanding the foregoing. These and other modifications and variations to the method can be implemented by those skilled in the art without departing from the scope of the invention as specifically described in the appended claims. For example, even if some embodiments use the described curved shape, one skilled in the art will understand that straight lines or arbitrary shapes are used to represent the design in other embodiments.

[0100] Furthermore, those skilled in the art will understand that the foregoing description is merely illustrative and not intended to be limiting. Steps in the specification may be added, omitted, or modified without departing from the scope of the invention. Generally, any illustrated flowchart is intended only to represent one possible sequence of basic operations to achieve the function, and many variations are possible. Therefore, the subject matter of this invention is intended to cover such modifications and variations falling within the scope of the appended claims and their equivalents.

[0101] 1-9: Conductor segment 200: Busbar Structure 300: Two-dimensional circuit line structure 302: Extrusion process 304: Field Resolver 306: Capacitor Matrix 308: Filtering process 364: Capacitance value 420: Busbar Cross Structure 425: Busbar Cross Structure 500: Line 600: Two-dimensional shape 605:RET 610: Curved shape 615: Semiconductor Manufacturing Process Model 616: 3D Extrusion and Meshing Process 618: Process Technology Document 620: Three-dimensional shape 622: Field Resolver 624: Capacitance value 650: Neural Networks 652: Two-dimensional shapes 654: Two-dimensional curve shape 656: 3D Extrusion and Meshing Process 658: Process Technology Document 660: Three-dimensional shape (three-dimensional surface mesh) 662: Field Resolver 700: Non-geometric methods 710: Line Structure 720: Image Rasterization 730: Multi-channel 2D images 740: Neural Networks 750: Capacitor Vector (Capacitor Vector Value) 755: Post-processor 760: Capacitance coefficient 800:CNN 805: Three-channel input image 810: Convolutional basis 815: Convolutional Layer 820: Convolutional layer 825: Two-dimensional maximum pool 830: Two-dimensional maximum pool 835: Fully Connected Bottleneck Layer 840: Return to the Internet 900: Two-dimensional rectangular line intersection structure (line structure) 910: Image rasterizer 920: Extrusion and Mesh Simulation Process 925: Field Resolver 930: Filter 1002: IC Design 1003: Image rasterizer 1004: Neural Networks 1006: Database 1008: Manufacturing Process 1012: Square tile three-channel raster image 1014: Neural Networks 1016: Specific Capacitor of Sub-block 1018: Manufacturing Process 1020: Standard Parasitic Format 1102: Conductor 1104: Neighbor 1106: Neighbor 1112: Tile 1114: Tile 1116: Tile 1120: pixel raster image 1122-1126: Channel Images 1202: IC Design Database 1204: Image rasterizer 1206: Neural Networks 1210: Curve images of each process angle 1212: Manufacturing Process 1214: Process Technology Document 1216: Field Resolver 1218: NxN Capacitor Matrix 1222: Filter 1400: Computing Hardware Structure 1402: Central Processing Unit 1404: Main Memory 1408: Disk Controller 1410: Disk 1412: Local Area Network Controller 1414: Graphics Processing Unit 1420: PCIe Bus 1500: System (CDP) 1510: Master Node 1520: View Nodes 1530: Online Archive System 1540: Computing Node 1550: Network 1552: Internet 1554: Internet 1560: External Network S: Spacing Sc: Spacing W: Width W': Width Wc: Line width

Claims

1. A method for calculating parasitic parameters of a line structure defined in a semiconductor design, comprising: generating a second line structure for a first line structure in the semiconductor design, the first line structure comprising a plurality of straight line shapes, the second line structure comprising a plurality of curved shapes; and generating a set of parasitic parameters using the second line structure, the set of parasitic parameters being associated with a set of parasitic effects caused by at least one wire in the first line structure in the semiconductor design.

2. The method of claim 1, wherein the second line structure having the curved shapes is a structure to be predicted once the first line structure is fabricated, and thus the structure is a predicted fabrication structure of the first line structure.

3. The method of claim 1, wherein the step of generating the second line structure includes providing the first line structure to a machine training network to generate the second line structure.

4. The method as described in claim 3, wherein the machine training network is a neural network having a plurality of machine training neurons.

5. The method of claim 1, wherein the step of generating the second line structure comprises using a software simulator to generate the second line structure as a predictive fabrication structure of the first line structure.

6. The method of claim 1, wherein the first line structure comprises a plurality of two-dimensional shapes, the method further comprising: receiving a process technology information set associated with the semiconductor design; using the process technology information set to generate a plurality of three-dimensional shapes for the second line structure; and providing the three-dimensional shapes to a field resolver to generate the parasitic parameters.

7. The method as described in claim 6, wherein the process technology information group includes wire height and dielectric thickness.

8. The method of claim 6, wherein the parasitic parameter is a parasitic coefficient, the method further comprising: extracting the first line structure from the semiconductor design; rasterizing the first line structure to generate a pixel-based definition of the first line structure; providing the pixel-based definition to a machine training network to generate the second line structure; calculating a plurality of parasitic coefficients based on the three-dimensional shapes; and calculating a parasitic value using the generated parasitic coefficients, the parasitic value representing a parasitic effect of at least one conductor of the first line structure.

9. The method of claim 6 further comprises: extracting the first line structure from the semiconductor design; rasterizing the first line structure to generate a pixel-based definition of the first line structure; and providing the pixel-based definition to a machine training network to generate the second line structure.

10. The method of claim 1, wherein the straight line shapes comprise shapes generated using straight line segments, and the curved shapes are shapes generated by at least one curved segment.

11. A machine-readable medium storing a program, wherein when the program is implemented by at least one processing unit, the program implements the method as described in any one of claims 1 to 10.

12. An electronic device for calculating parasitic parameters of a line structure defined in a semiconductor design, comprising: a set of processing units; and a machine-readable medium storing a program, wherein when the program is implemented by at least one of the processing units, the program implements the method as described in any one of claims 1 to 10.

13. A system for calculating parasitic parameters of a line structure defined in a semiconductor design, the system comprising means for implementing the method as described in any one of claims 1 to 10.

14. A computer program product comprising a plurality of instructions, wherein when the instructions are executed by a computer, the computer performs the method as described in any one of claims 1 to 10.

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