Processor-based system employing configurable local frequency throttling management to manage power demand and consumption, and related methods

Abstract

This document discloses processor-based systems and related methods employing configurable local frequency throttling management to manage power demand and consumption. For example, such a processor-based system may include a processor and other power circuitry to control the processor's power. The processor includes clock control circuitry configured to generate (i.e., limit and / or reduce) the frequency of (i.e., restrict and / or reduce) the clock signals providing the processor in response to frequency-limiting events that may be unexpected. Reducing power demand can be important to ensure the processor can continue operating under interrupted or reduced power supply conditions. Limiting the processor's operating frequency may be faster than limiting the operating voltage supplying power to the processor.

Description

Technical Field

[0001] The technology of this application relates to the control of power requirements and power consumption in processing units such as central processing units (CPUs) in processor-based systems (including system-on-a-chip (SoC)). Prior Technology

[0002] A data center is an integral part of an enterprise system used to support computer business applications and provide computer-related services. Data centers can provide cloud-based computer services, including data storage, data management, and software application hosting. Data centers can also be used to execute big data applications, such as machine learning and artificial intelligence applications. A data center includes storage systems, computer servers, and associated network infrastructure to facilitate communication with the computer servers. For example, Figure 1A shows a data center 100, which includes "M" server racks 102(1)-102(M). In this example, each server rack 102(1)-102(M) is configured to accommodate "N" processor-based systems 104(1)(1)-104(M)(N). Each processor-based system 104(1)(1)-104(M)(N) is set up in the form of a printed circuit board (PCB), sometimes referred to as a "card" or "blade". Figure 1B shows a server rack 102 in the data center 100 of Figure 1A. As shown in Figure 1B, a processor-based system 104 is supported in a corresponding chassis device 106; the chassis device 106 may be in the form of a device tray installed in corresponding slots 108(1)-108(N) of the server rack 102. The processor-based system 104 is communicatively coupled in the data center 100 via a backplane interface connector 110; when the processor-based system 104 is fully installed in the corresponding slots 108(1)-108(N) of the server rack 102, the backplane interface connector 110 is connected to the backplane connector 112 of the processor-based system 104.

[0003] A processor-based system (such as processor-based system 104 in Figures 1A and 1B) is mounted on a blade or card as an integrated circuit (IC) including one or more central processing units (CPUs). For example, the processor-based system can be configured as a computer server or as a dedicated processor-based system to execute specific applications and tasks depending on the application. The CPU mounted on the blade or card in a processor-based system can be a single-processor core ("core") CPU or a multi-core CPU. The CPU can be mounted on an IC chip that is a system-on-a-chip (SoC), which also includes other supporting components such as memory, interface circuitry, modems, etc., located on the same semiconductor die and IC chip.

[0004] As mentioned above, data centers are particularly useful for supporting a large number of processor-based systems to support applications and workloads. For processor-based systems to deliver high performance, they require significant power consumption to operate at higher frequencies. The need for CPUs in a processor-based system to operate at higher frequencies depends on the workloads being executed and the performance required to perform those workloads. However, the power that can be consumed by processor-based systems in a data center may be limited by the capacity and distribution of the data center's power distribution system. For example, a data center may be able to allocate power to each of its processor-based systems based on a fixed power budget established for each system. The workloads of the processor-based systems can be well-known, allowing for the establishment of a fixed power budget and the achievement of the desired performance by the processor-based systems.

[0005] The power availability of processor-based systems can change abruptly, impacting performance. For example, changes in uninterruptible power supplies (UPS) reduce the power available for consumption by a processor-based system. Furthermore, as another example, voltage regulation circuitry in a processor-based system may limit power consumption for various reasons. As yet another example, a processor-based system may automatically limit power based on thermal considerations, entering a low-power state to reduce heat dissipation when temperatures exceed defined thresholds. This affects power distribution within the processor-based system, thus impacting CPU performance. A sudden drop in available power to the processor in a processor-based system can lead to so-called "di / dt" problems, which can cause undervoltage (brown-out) conditions in the processor, resulting in operational interruptions. Because power delivery systems have significant parasitic inductance, current changes caused by sudden power fluctuations can create voltage ripples on the processor's power lines. This is important because if the supply voltage rises or falls below certain tolerance ranges, the processor may malfunction. The amplitude of these voltage ripples is affected by instantaneous changes in current over time. Summary of the Invention

[0006] The exemplary embodiments disclosed herein include processor-based systems that employ configurable local frequency limiting management to manage power requirements and consumption. Related methods are also disclosed. For example, such a processor-based system may include a system-on-a-chip (SoC) comprising a processor and other power circuitry to control the power supplied to the processor. The processor includes clock control circuitry configured to generate clock signals at specified frequencies to clock (multiple) processor cores (multiple) within the processor at desired operating frequencies. Such processor-based systems may be included as printed circuit boards (PCBs) on cards or blades, which may be mounted in equipment racks in data centers for executing large, data-intensive workloads and applications. In the exemplary embodiments disclosed herein, the clock control circuitry is configured to dynamically throttle (i.e., limit and / or reduce) the frequencies of (multiple) clock signals (multiple) supplying clock to the processor in response to a frequency limiting event (which may be an unexpected event). A frequency throttling event is an event that indicates a potential need to reduce and / or limit the frequency of the clock signal supplying the processor to decrease power requirements and consumption. Reducing power requirements can be critical to ensure the processor can continue operating under potential interruptions or reduced power conditions. Limiting the processor's operating frequency reduces power requirements and consumption more quickly than limiting the operating voltage supplying power to the processor. An example of such a frequency throttling event might be an internally detected thermal condition exceeding or approaching a maximum temperature threshold that could degrade processor performance. Another example might be an external power condition indicating reduced power availability, which could affect the processor's ability to operate normally at its current operating frequency. If power requirements are not reduced to operating limits based on available power and / or thermal requirements, the processor may experience a "di / dt" problem, leading to performance degradation or malfunction.

[0007] In an exemplary configuration, clock control circuitry can be housed in the same integrated circuit (IC) wafer and / or semiconductor die as the processor core. The clock control circuitry can be configured (e.g., via an interrupt) to directly receive notification of a frequency limiting event to reduce the frequency of (multiple) clock signals providing clock to the processor without incurring additional latency controlled by the processor core or other processing circuitry. This can be important for the processor to reduce its power requirements more quickly to avoid interrupting operation in response to reduced power availability. The clock control circuitry can be configured to reduce and / or limit the frequency of (multiple) generated clock signals in response to a frequency limiting event, based on frequency settings programmed at manufacturing time and / or adjusted at installation time. Alternatively, power control circuitry can be configured as the processor core within the processor; for example, the power control circuitry executes computer program code based on a power budget that does not respond to frequency limiting events to cause the clock control circuitry to adjust (i.e., increase or decrease) the frequency of (multiple) clock signals. The power control circuit can also be configured to execute computer program code to set or adjust the settings of the reduced (multiple) frequencies accessible by the clock control circuit, thereby limiting the frequency of (multiple) clock signals. In this way, the reduced frequency of the clock signal can be programmed and changed as needed through the clock control circuit to gain flexibility and achieve further fine-tuning control for improved power consumption efficiency.

[0008] In a further exemplary embodiment, the voltage level supplied to the processor can also be reduced after the frequency of the clock signal is reduced, thereby reducing the processor's power requirements. The clock control circuit can also be configured to gradually limit the frequency of the clock(s) providing the clock to the processor in response to an incrementally stepped frequency limiting event. For example, the clock control circuit can be configured to gradually reduce the frequency of the clock(s) providing the clock to the processor, thereby gradually reducing the processor's operating frequency. Gradually reducing the processor's operating frequency over time to avoid or reduce the "di / dt" problem in the processor can be important. In this regard, in the exemplary embodiment, the clock control circuit may include a finite state machine (FSM) circuit configured to control the generation of clock(s) at desired frequencies in incremental steps. The clock control circuit may also include a clock generation circuit (e.g., a phase-locked loop (PLL) circuit) to generate clock signals at a desired limiting frequency, and to provide feedback in a closed-loop manner when the frequency of the clock signals has stabilized at a new set frequency, to control the hysteresis effect of the frequency of the clock signals when they change. When the new frequency of the clock signals stabilizes, the clock control circuit may notify the power control circuit, which then allows the processor to be clocked by the clock signals at the new frequency. Thus, in one example, the processor core halts and stalls until the clock signals stabilize at their new frequency. In another exemplary case, to avoid the need to stall the processor in response to the frequency limitation of the clock signals, the clock control circuit may include, for example, two (2) or more PLL circuits. A clock selection switch may be set and controlled by the clock control circuit to alternate between selections of the clock outputs of each PLL circuit to provide the selected clock signal as the new limiting clock signal to clock the processor. In this way, when one PLL circuit stabilizes its clock signal to a new reduced frequency until it is released to provide a clock signal for the processor, the processor can continue to operate based on a stable clock signal generated by another PLL circuit.

[0009] In this regard, in one exemplary embodiment, a processor-based system is provided. The processor-based system includes clock control circuitry configured to generate a clock signal at a current frequency on a clock output. The processor-based system also includes a processing unit comprising at least one computing processor core, each computing processor core coupled to a clock output, each clock output configured to execute program code at a rate based on the current frequency of the clock signal as the operating frequency. The processor-based system also includes a frequency-limiting memory configured to store the frequency limit. The clock control circuitry is configured to receive a frequency-limiting signal indicating a frequency-limiting event. In response to receiving the frequency-limiting signal indicating a frequency-limiting event, the clock control circuitry is also configured to generate a clock signal at a frequency lower than the current frequency, which is accomplished by generating a clock signal at a next intermediate frequency between the current frequency and the limit frequency on the clock output and verifying the clock signal at the next intermediate frequency. In response to verifying the clock signal at the next intermediate frequency, the clock control circuit is configured to repeat the generation of the clock signal at the next intermediate frequency and verify the clock signal at the next intermediate frequency one or more times until the next intermediate frequency is the limit frequency.

[0010] In another exemplary embodiment, a method for limiting the operating frequency of a processor in a processor-based system is provided. The method includes the steps of: generating a clock signal at the current frequency on a clock output. The method also includes the steps of: executing program code at a rate based on the current frequency of the clock signal in a processing unit including at least one computing processor core that receives the clock signal. The method also includes the steps of: receiving a frequency limiting signal indicating a frequency limiting event. The method also includes the steps of: in response to receiving the frequency limiting signal indicating a frequency limiting event, generating a clock signal at a limiting frequency lower than the current frequency by (a) generating a clock signal at a next intermediate frequency between the current frequency and the limiting frequency on the clock output, and (b) verifying the clock signal at the next intermediate frequency. The method also includes the steps of: in response to verifying the clock signal at the next intermediate frequency, repeating steps (a)-(b) once or more until the next intermediate frequency is the limiting frequency.

[0011] After reading the following description of preferred embodiments in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this application and implement its additional forms. Simple Explanation of the Diagram

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate several aspects of this application and, together with the description herein, serve to explain the principles of this application.

[0013] Figure 1A is a view of an exemplary data center, which includes server racks, each server rack including computer systems, and each computer system including a processor-based system on a circuit board;

[0014] Figure 1B is a more detailed view of an exemplary computer system mounted in a server rack, the server rack including a processor-based system mounted on a circuit board and interconnected with a signal and power backplane for external communication and power supply;

[0015] Figure 2 is a block diagram of an exemplary processor-based system. The exemplary processor-based system includes a clock control circuit configured to locally limit the frequency of (multiple) clock signals that provide a clock to the processor, thereby limiting the processor's (multiple) operating frequencies in response to a frequency limiting event, and thus limiting the processor's power requirements.

[0016] Figure 3 is a flowchart illustrating an exemplary process of the processor-based system in Figure 2, which in response to self-limiting and frequency-limiting events self-limits the operating frequencies of the processor(s), thereby limiting the processor's power requirements;

[0017] Figure 4 is a block diagram of an exemplary phase-locked loop (PLL) system that can be used in the clock control circuit of the processor-based system in Figure 2 and is configured to select a clock signal generated by one of a plurality of PLL circuits used to provide a clock to the processor.

[0018] Figure 5 is an exemplary communication flow for a thermal shutdown frequency limiting event in the processor-based system shown in Figure 2;

[0019] Figure 6 is an exemplary communication flow for a self-limiting frequency limiting event in the processor-based system shown in Figure 2;

[0020] Figure 7 is an exemplary communication flow for external frequency limiting events in the processor-based system shown in Figure 2;

[0021] Figure 8 is a flowchart illustrating a more detailed exemplary flow of the power control circuitry in the processor-based system of Figure 2. This power control circuitry monitors the power requirements of the processor-based system and manages the power requirements locally by dynamically adjusting the operating frequency and / or the operating voltage supplied to the processor-based system within a predetermined power budget.

[0022] Figure 9 is an exemplary voltage-frequency table, which can be stored in the processor in Figure 2 and accessed by the power control circuitry therein to determine a new operating voltage and corresponding operating frequency as a voltage-frequency for controlling the power requirements of a processor-based system;

[0023] Figure 10 is a flowchart illustrating a more detailed exemplary flow of the power control circuitry in the processor-based system of Figure 2. This power control circuitry monitors the power requirements of the processor-based system and locally manages the power requirements by dynamically adjusting the operating frequency and / or the operating voltage supplied to the processor-based system within a predetermined power budget; and

[0024] Figure 11 is a block diagram of an exemplary processor-based system, which includes a processor having one or more processor cores, each processor core configured to execute computer instructions for execution. The processor-based system further includes clock control circuitry configured to, in response to a frequency limiting event, locally limit the frequencies of (multiple) clock signals provided to the processor to limit the processor's (multiple) operating frequencies, thereby limiting the processor's power requirements. The processor includes, but is not limited to, the processor-based systems shown in Figures 2, 3, 6, and 8. Implementation

[0025] The exemplary embodiments disclosed herein include processor-based systems that employ configurable local frequency limiting management to manage power requirements and consumption. Related methods are also disclosed herein. For example, such a processor-based system may include a system-on-a-chip (SoC), which includes a processor and other power circuitry to control the power supplied to the processor. The processor includes clock control circuitry configured to generate multiple clock signals of a specified frequency to clock multiple processor cores within the processor at multiple desired operating frequencies. Such a processor-based system may be included as a printed circuit board (PCB) on a card or blade, which may be mounted in a data center rack for executing large data-intensive workloads and applications. In the exemplary embodiments disclosed herein, the clock control circuitry is configured to dynamically throttle (i.e., limit and / or reduce) the frequency of the multiple clock signals supplying the processor in response to a frequency limiting event (which may be an unexpected event). A frequency throttling event is an event that indicates a potential need to reduce and / or limit the frequency of the clock signal supplying the processor to decrease power requirements and consumption. Reducing power requirements is important to ensure the processor can continue operating under potential interruptions or reduced power conditions. Limiting the processor's operating frequency reduces power requirements and consumption more quickly than limiting the operating voltage supplied to the processor. An example of such a frequency throttling event might be an internally detected thermal condition exceeding or approaching a maximum temperature threshold that could degrade processor performance. Another example might be an external power condition indicating reduced power availability, which could affect the processor's ability to operate normally at its current operating frequency. If power requirements are not reduced to operating limits based on available power and / or thermal requirements, the processor may experience a "di / dt" problem, leading to performance degradation or malfunction.

[0026] In an exemplary configuration, clock control circuitry can be housed in the same integrated circuit (IC) wafer and / or semiconductor die as the processor core. The clock control circuitry can be configured to directly receive (e.g., via an interrupt) notification of a frequency limiting event to reduce the frequency of (multiple) clock signals providing clock signals to the processor without incurring additional latency controlled by the processor core or other processing circuitry. This can be important for the processor to reduce its power requirements more quickly to avoid interrupting operation in response to reduced power availability. The clock control circuitry can be configured to reduce and / or limit the frequency of (multiple) generated clock signals in response to a frequency limiting event, based on frequency settings programmed at manufacturing time and / or adjusted at installation time. Alternatively, power control circuitry can be provided as the processor core within the processor; for example, the power control circuitry executes computer program code to adjust (i.e., increase or decrease) the frequency of (multiple) clock signals based on a power budget that does not respond to a frequency limiting event. The power control circuit can also be configured to execute computer program code to set or adjust the settings of the reduced (multiple) frequencies accessible by the clock control circuit, thereby limiting the frequency of (multiple) clock signals. In this way, the reduced frequency of the clock signal can be programmed and changed as needed through the clock control circuit to gain flexibility and achieve further fine-tuning control for improved power consumption efficiency.

[0027] In this regard, Figure 2 is an exemplary block diagram of a processor-based system 200. The processor-based system 200 includes clock control circuitry 202. As discussed in more detail below, clock control circuitry 202 is configured to dynamically throttle (i.e., limit and / or reduce) the frequency of multiple clock signals CLK generated on clock output 204, which provides a clock signal to processor 206, in response to a frequency limiting event that may be an unexpected event. A frequency limiting event 208 is an event indicating that throttling (i.e., reducing and / or limiting) the frequency of the clock signal CLK providing a clock signal to processor 206 may be necessary to reduce the power demand and consumption of processor 206. Reducing the power demand of processor 206 in processor-based system 200 can be important to ensure that processor 206 can continue to operate under possible interruptions or reduced power conditions. Limiting the operating frequency of processor 206 can reduce the power demand and consumption of processor 206 more quickly than limiting the operating voltage to which power is supplied to processor 206. As discussed in more detail below, one example of this frequency limiting event 208 might be a thermal condition detected internally by the temperature monitoring circuit 210, which could reduce the performance of the processor 206. Another example of the frequency limiting event 208 could be an external power condition indicating reduced power availability, which could affect the processor 206's ability to operate correctly at its current operating frequency.

[0028] If power requirements are not reduced to within operating limits based on available power and / or thermal requirements, the processor may encounter a "di / dt" problem, which can lead to performance degradation or malfunction. The "di / dt" problem is a current variation caused by sudden power changes, which generates voltage ripples on the power lines of processor 206. The amplitude of these voltage ripples is affected by the instantaneous change in current (di) relative to time (dt). When the power supplied to processor 206 suddenly decreases, this can lead to an undervoltage (brown-out) condition in processor 206, resulting in operational interruption or malfunction.

[0029] Referring to Figure 2, the processor-based system 200 can be deployed as a board or blade mounted in a server or equipment rack in a data center, such as data center 100 in Figures 1A and 1B. In Figure 2, the processor-based system 200 includes a processor 206; the processor 206 is configured as an integrated circuit (IC) 212 mounted to a board 214 such as a printed circuit board (PCB). Exemplary components of the processor-based system 200 will now be described. An exemplary operating mode of the clock control circuit 202 will then be discussed starting with Figure 3, in which the processor 206 limits the operating frequency of the clock signal CLK supplied to the processor-based system 200 in response to a frequency limiting event 208, in order to control the power requirements and consumption of the processor 206.

[0030] Referring to Figure 2, the processor 206 of the processor-based system 200 includes a processing unit 216 (e.g., a central processing unit (CPU) or a general-purpose processing unit (GPU)), which may include one or more processor cores 218(1)-218(C). The processor cores 218(1)-218(C) are configured to execute computer program code at a rate based on the operating frequency FO of a clock signal CLK generated on clock output 204 by clock control circuitry 202. For example, processor core 218(1) is shown as computation processor core 220, which is configured to execute computer program code 222 ("program code 222") in memory 223 to perform computations of an application. In this example, as discussed in more detail starting from Figure 10, one of the processor cores 218(1)-218(C), processor core 218(C) is a power control circuit 226, which can also be configured to dynamically adjust the operating frequency and / or operating voltage of the power signal 224 provided to the processor-based system 200 within a predetermined power budget. As an example, the processing unit 216 and memory 223 can be integrated into a single IC chip 228 as a system-on-a-chip (SoC) 230. Clock control circuitry 202 is included on the same IC chip 228 as the processing unit 216. This provides greater flexibility for the clock control circuitry 202 in receiving and providing information in the processor 206 (e.g., via interrupts and registers) to limit the frequency FO of the clock signal CLK in response to a frequency limiting event 208.

[0031] Referring again to FIG. 2, processor 206 further includes clock control circuitry 202, configured to generate a clock signal CLK at a set frequency FO to provide a clock signal to processor 206. For example, clock control circuitry 202 may include phase-locked loop (PLL) circuitry 232 configured to adjust the frequency FO of clock signal CLK in a closed-loop feedback manner. Clock control circuitry 202 is configured to limit the frequency FO of clock signal CLK based on a frequency limiting event 208. In the exemplary processor 206 of FIG. 2, as discussed in more detail below, clock control circuitry 202 includes finite-state finite-mode (FSM) circuitry 234. FSM circuitry 234 is configured to control PLL circuitry 232 to generate clock signal CLK at a desired operating frequency, which may be a limiting frequency or another operating frequency controlled by power control circuitry 226, as discussed in more detail below. The clock control circuit 202 in this example includes a frequency stepping circuit 236, which is configured to incrementally increase or decrease the operating frequency FO of the clock signal CLK. This allows the operating frequency FO of the clock signal CLK to stabilize to a new operating frequency over time, thereby controlling the hysteresis (i.e., delay) effect of the operating frequency FO of the clock signal CLK when it changes. This is accomplished in contrast to drastically changing the operating frequency FO of the clock signal CLK to a new operating frequency in a single action or step.

[0032] Clock control circuit 202 is configured to receive a frequency limiting event 208, which indicates that the frequency FO of clock signal CLK will be limited. For example, frequency limiting event 208 can be in the form of an interrupt, which is generated and transmitted to processor 206 and clock control circuit 202. Temperature monitor circuit 210 is configured to generate a frequency limiting signal 238 indicating frequency limiting event 208 in response to a detected ambient temperature exceeding a defined threshold temperature. For example, frequency limiting event 208 can be generated in frequency limiting signal 240 by an external device such as power management circuitry (PMC) 242, which is configured to cause clock control circuit 202 to limit the frequency FO of clock signal CLK. As another example, frequency limiting event 208 can be generated by temperature monitor circuit 210 as a result of a measured temperature exceeding or approaching a defined threshold temperature, which may cause processor 206 to degrade performance and / or malfunction in an undesirable manner. If the measured temperature is only close to but does not exceed the defined threshold temperature, the clock control circuit 202 can be configured to reduce and self-limit the frequency FO of the clock signal CLK to reduce the power demand of the processor 206, thereby lowering it to a temperature suitable for continued operation. However, if the measured temperature exceeds the defined threshold temperature, the clock control circuit 202 can be configured to shut down the operation of the processor 206 by gradually reducing the frequency FO of the clock signal CLK until a limit frequency is reached, and then shut down and reset the processor 206. The temperature monitoring circuit 210 can be located in and / or near the IC chip 228 to detect the ambient temperature of the processor 206.

[0033] In this example, clock control circuit 202 is configured to generate a clock signal CLK at the current frequency F0 on clock output 204 to provide a clock for processor 206 (block 302 in FIG. 3). Processor 206 is configured to execute program code 222 at a rate based on the current frequency FO of clock signal CLK in a processing unit 216 including at least one computing processor core 220 that receives clock signal CLK (block 304 in FIG. 3). Clock control circuit 202 is configured to receive frequency limiting signals 238, 240, which indicate that frequency limiting event 208 can respond quickly to instructions to limit the frequency FO of clock signal CLK (block 306 in FIG. 3). In response to receiving frequency limiting signals 238, 240 indicating frequency limiting event 208, clock control circuit 202 is configured to generate a clock signal CLK (in block 308 in FIG. 3) at a limiting frequency FT lower than the current frequency FO of clock signal CLK. For example, the limiting frequency FT can be a programmed and / or pre-configured frequency stored in a limiting frequency memory such as memory 223, accessible by the clock control circuit 202 to set the frequency FO of the clock signal CLK. The clock control circuit 202 is configured to generate a clock signal CLK (box 310 in Figure 3) at the clock output 204 at the next intermediate frequency FO between the current frequency FO and the limiting frequency FT. This causes the frequency FO of the clock signal CLK to be ultimately set to the limiting frequency FT in multiple frequency steps to avoid drastic changes in the frequency FO that could cause di / dt events in the processor 206. In this example, the FSM circuit 234 is configured to cause the PLL circuit 232 to generate the clock signal CLK at the next intermediate frequency FO at the clock output 204. The clock control circuit 202 (more specifically, the FSM circuit 234 in this example) is configured to subsequently verify that the frequency FO of the clock signal CLK has stabilized to the next intermediate frequency FO (box 312 in Figure 3). In response to the clock signal CLK that verifies the next intermediate frequency FO, the clock control circuit 202 is configured to continue generating and verifying the clock signal CLK for the next intermediate frequency FO until the next intermediate frequency FO is or approximately the limit frequency FT (blocks 314, 310 and 312 in Figure 3).

[0034] In this example, the FSM circuit 234 can be configured to adjust power states in response to a frequency limiting event 208 to increase and decrease the frequency FO of the clock signal CLK. The FSM circuit 234 controls the PLL circuit 232 to generate the clock signal CLK at the next operating frequency. The FSM circuit 234 can be programmed so that the PLL circuit 232 generates the clock signal CLK at the next operating frequency in incremental steps after verifying the next incremental change of the frequency FO of the clock signal CLK in a closed-loop manner. The FSM circuit 234 can be configured to instruct the PLL circuit 232 to change the frequency FO of the clock signal CLK according to a proportional-integral-derivative (PID) algorithm, wherein the next incremental frequency FO of the clock signal CLK is determined using the frequency FO of the clock signal CLK, the rate of change of the frequency FO of the clock signal CLK, and / or the integral of the previous history of the frequency FO of the clock signal CLK. For example, the previously set operating frequency FO of the clock signal CLK can be stored by the FSM circuit 234 in the clock control circuit 202. Clock control circuit 202 can be configured to iteratively adjust the frequency FO of clock signal CLK until the frequency FO of clock signal CLK reaches a desired next operating frequency, which can be a limit frequency or another frequency set by power control circuit 226. In this example, clock control circuit 202 can notify power control circuit 226 when the new frequency FO of clock signal CLK stabilizes, allowing processor 206 to be clocked by the new frequency of clock signal CLK. Processor 206 can halt all operations and stall processor cores 218(1)-218(C) until clock signal CLK stabilizes at its new frequency FO.

[0035] In another exemplary configuration, to avoid the need for a stall processor 206 in response to the frequency F0 limitation of the clock signal CLK, the clock control circuit 202 may, for example, include two (2) or more PLL circuits 232. This is illustrated by the exemplary PLL circuit 400 in FIG4, which may be the PLL circuit 232 in the clock control circuit 202 of FIG2. As shown, the PLL circuit 400 includes a first PLL circuit 402 (1) and a second PLL circuit 402 (2). Each PLL circuit 402 (1), 402 (2) is configured to generate respective clock signals CLK1, CLK2 at their respective first and second frequencies in a closed-loop manner. A clock selection circuit 404 is incorporated in the PLL circuit 400 to transmit one of two (2) clock signals CLK1 and CLK2 generated by the corresponding PLL circuits 402(1) and 402(2) based on a clock selection signal 406, which in this example is provided by the FSM circuit 234 in FIG2. In this example, the clock selection circuit 404 is a multiplexer circuit. The PLL circuit 400 also includes a clock feedback selection switch 408, which controls, based on the clock selection signal 406, which controls which clock signal between the clock signals CLK1 and CLK2 on the clock output 204 is fed back to the corresponding PLL circuits 402(1) and 402(2). The FSM circuit 234 is configured to control the clock selection signal 406 to alternately select between transmitting either the first clock signal CLK1 or the second clock signal CLK2 on the clock output 204 as the clock signal CLK to the processor 206 in FIG2. FSM circuit 234 controls clock selection signal 406 based on PLL circuits 402(1) and 402(2) that generate previously stable clock signals. Clock selection signal 406 selects between a first clock signal CLK1 and a second clock signal CLK2 on clock output 204, while another PLL circuit 402(2) and 402(1) generate stable clock signals CLK2 and CLK1. In this way, processor 206 can continue to operate based on stable clock signals CLK2 and CLK1 as clock signals CLK generated by one of PLL circuits 402(1) and 402(2), while the other PLL circuit 402(2) stabilizes its clock signals CLK2 and CLK1 to a new reduced frequency, which can then be used to provide a clock for processor 206. FSM circuit 234 may continue to alternately select between the first PLL circuit 402(1) and the second PLL circuit 402(2) to generate clock signal CLK until clock signal CLK reaches the final limiting frequency FT.

[0036] As described above, the clock control circuit 202 in the processor 206 of the processor-based system 200 in FIG2 is configured to limit the frequency FO of the clock signal CLK in response to the frequency limiting event 208. A non-limiting example of a frequency limiting event that may occur in a processor-based system will now be described with respect to FIG5 to FIG7, wherein the clock control circuit may limit the frequency of the clock signal that provides the clock to the processor in response.

[0037] In this regard, Figure 5 illustrates an exemplary communication flow for a thermal frequency limiting event in a processor-based system 500; the processor-based system 500 may be the processor-based system 200 in Figure 2. An example of a thermal frequency limiting event is where the ambient temperature and the processor in the processor-based system 500 reach defined temperature limits, requiring the processor to be shut down for cooling. However, it is desirable to first reduce the operating frequency of the clock signal providing the processor to allow it to continue operating under reduced power demands before shutting it down. Common components between the processor-based system 500 in Figure 5 and the processor-based system 200 in Figure 2 are shown using common component symbols.

[0038] As shown in Figure 5, the processor-based system 500 may include one or more temperature monitoring circuits 210(1)-210(N), each temperature monitoring circuit being configured to detect the temperature in the processor-based system 500. The temperature monitoring circuits 210(1)-210(N) may be included in the processor 506 and / or disposed on the same semiconductor die and / or the same IC chip as the processor 506. More than one temperature monitoring circuit 210(1)-210(N) may be used to measure the temperature of different areas of the processor-based system 500 and / or its processor 506. If the temperature monitoring circuit 210(1)-210(N) reaches a maximum permissible temperature (which can be programmed), then, for example, such a temperature monitoring circuit 210(1)-210(N) is configured in this example to generate a thermal shutdown interrupt 502 as a frequency limiting event 208. This means that the temperature at or around the processor 506 exceeds the operating capability or specifications of the processor 506 in the absence of a fault. Therefore, it may be necessary to shut down processor 506 to allow it to cool down, and then reset processor 506 to continue operation.

[0039] At this point, the frequency limiting event 208 is transmitted to the power control circuit 226 and clock control circuit 202, which are the processor core 218. The frequency limiting event 208 is also transmitted to the thermal trip pin 504, which then communicates with the board management circuitry (BMC) 508 in the processor-based system 500 to communicate with other systems or external processor-based systems 500. In response to receiving the frequency limiting event 208 indicating thermal shutdown, the clock control circuit 202 is configured to begin limiting and incrementally or stepwise reduce the frequency FO of the clock signal CLK until the programmed or configured limiting frequency FT for the thermal shutdown event, as described above, is reached. The FSM circuit 234 in the clock control circuit 202 is configured to send a frequency limiting completion signal 510 when the limiting frequency FT is reached. Then, the error flow circuit 512 initiates a reset of the processor 506 by transmitting a reset signal 514. In one option, the error flow circuit 512 may also transmit a power-off signal 516 to the power circuit (discussed in more detail below with respect to Figure 2) to shut down and reset power generation to power the processor 506.

[0040] If the processor temperature or the temperature around the processor exceeds a desired temperature threshold, even if such a threshold is not high enough to guarantee a complete shutdown, the frequency of the clock signal providing the clock to the processor in a processor-based system is still limited. The frequency of the clock signal can be self-limited to keep the processor within the required temperature range. This allows for limiting the clock signal to reduce the processor's power requirements and consumption, thereby preventing the temperature from exceeding the temperature required for shutdown and reset.

[0041] In this regard, Figure 6 illustrates an exemplary communication flow of a self-limiting frequency limiting event 208 in a processor-based system 600, which may be the processor-based system 200 of Figure 2. An example of a self-limiting frequency limiting event is a processor-based system 600 where the ambient temperature in the processor reaches a defined temperature limit that allows the processor to still operate; however, the temperature should ideally be reduced by decreasing the operating speed, thereby reducing power requirements to allow the processor temperature to remain within the desired temperature range. Common components between the processor-based system 600 in Figure 6 and the processor-based system 200 in Figure 2 are shown using common component symbols.

[0042] As shown in Figure 6, the processor-based system 600 may include one or more temperature monitoring circuits 210(1)-210(N), each temperature monitoring circuit being configured to detect the temperature in the processor-based system 600. The temperature monitoring circuits 210(1)-210(N) may be included in the processor 606 and / or disposed on the same semiconductor die and / or the same IC wafer as the processor 606. More than one temperature monitoring circuit 210(1)-210(N) may be used to measure the temperature of different regions of the processor-based system 600 and / or its processor 606. If the temperature monitoring circuit 210(1)-210(N) exceeds a defined temperature limit (where the power demand of the processor 606 should be reduced to avoid exceeding the maximum temperature limit for shutdown, which can be programmed), then, for example, such a temperature monitoring circuit 210(1)-210(N) is configured in this example to generate a self-limiting interrupt 602 as a frequency limiting event 208. This means that the temperature at or around processor 606 exceeds the expected limit for continued operation at the current frequency FO of the clock signal CLK. Therefore, it may be necessary to limit the frequency FO of the clock signal CLK that provides the clock to processor 606 to reduce the power requirements of processor 606, thereby allowing processor 606 to cool down and continue operation.

[0043] At this point, a frequency limiting event 208 is transmitted to the power control circuitry 226 and clock control circuitry 202, which is the processor core 218. The frequency limiting event 208 is also transmitted to the thermal trip pin 604, which then communicates with the BMC 608 in the processor-based system 600 to communicate with other systems or off-board processor-based systems 600. In response to receiving the frequency limiting event 208 and transmitting it in parallel to the frequency limiting event 208 to the thermal trip pin 604 (which indicates a self-limiting frequency limiting event), the clock control circuitry 202 is configured to begin limiting and incrementally or stepwise reduce the frequency FO of the clock signal CLK until the programmed or configured limiting frequency FT for the thermal shutdown event as described above is reached. The FSM circuitry 234 in the clock control circuitry 202 is configured to send a frequency limiting completion signal 610 when the limiting frequency FT is reached. BMC 608 can obtain temperature information from temperature monitoring circuits 210(1)-210(N) to determine when the temperature is below a desired temperature threshold, thereby allowing processor 606 to continue operating normally. As discussed in the example below starting with Figure 8, power control circuit 226 can then adjust the frequency and / or operating voltage of processor-based system 600.

[0044] As a method for controlling power demand and consumption, it may also be desirable to allow external devices of the processor-based system to initiate a limitation on the frequency of the clock signal that provides the clock to the processor in the processor-based system. For example, a processor-based system may be located in a data center alongside many other processor-based systems. The data center may have a power management system designed to regulate and control power allocation to the processor-based system based on various conditions and factors.

[0045] In this regard, Figure 7 is an exemplary communication flow of an external frequency limiting event 208 in a processor-based system 700, which may be the processor-based system 200 in Figure 2. Common elements between the processor-based system 700 in Figure 7 and the processor-based system 200 in Figure 2 are shown with common component symbols.

[0046] As shown in Figure 7, the processor-based system 700 includes an external communication pin 704 configured to receive external signals from an external device. The external device may be external to the processor 706 and still part of the processor-based system 700, or external to the processor-based system 700. The external communication pin 704 may be configured to receive a frequency limiting signal 702 that can trigger a frequency limiting interrupt 708. The frequency limiting interrupt 708 may trigger an external frequency limiting event 208, which is transmitted to the power control circuit 226 and the clock control circuit 202. In response to receiving the frequency limiting event 208, the clock control circuit 202 is configured to begin limiting and incrementally or stepwise reduce the frequency FO of the clock signal CLK until the programmed or configured limiting frequency FT for the thermal shutdown event as described above is reached. The FSM circuit 234 in the clock control circuit 202 is configured to send a frequency limiting completion signal 710 when the limiting frequency FT is reached. The frequency limiting completion signal 710 is transmitted to the BMC 709 to release the processor 706 into normal operation. As discussed in the example beginning with Figure 8 below, the power control circuit 226 can then also adjust the frequency and / or operating voltage of the processor-based system 700.

[0047] Controlling the operating voltage supplied to the processor-based system 200 and its processor 206 in Figure 2 to limit their power requirements and power consumption is also important. For example, if the processor-based system 200 is deployed in a data center, managing the overall power consumption in the data center is important. However, especially in artificial intelligence (AI) applications, the operating load allocated to the processor-based system 200 can vary considerably. Furthermore, not all processor-based systems in a data center may require the same amount of power to handle a given operating load at the required operating frequency to achieve the desired performance. Some processor-based systems may be performing low-intensity operating loads that can be performed at lower operating frequencies (and therefore lower performance levels) within their power budget. Other processor-based systems may be performing operating loads that require additional power beyond their power budget to operate at higher operating frequencies and achieve the required performance. In addition, the power availability of the data center may change abruptly, such as changes in uninterruptible power supplies (UPS), which can affect the power distribution to the processor-based systems, thereby impacting the CPU performance within the processor-based systems. These issues can affect the performance of applications running on processor-based systems (such as processor-based system 200) in data centers. This can impact the user experience of such applications. Consequently, in data centers, power is becoming one of the major drivers of total cost of ownership.

[0048] Referring back to Figure 2, the processor-based system 200 includes a power circuit 246, which may be, for example, a voltage regulator circuit. The power circuit 246 may be configured as an IC chip 249 separate from the IC chip 228 containing the processor 206. The power circuit 246 is coupled to a power rail 250, which receives a power signal 252 to provide power to the processor-based system 200. The power circuit 246 is configured to set an operating voltage VOP on the power signal 252 at a power output 254 provided to the power rail 250 for operation of the processor 206. The power circuit 246 sets the operating voltage VOP of the power signal 252 based on a power budget established for the processor-based system 200. The power control circuit 226 of the processor 206 receives a power budget 255 from a PMC 242, which in this example is a separate system from the processor-based system 200. For example, the PMC242 can be used as a centralized system setup in a data center, which provides power budgets to multiple processor-based systems 200 (such as the processor-based system 200 in Figure 2) to manage the overall power consumption in the data center.

[0049] As discussed in more detail below, power control circuit 226 determines the operating voltage of processor-based system 200 based on the received power budget 255. Power control circuit 226 then transmits an operating voltage indicator 256, indicating the operating voltage level, to power circuit 246. In response, power circuit 246 provides a power signal 224, indicating the operating voltage VOP at the operating voltage level indicated by operating voltage indicator 256, to processor-based system 200 and its processor 206 for operation. Power circuit 246 may provide an operating voltage feedback indicator 258, indicating the operating voltage level of operating voltage VOP of power signal 224, back to power control circuit 226. The operating voltage level in operating voltage feedback indicator 258 can be used by power control circuit 226 to determine the power consumption of processor-based system 200. The operating voltage level in operating voltage feedback indicator 258 can also be used to confirm the new operating voltage VOP of power signal 224.

[0050] In other configurations, power control circuit 226 is also configured to determine the desired operating frequency FO of clock signal CLK based on power budget 255 received from PMC to manage the total power consumption 242 of processor-based system 200. Power control circuit 226 is configured to transmit an operating frequency indicator 239, indicating the operating frequency level, to clock control circuit 202, causing clock control circuit 202 to generate clock signal CLK at this operating frequency FO. Clock control circuit 202 may provide operating frequency feedback indicator 241 back to power control circuit 226 to confirm receipt of operating voltage indicator 256 and / or the actual operating frequency FO of clock signal CLK by power control circuit 226. For example, as discussed below, power control circuit 226 may only instruct power circuit 246 to reduce operating voltage VOP of power signal 224 after reducing the operating frequency FO of clock signal CLK when a reduction in power consumption of processor-based system 200 is required. In this way, the processor 206 will not operate at the operating frequency FO based on the clock signal CLK, which exceeds the speed capability of the logic circuitry in the processor 206 for the given operating voltage VOP of the power signal 224.

[0051] Furthermore, as another example, as described above, the power circuit 246 can provide an operating voltage feedback indicator 258 indicating the actual operating voltage VOP of the power signal 224 for feedback control purposes. The power control circuit 226 can only instruct the clock control circuit 202 to increase the operating frequency FO of the clock signal CLK after increasing the operating voltage VOP of the power signal 224 when an increase in power consumption of the processor-based system 200 is required. In this way, the processor 206 will not operate at an operating frequency FO based on the clock signal CLK, which exceeds the speed capability of the logic circuitry in the processor 206 for the given operating voltage VOP of the power signal 224.

[0052] Referring again to Figure 2, one advantage of providing the power control circuitry 226 as processor circuitry is that registers can be easily used to provide interconnection between the power control circuitry 226 and the clock control circuitry 202. For example, the processor 206 may include an operating frequency register 248, wherein an operating frequency indicator 239 can be written to by the power control circuitry 226, indicating a new operating frequency for the clock signal CLK. The clock control circuitry 202 may be configured to read the operating frequency register 248 to determine the new operating frequency of the clock signal CLK based on the operating frequency indicator 239. Similarly, the processor 206 may also include an operating frequency feedback register 250, wherein an operating frequency feedback indicator 241 can be written to by the clock control circuitry 202, indicating the actual operating frequency of the clock signal CLK. The power control circuitry 226 may read the operating frequency feedback register 250 to obtain the operating frequency feedback indicator 241.

[0053] Furthermore, processor 206 may include an operating voltage register 260, wherein an operating voltage indicator 256, indicating a new operating voltage level to be set for the operating voltage VOP of power signal 224, can be written by power control circuitry 226. Power circuitry 246 may be configured to read operating voltage register 260, and / or processor 206 may be configured to transmit the operating voltage indicator 256 from operating voltage register 260 to power circuitry 246. Similarly, processor 206 may also include an operating voltage feedback register 262, wherein an operating voltage feedback indicator 258 can be written to communicate with power control circuitry 226. Power control circuitry 226 may read operating voltage feedback indicator 258 from operating voltage feedback register 262 to obtain operating voltage feedback indicator 258, which indicates the actual operating voltage VOP of power signal 224. The operating frequency register 248, the operating frequency feedback register 250, the operating voltage register 260, and the operating voltage feedback register 262 may be memory-mapped registers to allow the power control circuit 226 to write to and read from these registers via memory read / write operations.

[0054] Note that the power control circuit 226 in the processor 206 of the processor-based system 200 in Figure 2 can also be configured to cause the power circuit 246 to adjust the power in multiple power domains. For example, the power circuit 246 can be configured to generate a power signal 224 in one voltage domain and a second power signal 224(1) at a second power output terminal 254(1) in a different voltage domain to power the processor 206. The processor 206 may have circuitry that operates in different voltage domains, which requires separate power signals 224, 224(1) for different corresponding operating voltages VOP, VOP(1). For example, in cases where the processor cores 218(1)-218(C-1) need to be placed at a lower voltage in idle or sleep mode, it may be necessary to operate the memory 223 of the processor 206 in a different voltage domain than the processor cores 218(1)-218(C-1) to save power. Compared to the minimum operating voltage required by processor cores 218(1)-218(C-1) during low-power mode, memory 223 may have the minimum operating voltage required to hold data (e.g., like static random access memory (SRAM)).

[0055] As discussed in more detail below, power control circuit 226 is aware of the total power budget of the processor-based system. This power budget may have been established for the processor-based system by, for example, another power management system in a data center. If the power consumption is below the power budget, the control processor in the processor-based system can dynamically increase the operating voltage and / or operating frequency supplied to the processor-based system. If the power consumption is above the power budget, the power control circuit can also dynamically decrease the operating frequency and / or operating voltage supplied to the processor-based system. The power consumption of the processor-based system can vary based on various factors, including the operating load and the specific application being executed. Therefore, the power control circuit can continuously monitor the power consumption of the processor system in a closed-loop manner and adjust the operating frequency and / or operating voltage supplied to the processor system to maintain its power consumption within the power budget. In this way, the processor-based system and its power control circuit can dynamically manage power consumption to achieve a desired trade-off between higher efficiency and lower power consumption within the power budget.

[0056] Figure 8 is a flowchart illustrating an exemplary process 800 in which the power control circuit 226 in the processor-based system 200 of Figure 2 monitors the power consumption of the processor-based system 200. Process 800 includes the following steps: the power control circuit 226 locally manages power consumption by dynamically adjusting the operating frequency FO and / or operating voltage VOP of the power signal 224 provided to the processor 206 within an established power budget 255. The process 800 in Figure 8 is described with reference to the processor-based system 200 in Figure 2.

[0057] At this point, referring to Figure 8, the processor-based system 200 (more specifically, the power control circuit 226 in this example) receives a power budget 255 (block 802 in Figure 8) for the power consumption of the processor-based system 200. As described above, the power budget 255 can be received from a separate system other than the processor-based system 200 (such as PMC 242 in Figure 2), and the power circuit 246 sets the operating voltage VOP of the power signal 224 based on the power budget 255 (block 804 in Figure 8). As discussed above and below, the power control circuit 226 determines the operating voltage VOP of the power signal 224 based on the power budget 255. The power control circuit 226 transmits an operating voltage indicator 256, indicating the determined operating voltage level of the operating voltage VOP, to the power circuit 246. Power circuit 246 distributes a power signal 224 at a set operating voltage VOP on power output 254 for reception by processor 206 to power processor 206, which includes processor cores 218(1)-218(C) (block 806 in FIG. 8). Clock control circuit 202 generates a clock signal CLK at operating frequency FO on clock output 204 based on power budget 255 to provide clock for processor 206 (block 808 in FIG. 8). As discussed above and below, power control circuit 226 determines the operating frequency FO of clock signal CLK based on power budget 255. Power control circuit 226 transmits an operating frequency indicator 239 indicating the determined operating frequency level of operating frequency FO to clock control circuit 202. The computing processor core 220 in processor 206 executes program code 222 at a set operating frequency FO based on a clock signal CLK, which is powered by a power signal 224 of the operating voltage VOP allocated by power circuit 246 (box 810 in Figure 8).

[0058] As described above, the power control circuit 226 is configured to determine the power consumption of the processor-based system 200 and to determine that the operating frequency FO of the clock signal CLK and / or the operating voltage VOP of the power signal 224 should be adjusted based on the power budget 255. As an example, the power control circuit 226 may determine the power consumption of the processor-based system 200 based on the operating voltage level in the operating voltage feedback indicator 258 set by the power circuit 246. For example, the power budget 255 may be updated. Furthermore, as another example, a previously determined and set operating frequency FO of the clock signal CLK and / or operating voltage VOP of the power signal 224 may cause the power consumption of the processor-based system 200 to exceed or fall below the power budget 255. Ideally, the power consumption of the processor-based system 200 is expected to be equal to or close to the power budget 255, thereby achieving a desired trade-off between the performance of the processing unit 216 and the power consumption efficiency of the processor-based system 200 according to the set power budget 255.

[0059] At this point, as shown in Figure 8, another step in process 800 is that power control circuit 226 determines the current power consumption of processor-based system 200 based on computing processor core 220 operating at the current operating frequency FO of clock signal CLK and the current operating voltage VOP of power signal 224 (box 812 in Figure 8). Power control circuit 226 determines whether the current power consumption of processor-based system 200 is greater than the power budget 255 of processor-based system 200 (box 814 in Figure 8). For example, power budget 255 may have been reduced to allow another processor-based system 200 to receive power from the same distribution network supplying power signal 252 to processor-based system 200 with increased power consumption and efficiency. In response to determining that the current power consumption is greater than power budget 255 (box 816 in Figure 8), power control circuit 226 causes clock signal CLK to be generated by clock control circuit 202 at the next operating frequency FO lower than the current operating frequency FO of clock signal CLK (box 818 in Figure 8). This is because the operating frequency FO of the clock signal CLK needs to be reduced before the operating voltage VOP of the power signal 224 is reduced, so that the processor 206 can continue to operate normally. The processor 206 requires a minimum voltage to operate with the clock signal CLK at a given operating frequency FO, so that the logic circuits in the processor 206 can operate normally. The power control circuit 226 then determines whether the current operating frequency FO of the clock signal CLK is equal to or lower than the next operating frequency FO of the clock signal CLK, to determine whether the clock signal CLK has stabilized at the new next operating frequency FO (box 820 in Figure 8). In response to determining that the current operating frequency FO of the clock signal CLK is equal to or lower than the next operating frequency FO (box 822 in Figure 8), the power control circuit 226 causes the power circuit 246 to generate a power signal 224 (box 824 in Figure 8) lower than the current operating voltage VOP of the determined next operating voltage VOP.

[0060] In this manner, when the power consumption of the processor-based system 200 needs to be reduced based on the power budget 255 and its current power consumption, the operating frequency FO of the clock signal CLK is reduced before reducing the operating voltage VOP of the power signal 224. By reducing the operating frequency FO of the clock signal CLK and the operating voltage VOP of the power signal 224, the power consumption of the processor-based system 200 is reduced. Furthermore, the processing unit 216 can continue to operate to execute program code 222 at the new operating frequency FO of the clock signal CLK and the operating voltage VOP of the power signal 224. The power control circuit 226 is configured to repeat blocks 810-824 in FIG8 continuously to continuously monitor the power consumption of the processor-based system 200, and, if necessary, adjust the operating frequency FO of the clock signal CLK and / or the operating voltage VOP of the power signal 224 based on whether the power consumption is outside the power budget 255 (i.e., above or below the power budget 255).

[0061] However, if, in block 816 of Figure 8, the power budget 255 is greater than the current power consumption of the processor-based system 200, then the power control circuit 226 is also configured to increase the power consumption of both the processor-based system 200 and the processor 206 to achieve higher performance. In this case, the power budget 255 allows for increased power consumption to achieve higher performance in the processor 206. At this point, if, in block 814 of Figure 8, the power control circuit 226 determines that the current power consumption of the processor-based system 200 is less than the power budget 255 of the processor-based system 200, the power control circuit 226 can increase the power consumption of the processor-based system 200 to achieve higher performance in the processor 206. At this point, the power control circuit 226 first causes the power circuit 246 to generate a power signal 224 that is higher than the current operating voltage VOP and represents the next determined operating voltage VOP. The power control circuit 226 sets the operating voltage VOP of the power signal 224 to the determined next operating voltage VOP. This enables processor 206 to support operation based on an increased operating frequency FO of the clock signal CLK to increase performance. Power control circuitry 226 then determines whether the current operating voltage VOP of power signal 224 is equal to or higher than the next operating voltage VOP to ensure that the operating voltage VOP of power signal 224 has stabilized at the next operating voltage VOP. Power control circuitry 226 then enables clock control circuitry 202 to generate a clock signal CLK with a next operating frequency FO higher than the current operating frequency FO of clock signal CLK. Therefore, processor 206 operates based on the new, higher operating frequency FO of clock signal CLK and the higher operating voltage VOP of power signal 224 to improve performance.

[0062] If the power control circuit 226 determines that the current power consumption of the processor-based system 200 is equal to or within the defined tolerance of the power budget 255, the power control circuit 226 may choose not to adjust the operating frequency FO of the clock signal CLK and / or the operating voltage VOP of the power signal 224. At this point, the power control circuit 226 will not cause the power circuit 246 to generate a power signal 224 with a different operating voltage. The power control circuit 226 will also not cause the clock control circuit 202 to generate the clock signal CLK at a new operating frequency.

[0063] Processor 206 may be configured to store a voltage-frequency table that holds voltage-frequency pairs usable by power control circuitry 226 to determine the next operating voltage VOP of power signal 224 and the corresponding next operating frequency FO of clock signal CLK to manage the power consumption of processor-based system 200. For example, Figure 9 shows an exemplary voltage-frequency table 900 that may be stored in memory 223 of processor 206 in Figure 2 and accessible by power control circuitry 226. Voltage-frequency table 900 contains a plurality of voltage-frequency pair entries 902(1)-902(X), each entry containing a voltage level entry 904(1)-904(X) configured to store an operating voltage level and a corresponding frequency level entry 906(1)-906(X) configured to store the corresponding operating frequency level. Voltage-frequency pair entries 902(1)-902(X) are fused together to provide complementary operating voltage and operating frequency pairs. Voltage-frequency pairs 902(1)-902(X) may be based on the performance profile of processor 206 and processor-based system 200. For example, voltage-frequency table 900 may contain eight (8) voltage-frequency pairs 902(1)-902(X). The operating voltage level and corresponding operating frequency level stored in voltage-frequency pairs 902(1)-902(X) may have been determined when designing or manufacturing processor 206 in processor-based system 200. For example, some processors 206 manufactured according to the same design may have the ability to operate at a higher operating frequency for a given operating voltage than other processors 206 based on manufacturing variations. By storing the voltage-frequency table 900 in memory 223 and configuring the power control circuit 226 to access the voltage-frequency table 900 in memory 223, this provides flexibility for updating the voltage-frequency pairs 902(1)-902(X) at manufacturing time (or even during operation) if needed.

[0064] When the power control circuit 226 in the processor-based system 200 in Figure 2 determines to set a new operating voltage VOP or a new operating frequency FO for the processor 206, the power control circuit 226 can consult the voltage-frequency table 900. If it is desired to increase the operating frequency FO of the clock signal CLK to improve performance when the power consumption of the processor-based system 200 is lower than the power budget 255, the power control circuit 226 can be configured to access the next higher voltage-frequency pair entry 902(1)-902(X) in the voltage-frequency table 900. The power control circuit 226 can then access the operating voltage level in the voltage level entry 904(1)-904(X) of the next voltage-frequency pair entry 902(1)-902(X) to obtain the corresponding operating voltage to communicate with the power circuit 246, thereby increasing the operating voltage VOP of the power signal 224. The power control circuit 226 can also access the operating frequency level in the corresponding frequency level entry 906(1)-906(X) in the next voltage-frequency pair entry 902(1)-902(X) to obtain the corresponding operating frequency to be transmitted to the clock control circuit 202 to increase the operating frequency FO of the clock signal CLK.

[0065] Similarly, if it is desired to reduce the operating frequency FO of the clock signal CLK when the power consumption of the processor-based system 200 exceeds the power budget 255, the power control circuit 226 may be configured to access the next voltage-frequency pair entry 902(1)-902(X) in the voltage-frequency table 900, which has the next lower operating voltage VOP. The power control circuit 226 may then access the operating frequency level in the frequency level entry 906(1)-906(X) in the next lower voltage-frequency pair entry 902(1)-902(X) to obtain the corresponding operating frequency to be transmitted to the clock control circuit 202 to reduce the operating frequency FO of the clock signal CLK. The power control circuit 226 can also access the operating voltage level in the corresponding voltage level entry 904(1)-904(X) in the next voltage-frequency pair entry 902(1)-902(X) to obtain the corresponding operating voltage to be transmitted to the power circuit 246 in order to reduce the operating voltage VOP of the power signal 224.

[0066] Note that the voltage-frequency table 900 can also be directly accessed and / or stored in the memory of the clock control circuit 202 for use by the FSM circuit 234 to control instructions to the PLL circuit 232 to adjust the operating frequency FO of the clock signal CLK. The FSM circuit 234 can access the voltage-frequency table 900 to determine the incremental operating frequency to instruct the PLL circuit 232 to adjust the operating frequency FO of the clock signal CLK in a stepwise manner, for example, during intermediate frequency adjustment. For example, as shown in FIG9, the voltage-frequency table 900 can also include intermediate voltage-frequency pair entries 908(1)(1)-908(1)(Y)-908(X)(1)-908(X)(Y) for each voltage-frequency pair entry 902(1)-902(X) to provide intermediate operating voltage and operating frequency pairs between voltage-frequency pair entries 908(1)(1)-908(1)(Y). For example, power circuit 246 can use intermediate operating voltage and operating frequency pairs from intermediate voltage-frequency pair entries 908(1)(1)-908(1)(Y)-908(X)(1)-908(X)(Y) to adjust the operating frequency FO of clock signal CLK and the operating voltage VOP of power signal 224 in a stepwise manner to mitigate sudden large adjustments. Before making the next adjustment, clock control circuit 202 can confirm the adjustment of each granular level of the adjusted operating frequency FO of clock signal CLK. Clock control circuit 202 can adjust the operating frequency FO of clock signal CLK in granular terms according to intermediate voltage-frequency pair entries 908(1)(1)-908(1)(Y)-908(X)(1)-908(X)(Y). The power control circuit 226 can receive an acknowledgment confirming that the next determined operating frequency FO of the clock signal CLK has been reached, based on the power budget 255, via the operating frequency feedback indicator 241 from the control clock circuit 202.

[0067] Figure 10 is a flowchart illustrating a more detailed exemplary process 1000 in which the power control circuit 226 in the processor 206 of the processor-based system 200 in Figure 2 monitors and locally manages the power consumption of the processor-based system 200. For example, as discussed below, the process 1000 in Figure 10 can be used in conjunction with the power circuit 246 and the clock control circuit 202 to change the operating frequency FO of the clock signal CLK based on the FSM circuit 234, which controls the operating power state of the PLL circuit 232 in the clock control circuit 202 in Figure 2 in a closed-loop manner.

[0068] At this point, as shown in Figure 10, PMC 242 sends a new power budget 255 as the next power budget 255 to the power control circuit 226 of processor 206 (block 1002 in Figure 10). Power control circuit 226 initializes the power state (P state) to the current power state (block 1004 in Figure 10). Power control circuit 226 sets the operating frequency fn and operating voltage Vn to the current operating frequency FO and current operating voltage VOP, respectively (block 1004 in Figure 10). The current operating frequency FO and current operating voltage VOP are predetermined and set and / or maintained by power control circuit 226 in previous iterations of process 1000 in Figure 10. Power control circuit 226 then reads the current power as the operating voltage feedback indicator 258 from the operating voltage feedback register 262 of power circuit 246 to determine the current power consumed by processor-based system 200 as the currently consumed power (curr_pwr) (block 1006 in Figure 10). Alternatively, power circuit 246 can provide the current operating voltage VOP and the current IOP consumed by power circuit 246, which in turn determines the current power consumed (curr_pwr).

[0069] Referring again to Figure 10, the power control circuit 226 next determines whether the current power consumption (curr_pwr) exceeds the next power budget 255 (box 1008 in Figure 10). If so, the power control circuit 226 initiates an operating frequency conversion to set a lower operating frequency FO of the clock signal CLK via communication, thereby providing a clock for the processor 206 at the next operating frequency FO. This communication is via the operating frequency register 248 and the operating frequency feedback register 250 to the FSM circuit 234 and PLL circuit 232 of the clock control circuit 202. The FSM circuit 234 can be configured to gradually change or modify the operating frequency FO of the clock signal CLK by verifying that each step change of the operating frequency FO of the clock signal CLK has taken effect before further changing the operating frequency FO of the clock signal CLK to achieve the final, desired operating frequency FO.

[0070] At this point, as shown in Figure 10, if the power control circuit 226 determines that the current power consumption (curr_pwr) exceeds the next power budget 255 (box 1008 in Figure 8), then the power control circuit 226 determines the next operating frequency (fn) of the clock signal CLK as a lower operating frequency FO by means of the expected change (Δf) in the operating frequency FO, in order to reduce the power consumption of the processor-based system 200 (box 1010 in Figure 10). For example, as described above, the power control circuit 226 can determine the next lower operating frequency FO from the voltage-frequency table 900 in Figure 9. The power control circuit 226 then transmits the determined next operating frequency (fn) to the FSM circuit 234 in the clock control circuit 202 in Figure 2 via the operating frequency register 248, which serves as the operating frequency indicator 239, so that the clock control circuit 202 (more specifically, the PLL circuit 232) sets the operating frequency FO of the clock signal CLK to the next operating frequency (fn) (box 1012 in Figure 10). Power control circuit 226 determines whether the operating frequency FO of clock signal CLK has been set to the next operating frequency (fn) (block 1014 in Figure 10). Once power control circuit 226 determines that the operating frequency FO of clock signal CLK has been set to the next operating frequency (fn) by clock control circuit 202 (block 1014 in Figure 10), power control circuit 226 sets the operating voltage VOP for power signal 224 to power processor-based system 200 at a lower operating voltage (Vn+1) as the new operating voltage VOP, thereby reducing the power consumption of processor-based system 200 (block 1016 in Figure 10). For example, as described above, power control circuit 226 may determine the next lower operating voltage VOP from voltage-frequency table 900 in Figure 9. The power control circuit 226 transmits the determined next operating voltage (Vn) to the power circuit 246 in Figure 2 as an operating voltage indicator 256 through the operating voltage register 260, so that the power circuit 246 sets the operating voltage VOP of the power signal 224 to the next operating voltage (Vn) (box 1018 in Figure 10).

[0071] Referring to Figure 2, in this example of processing 10000 and processor-based system 200, the FSM circuit 234 is configured to adjust its power state in response to changes in the next operating frequency (fn) set by the power control circuit 226, increasing and decreasing the operating frequency FO of the clock signal CLK. In this example, the power control circuit 226 simply instructs the clock control circuit 202 to raise or lower the operating frequency FO of the clock signal CLK. The FSM circuit 234 controls the PLL circuit 232 to generate the clock signal CLK at the next operating frequency (fn). The FSM circuit 234 can be programmed so that the PLL circuit 232 generates the clock signal CLK at the next operating frequency (fn) in an incremental step manner after verifying the next incremental change of the operating frequency FO of the clock signal CLK in a closed-loop manner. FSM circuit 234 can be configured to instruct PLL circuit 232 to change the operating frequency FO of clock signal CLK according to a PID algorithm, wherein the operating frequency FO of clock signal CLK, the rate of change of operating frequency FO of clock signal CLK, and / or the integral of the previous history of operating frequency FO of clock signal CLK are used to determine the next incremental operating frequency FO of clock signal CLK. For example, the previously set operating frequency FO of clock signal CLK can be stored in clock control circuit 202 by FSM circuit 234. Clock control circuit 202 can be configured to iteratively adjust the operating frequency FO of clock signal CLK until the operating frequency FO of clock signal CLK reaches the desired next operating frequency (fn) set by power control circuit 226. Clock control circuit 202 can pass the current operating frequency FO of clock signal CLK as the operating frequency feedback indicator 241 in the operating frequency feedback register 250 read by power control circuit 226. On a continuous basis or once the current operating frequency FO of the clock signal CLK reaches the next operating frequency (fn) set by the PLL circuit 232, the clock control circuit 202 can transmit the current operating frequency FO of the clock signal CLK as the operating frequency feedback indicator 241 in the operating frequency feedback register 250.

[0072] Referring back to Figure 10, if the power control circuit 226 determines that the currently consumed power (curr_pwr) does not exceed the next power budget 255 (box 1008 in Figure 10), it can increase the operating frequency FO of the clock signal CLK and / or the operating voltage VOP of the power signal 224 to achieve better performance by means of the processor-based system 200 and the processor 206, as previously described. At this point, the power control circuit 226 sets the next operating voltage VOP for the power signal 224 to power the processor-based system 200 at an increased operating voltage (Vn-1) as the new operating voltage VOP, thereby increasing the power consumed by the processor-based system 200 (box 1020 in Figure 10). The power control circuit 226 sets the next operating frequency FO of the clock signal CLK to an increased operating frequency FO with an increased required change (fn-1) to reduce the power consumption of the processor-based system 200 (box 1020 in Figure 10). For example, as described above, the power control circuit 226 can determine the next increasing operating voltage VOP and operating frequency FO from the voltage-frequency table 900 in FIG. 9. The power control circuit 226 transmits the determined next operating voltage (Vn) to the power circuit 246 in FIG. 2 as an operating voltage indicator 256 via the operating voltage register 260, so that the power circuit 246 sets the operating voltage VOP of the power signal 224 to the next operating voltage (Vn) (box 1022 in FIG. 10). After the power control circuit 226 confirms the operating voltage VOP of the power signal 224 through the operating voltage feedback register 262, the power control circuit 226 then transmits the determined next operating frequency (fn) as an operating frequency indicator 239 to the FSM circuit 234 in the clock control circuit 202 of FIG2 through the operating frequency register 248, so that the clock control circuit 202 (more specifically, the PLL circuit 232) sets the operating frequency FO of the clock signal CLK to the increased next operating frequency (fn) (box 1022 in FIG10).

[0073] Process 1000 then repeats in a loop, iterative manner back to box 1006 in Figure 10 to continuously and dynamically determine and adjust the operating frequency FO of the clock signal CLK and / or the operating voltage VOP of the power signal 224 to control the power consumption of the processor-based system 200 within the power budget 255.

[0074] Note that the power control circuit 226 described above in the processor 206 of the processor-based system 200 in Figure 2 can also be configured to cause the power circuit 246 to adjust the power in multiple power domains. For example, the power circuit 246 can be configured to generate a second power signal 224(1) in a voltage domain different from the power signal 224 to power the processor 206. For example, the processor 206 may have circuitry that operates at different voltages based on the domains of the power signals 224, 224(1). For example, in cases where the processor cores 218(1)-218(C-1) need to be able to operate at lower voltages in idle or sleep modes, for example, it may be necessary to operate the memory 223 of the processor 206 in a voltage domain different from that of the processor cores 218(1)-218(C-1). The memory 223 may have a minimum operating voltage (e.g., like SRAM) required to retain data, compared to the minimum operating voltage required by the processor cores 218(1)-218(C-1) during low-power modes.

[0075] Figure 11 is a block diagram of an exemplary processor-based system 1100, which includes a processor 1102 having one or more CPU cores 1104(1)-1104(P), each CPU core 1104(1)-1104(P) configured to execute computer instructions for execution. The processor-based system 1100 further includes clock control circuitry 1106, configured to locally limit (multiple) frequencies of clock signals 1108 that provide clock signals to the processor 1102 in response to a frequency limiting event, thereby limiting the operating frequency of the processor 1102 and thus limiting its power requirements. The processor-based system 1100 may include, but is not limited to, processor-based systems 200, 500, 600, and 700 as shown in Figures 2, 5, 6, and 7. The clock control circuit 1106 in the processor-based system 1100 in Figure 3 can be the clock control circuits 202, 502, 602, and 702 in Figures 2, 5, 6, and 7.

[0076] Referring to Figure 11, processor 1102 can also be configured to perform local dynamic power management based on control performance and operating power consumption. For example, one of the CPU cores 1104(P) can be a power control circuit, similar to power control circuit 226 in Figure 2, to perform local dynamic power management of the processor-based system 1100 based on control performance and operating power consumption. Power control circuit 1104(P) is configured to interconnect with voltage regulator circuit 1110, which is configured to set the voltage level for power supplied to the processor-based system 1100 for operation. Processor 1102 may include, but is not limited to, processors 206, 506, 606, and 706 in Figures 2, 5, 6, and 7, and any functions for performing the aforementioned dynamic power management.

[0077] The processor-based system 1100 may be one or more circuits included in an electronic board, such as a PCB, server, personal computer, desktop computer, laptop computer, personal digital assistant (PDA), computing board, mobile device, or any other device, and may represent, for example, a server or a user's computer. The processor 1102 represents one or more general-purpose processing circuits, such as a microprocessor and a central processing unit. The processor 1102 is configured to execute processing logic in computer instructions for performing the operations and steps discussed herein. The processor 1102 also includes an instruction cache 1112 for temporary, fast access to memory storage of instructions. Instructions fetched or prefetched from memory (such as from system memory 1114) via system bus 1116 are stored in the instruction cache 1112.

[0078] Processor 1102 and system memory 1114 are coupled to system bus 1116 and can interconnect peripheral devices included in the processor-based system 1100. Processor 1102 is known to communicate with these other devices by exchanging address, control, and data information on system bus 1116. For example, processor 1102 can transmit bus transaction requests to memory controller 1118 in system memory 1114, which is an example of a slave device. Although not shown in FIG11, multiple system buses 1116 may be provided, each with a different configuration. In this example, memory controller 1118 is configured to provide memory access requests to memory array 1120 in system memory 1114. Memory array 1120 includes an array of memory bits for storing data. System memory 1114 may be, as a non-limiting example, read-only memory (ROM), flash memory, and dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), as well as static memory (e.g., flash memory and SRAM).

[0079] Other devices may be connected to system bus 1116. As shown in Figure 11, these devices may include system memory 1114, one or more input devices 1122, one or more output devices 1124, modem 1126, and one or more display controllers 1128, as an example. The input devices 1122 may include any type of input device, including but not limited to input keys, switches, and voice processors. The output devices 1124 may include any type of output device, including but not limited to audio, video, and other visual indicators. Modem 1126 may be any device configured to allow data exchange with network 1130. Network 1130 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth™ networks, and the Internet. Modem 1126 may be configured to support any type of communication protocol required. The processor 1102 may also be configured to access (multiple) display controllers 1128 via system bus 1116 to control information sent to one or more displays 1132. The (multiple) displays 1132 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), and plasma display.

[0080] The processor-based system 1100 in Figure 11 may include a set of instructions 1134, which may include conditional control instructions that make these instructions either CI instructions or CD instructions. As an example of non-transitory computer-readable media 1136, the instructions 1134 may be stored in system memory 1114, processor 1102, and / or instruction cache 1112. The instructions 1134 may also reside wholly or at least partially in system memory 1114 and / or processor 1102 during execution. The instructions 1134 may further be sent or received on network 1130 via modem 1126, such that network 1130 includes non-transitory computer-readable media 1136.

[0081] Although the non-transitory computer-readable medium 1136 is shown as a single medium in the exemplary embodiments, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated cache and server) that store one or more sets of instructions. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processing device and causing the processing device to perform any or more of the methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0082] The embodiments disclosed herein include various steps. These steps may be formed by hardware components or embodied in machine-executable instructions that can be used to perform these steps using a general-purpose or special-purpose processor with instruction set programming. Alternatively, these steps may be performed by a combination of hardware and software.

[0083] The embodiments disclosed herein may be provided as computer program products or software, and may include machine-readable media (or computer-readable media) having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform processing according to the embodiments disclosed herein. Machine-readable media includes any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form. For example, machine-readable media includes machine-readable storage media (e.g., ROM, random access memory (RAM), magnetic disk storage media, optical storage media, and flash memory devices, etc.) and the like.

[0084] Unless otherwise expressly stated and apparent from the foregoing discussion, it should be understood that throughout this specification, the use of terms such as “processing,” “calculation,” “determination,” and “display” refers to the operation and processing of a computer system or similar electronic computing device that manipulates data and memory represented as physical (electronic) quantities in the computer system’s temporary storage and converts this data and memory into other data represented as physical quantities in computer system memory, temporary storage, or other such information storage, transmission, or display devices.

[0085] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the required method steps. The necessary structures for various such systems will be apparent from the foregoing. Furthermore, no particular programming language is referenced in describing the embodiments described herein. It should be understood that the teachings of the embodiments described herein can be implemented using a variety of programming languages.

[0086] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein can be implemented as electronic hardware and instructions stored in memory or another computer-readable medium, and executed by a processor or other processing device, or a combination of both. As an example, components of the distributed antenna system described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information as required. To clearly illustrate this interchangeability, these various illustrative components, blocks, modules, circuits, and steps have been described above generally in accordance with their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of the embodiments described herein.

[0087] Processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof can be used to implement or perform the various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein to perform the functions described herein. Furthermore, the controller can be a processor. The processor can be a microprocessor, but alternatively, the processor can be any conventional processor, controller, microcontroller, or state machine. Further, the processor can be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0088] Embodiments disclosed herein may be embodied in hardware and instructions stored in hardware and may reside in, for example, RAM, flash memory, ROM, electronic programmable ROM (EPROM), electronic erasable programmable ROM (EEPROM), registers, hard drives, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage media is coupled to a processor such that the processor can read information from and write information to the storage media. Alternatively, storage media can be integrated into the processor. The processor and storage media can reside in the ASIC. ASICs can reside in remote stations. Alternatively, the processor and storage media may reside as discrete components in a remote station, base station, or server.

[0089] It should also be noted that the operational steps described in any exemplary embodiment herein are described to provide examples and discussion. Many different orders other than the ones shown are available to perform the described operations. Furthermore, the operation described in a single operation step can actually be performed in a number of different steps. Furthermore, one or more operational steps discussed in the exemplary embodiments may be combined. What will also be understood by those with usual knowledge in the technical field to which they belong is that any of a variety of techniques and techniques can be used to represent information and signals. For example, the data, commands, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above account may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles or any combination of the above.

[0090] Unless otherwise explicitly stated, it is by no means intended to construe any of the methods articulated herein as requiring their steps to be performed in a particular order. Thus, a method claim does not actually state the order in which its steps follow, or does not otherwise specify in the scope or description of the patent application that these steps will be restricted to a particular order, it is in no way meant to infer any particular order.

[0091] What is evident to those who have the usual knowledge in the technical field to which they belong is the possibility of various modifications and variations without departing from the spirit or scope of the invention. The invention shall be construed to include everything within the scope of the attached applied patent and its equivalents as modifications, combinations, sub-combinations and variations of the disclosed embodiments that can be conceived by a person with usual knowledge in the technical domain to which combine the spirit and substance of the invention.

[0092] 100: Data Center 102: Server rack 102(1)~102(M): Server rack 104: Processor-based systems 104(1)(1)~104(M)(N): Processor-based systems 106: Chassis Equipment 108(1)~108(N): Slot 112: Backplane connector 200: Processor-based systems 202: Clock control circuit 204: Clock Output 206: Processor 208: Frequency Limiting Event 210: Temperature monitoring circuit 210(1)~210(N): Temperature monitoring circuit 212: Integrated Circuits (ICs) 214: Circuit Board 216: Processing Unit 218(1)~218(C): Processor core 222: Computer program code / Program code 222 223: Memory 224: Power signal 226: Power Control Circuit 232: Phase-Locked Loop (PLL) Circuit 234: Finite-State FSM Circuit 236: Frequency Stepping Circuit 238: Frequency limiting signal 239: Operating frequency indicator 240: Frequency limiting signal 242: Power Management Circuit (PMC) 248: Operating Frequency Register 249: IC chips 250: Power rail 252: Power signal 254: Power Output 254(1): Second power output terminal 256: Operating voltage indicator 258: Operating voltage feedback indicator 260: Operating voltage register 262: Operating voltage feedback register 302~314: Boxes 400: PLL circuit 402(1): First PLL circuit 402(2): Second PLL circuit 404: Clock Selection Circuit 406: Clock Selection Signal 408: Clock Feedback Selection Switch 500: Processor-based systems 502: Thermal shutdown interruption 504: Thermal trip pin 506: Processor 508: Board Management Circuit (BMC) 510: Frequency limiting completion signal 512: Error Flow Circuit 514: Reset signal 516: Power outage signal 600: Processor-based systems 602: Self-limiting interrupt 604: Thermal trip pin 606: Processor 608:BMC 700: Processor-based systems 702: Frequency Limiting Signal 704: External communication pin 706: Processor 708: Frequency Limiting Interruption 709:BMC 710: Frequency limiting completion signal 800: Processing 802~824: Boxes 900: Voltage-Frequency Meter 902(1)~902(X): Voltage-frequency pair entries 904(1)~904(X): Voltage level entries 906(1)~906(X): Frequency level entries 908(1)(1)~908(X)(Y): Intermediate voltage-frequency pair entries 1000: Processing 1002~1022: Boxes 1100: Processor-based system 1102: Processor 1104(1)~1104(P): CPU core 1106: Clock control circuit 1108: Clock Signal 1110: Voltage Regulator Circuit 1114: System Memory 1116: System Bus 1118: Memory Controller 1120: Memory Array 1122: Input device 1124: Output device 1126: Modem 1128: Display Controller 1130: Internet 1132: Monitor 1134: Instruction 1136: Non-transitory computer-readable media

[0093] Domestic storage information (please note in order of storage institution, date, and number) none

[0094] Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A processor-based system comprising: a clock control circuit configured to generate a clock signal at a current frequency on a clock output; a processing unit including at least one computing processor core, each computing processor core coupled to the clock output, each computing processor core configured to execute program code at a rate based on the current frequency of the clock signal as an operating frequency; a power control circuit configured to control power supplied to the processing unit; and a frequency limiting memory configured to store a frequency limiting frequency programmed to shut down the processing unit; wherein the clock control circuit is configured to: receive a frequency limiting signal indicating a thermal shutdown event, wherein a temperature at or around the processing unit exceeds the operating capability or specification of the processing unit; and respond to receiving the frequency limiting signal indicating the thermal shutdown event. The clock signal is generated at a frequency lower than the current frequency limit, and in response to reaching the frequency limit, a frequency limit completion signal is sent to the power control circuit; wherein the power control circuit is configured to: in response to receiving the frequency limit completion signal from the clock control circuit, shut down the operation of the processing unit to allow the processing unit to cool down to its operating capabilities or specifications; and reset the power generation to the processing unit so that the processing unit can continue to operate.

2. The processor-based system of claim 1, wherein the clock control circuit is configured to generate a clock signal at a limiting frequency lower than the current frequency by means of the following steps: (a) generating a clock signal at a next intermediate frequency between the current frequency and the limiting frequency on the clock output; and (b) verifying the clock signal at the next intermediate frequency; and in response to verifying the clock signal at the next intermediate frequency, repeating steps (a)-(b) once or more until the next intermediate frequency is the limiting frequency; and in response to the next intermediate frequency being the limiting frequency, generating a frequency limiting completion signal.

3. The processor-based system as claimed in claim 1, wherein the clock control circuit includes a phase-locked loop (PLL) circuit configured to generate the clock signal.

4. The processor-based system as claimed in claim 3, wherein the PLL circuit is configured to generate the clock signal based on the current frequency of the clock signal, the integral of the previous current frequency of the clock signal, and a rate of change of the current frequency of the clock signal.

5. The processor-based system of claim 2, wherein the clock control circuit comprises: a first phase-locked loop (PLL) circuit configured to generate a first clock signal at a first frequency; a second PLL circuit configured to generate a second clock signal at a second frequency; a clock selection circuit configured to receive the first clock signal and the second clock signal, and to pass one of the first clock signal and the second clock signal to the clock output based on a clock selection signal; and by means of the steps of: (c) generating the clock selection signal to select the first clock signal from the first PLL circuit to couple to the clock output; and (d) causing the second PLL circuit to generate the second clock signal at the next intermediate frequency; (e) Generate the clock selection signal to select the second clock signal from the second PLL circuit to couple to the clock output; and (f) cause the first PLL circuit to generate the first clock signal at the next intermediate frequency.

6. The processor-based system as claimed in claim 5, wherein the clock control circuit is further configured to repeat steps (c)-(f) until the next intermediate frequency is the limiting frequency.

7. The processor-based system of claim 1 further includes at least one temperature monitoring circuit, each temperature monitoring circuit being configured to: detect an ambient temperature of the at least one computing processor core; and, in response to the detected ambient temperature exceeding a defined threshold temperature, generate a frequency limiting signal indicating the thermal shutdown event.

8. The processor-based system as claimed in claim 1, wherein the clock control circuitry is configured to receive the frequency limiting signal indicating the thermal shutdown event from an external device.

9. The processor-based system of claim 1, further comprising: a power circuit configured to set an operating voltage of a power signal based on a power budget and to distribute the power signal to a power output; a power rail coupled to the power output; and the at least one computing processor core, each computing processor core coupled to the power rail; wherein: The processor-based system is further configured to: in response to a frequency limit completion signal indicating a frequency limit completion event, cause the power circuit to stop generating the power signal, thereby shutting down the operation of the processing unit.

10. The processor-based system as claimed in claim 1, wherein the processing unit is further configured to program the frequency-limited memory having the frequency limit.

11. The processor-based system of claim 9, comprising: a first integrated circuit (IC) chip including the clock control circuitry and the processing unit; and a second IC chip including the power circuitry.

12. A method for limiting an operating frequency of a processor in a processor-based system, comprising the steps of: generating a clock signal at a current frequency on a clock output; executing program code in a processing unit including at least one computing processor core receiving the clock signal at a rate based on the current frequency of the clock signal; receiving a frequency limiting signal indicating a thermal shutdown event, wherein a temperature at or around the processing unit exceeds the operating capability or specifications of the processing unit; and in response to receiving the frequency limiting signal indicating the thermal shutdown event, generating and programming the clock signal at a limiting frequency lower than the current frequency to shut down the processing unit by means of the steps of: generating the clock signal at the limiting frequency lower than the current frequency on the clock output; executing program code in the processing unit at a rate based on the limiting frequency of the clock signal; In response to the processing unit executing program code at the limited frequency, the operation of the processing unit is shut down to allow the processing unit to cool down to within the operating capabilities or specifications of the processing unit; and the power generation to the processing unit is reset so that the processing unit can continue to operate.

13. The method of claim 12, comprising the steps of: (a) generating a clock signal at a next intermediate frequency between the current frequency and the limiting frequency on the clock output; (b) verifying the clock signal at the next intermediate frequency; and repeating steps (a)-(b) once or more in response to verifying the clock signal at the next intermediate frequency until the next intermediate frequency is the limiting frequency; and generating a frequency limiting completion signal in response to the next intermediate frequency being the limiting frequency.

14. The method of claim 13, wherein the step of generating the clock signal at the next intermediate frequency on the clock output comprises the following steps: generating the clock signal at the next intermediate frequency on the clock output based on a phase-locked loop of the clock signal.

15. The method of claim 13, wherein the step of generating the clock signal at the next intermediate frequency on the clock output comprises the following steps: (c) generating a clock selection signal to select a first clock signal from a first phase-locked loop (PLL) circuit to be coupled to the clock output; (d) causing a second PLL circuit to generate a second clock signal at the next intermediate frequency; (e) generating the clock selection signal to select the second clock signal from the second PLL circuit to be coupled to the clock output; and (f) causing the first PLL circuit to generate the first clock signal at the next intermediate frequency.

16. The method of claim 15 further comprises the step of repeating steps (c)-(f) until the next intermediate frequency is the limiting frequency.

17. The method of claim 12 further comprises the steps of: detecting an ambient temperature of the at least one computing processor core; and generating a frequency limiting signal indicating the thermal shutdown event in response to the detected ambient temperature exceeding a defined threshold temperature.

18. The method of claim 12 further comprises the step of: receiving from an external device the frequency limiting signal indicating the thermal shutdown event.

19. The method of claim 12 further comprises the steps of: setting an operating voltage for a power signal based on a power budget, and distributing the power signal to a power output coupled to the at least one computing processor core; transmitting a frequency limit completion signal indicating a frequency limit completion event, the frequency limit completion event indicating the clock signal at the limit frequency; and in response to the frequency limit completion signal indicating the frequency limit completion event, causing a power circuit to stop generating the power signal to shut down the operation of the processing unit.

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