Semiconductor device

Abstract

According to one embodiment, a semiconductor memory system is provided, comprising a substrate, a plurality of components, and an interface. The substrate has a multilayer structure with wiring patterns and is generally rectangular in shape when viewed from above. The components are arranged side-by-side along the length of the substrate on the surface layer side. The interface exposes the surface of the components and fills the gaps between the components and between the components and the substrate.

Description

Technical Field

[0001] This embodiment generally relates to a semiconductor memory system. Prior Technology

[0002] Previously, semiconductor memory systems were used to mount non-volatile semiconductor memory elements such as NAND flash memory on a substrate forming a connector. Furthermore, in addition to non-volatile semiconductor memory elements, volatile semiconductor memory elements were mounted, or a controller was used to control both non-volatile and volatile semiconductor memory elements.

[0003] Such semiconductor memory systems, depending on their usage environment or specifications, may have limitations on the shape or size of the substrate. For example, some systems use substrates that appear rectangular when viewed from above. Furthermore, due to the recent demand for miniaturization of semiconductor memory systems, there is a trend towards thinner substrates. When using thin rectangular substrates, it is important to suppress substrate bending. Summary of the Invention

[0004] An embodiment of the present invention provides a semiconductor device that can suppress bending of a substrate when using a rectangular substrate viewed from above.

[0005] According to one embodiment, a semiconductor memory system comprising a substrate, non-volatile semiconductor memory elements, and an adhesive portion is provided. The substrate has a multilayer structure with wiring patterns and is generally rectangular in shape when viewed from above. The non-volatile semiconductor memory elements are arranged side-by-side along the length direction on the surface layer side of the substrate. The adhesive portion exposes the surface of the non-volatile semiconductor memory elements and fills the gaps between the non-volatile semiconductor memory elements and the gaps between the non-volatile semiconductor memory elements and the substrate.

[0006] According to an embodiment of the present invention, a semiconductor device is provided that can suppress bending of a substrate when using a substrate that is rectangular in shape when viewed from above. Simple Explanation of the Diagram

[0007] Figure 1 is a diagram showing an example of the configuration of a semiconductor memory system according to the first embodiment. Figure 2A is a top view showing the general structure of a semiconductor memory system. Figure 2B is a top view showing the schematic configuration of a semiconductor memory system as another example. Figure 3A is a side view of the semiconductor memory system shown in Figure 2A. Figure 3B is a side view of the semiconductor memory system shown in Figure 2B. Figure 4 is a diagram of the layer structure of the display substrate. Figure 5 is a diagram showing the wiring density of each layer of the display substrate. Figure 6 shows the wiring pattern formed on the back layer (8th layer) of the substrate. Figure 7 is a diagram showing the wiring density of each layer of the substrate used as a comparative example. Figure 8 is a diagram illustrating the line width and spacing of the wiring pattern formed on the back layer (8th layer) of the substrate. Figure 9 shows the bonding portion filling the gaps in NAND memory. Figure 10 shows a slit formed on the 7th layer of the substrate. Figure 11 is a diagram showing the layer structure of the substrate of the semiconductor memory system having the second embodiment. Figure 12 is a perspective view of the holding member in the handling method of the semiconductor memory system used in the third embodiment. Figure 13 is a cross-sectional view showing the retaining member shown in Figure 12 being housed in the box. Figure 14 is a front view of the retaining member in a variation of the third embodiment. Figure 15 shows the state of the movable part of the retaining member shown in Figure 14 when it is open. Figure 16 shows an example of the configuration of a SATA interface. Implementation

[0008] [Related Applications] This application enjoys the priority interest of Japanese Patent Application No. 2011-058140, filed on March 16, 2011, the entire contents of which are incorporated herein by reference.

[0009] The semiconductor memory system of the embodiments described below are explained in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0010] Figure 1 is a block diagram showing an example of the configuration of a semiconductor memory system according to the first embodiment. The semiconductor memory system 100 is connected to a host device (hereinafter referred to as host) 1, such as a personal computer or CPU core, via a memory connection interface such as a SATA interface (ATA I / F) 2, and functions as external memory for the host 1. Examples of the host 1 include the CPU of a personal computer, the CPU of a still camera, and the CPU of a video camera. Furthermore, the semiconductor memory system 100 can transmit and receive data with the error detection machine 200 via a communication interface 3 such as an RS232C interface (RS232C I / F).

[0011] The semiconductor memory system 100 includes a NAND flash memory (hereinafter referred to as NAND memory) 10 as a non-volatile semiconductor memory element, a driver control circuit 4 as a controller, a volatile semiconductor memory element 20, namely DRAM, which can perform faster memory operations than the NAND memory 10, a power supply circuit 5, an LED 6 for status display, and a temperature sensor 7 for detecting the internal temperature of the driver. The temperature sensor 7 directly or indirectly measures, for example, the temperature of the NAND memory 10. When the temperature sensor 7 measures a temperature above a certain level, the driver control circuit 4 restricts the writing of information to the NAND memory 10, thereby suppressing the temperature rise above that level.

[0012] Alternatively, multilayer NAND flash memory or ReRAM (Resistive RAM) can be used as non-volatile semiconductor memory elements. Conversely, MRAM (Magnetoresistive RAM) can be used as a volatile semiconductor memory element. MRAM may also have a magnetic blocking section to suppress magnetic intrusion. Furthermore, if the MRAM itself does not have a magnetic blocking section, a peripheral device (not shown) can be provided to cover the area around the MRAM and NAND memory 10 to suppress magnetic intrusion.

[0013] The power supply circuit 5 generates a plurality of different internal DC power supply voltages from the external DC power supply supplied by the power supply circuit on the host 1 side, and supplies these internal DC power supply voltages to various circuits within the semiconductor memory system 100. Furthermore, the power supply circuit 5 detects a rise in the external power supply, generates a power-on reset signal, and supplies it to the driver control circuit 4.

[0014] Figure 2A is a top view showing the general configuration of the semiconductor memory system 100. Figure 3A is a side view of the semiconductor memory system 100 shown in Figure 2A. The power supply circuit 5, DRAM 20, driver control circuit 4, and NAND memory 10 are mounted on a substrate 8 with wiring patterns. The substrate 8 is generally rectangular in shape when viewed from above. A connector 9 for connection to a host computer 1 is provided on the short side of one side of the generally rectangular substrate 8. The connector 9 functions as the aforementioned SATA interface 2 and communication interface 3. The connector 9 functions as a power input section that supplies power from the host computer 1 to the power supply circuit 5. The connector 9 is, for example, a LIF connector. Furthermore, a slit 9a is formed in the connector 9 at a position offset from the center along the short side of the substrate 8, to engage with a protrusion (not shown) on the host computer 1 side. This prevents the semiconductor memory system 100 from being installed upside down.

[0015] The substrate 8 is a multilayer structure formed by overlapping synthetic resins, for example, an 8-layer structure. However, the number of layers in the substrate 8 is not limited to 8. Figure 4 shows the layer structure of the substrate 8. On the substrate 8, wiring patterns of various shapes are formed on the surface or inner layers of each layer (insulating film 8a) made of synthetic resin as wiring layers 8b. The wiring patterns are formed, for example, with copper. Through the wiring patterns formed on the substrate 8, the power supply circuit 5, DRAM 20, driver control circuit 4, and NAND memory 10 mounted on the substrate 8 are electrically connected to each other. Furthermore, the surface (first layer side) and back side (eighth layer side) of the substrate are covered with solder resist 8c as protective films.

[0016] Figure 5 is a diagram showing the wiring density of each layer of substrate 8. Here, layers 1 to 4, which are formed on the surface layer side relative to the center line 30 of the layer structure of substrate 8 (also refer to Figure 4), are called upper layers, and layers 5 to 8, which are formed on the back layer side relative to the center line 30, are called lower layers.

[0017] As shown in Figure 5, the wiring layers 8b formed on each layer of the substrate 8 function as signal layers for transmitting and receiving signals, and as flat plates for grounding or power lines. Furthermore, the wiring density of the wiring patterns formed on each layer, that is, the proportion of the wiring layers relative to the surface area of ​​the substrate 8, is shown in Figure 5.

[0018] In this embodiment, the 8th layer, which functions as a ground layer, is not a flat layer but a mesh wiring layer, thereby suppressing its wiring density to 30-60%. Here, the overall wiring density of the upper layer of the substrate 8 is approximately 60%. Therefore, by forming a wiring pattern with a wiring density of approximately 30% for the 8th layer, the overall wiring density of the lower layer can be approximately 60%, thus making the overall wiring density of the upper layer approximately equal to that of the lower layer. Furthermore, by adjusting the wiring density of the 8th layer within the range of approximately 30-60%, it can be made approximately equal to the overall wiring density of the upper layer.

[0019] Figure 6 shows the wiring pattern formed on the back layer (8th layer) of substrate 8. As shown in Figure 6, the wiring pattern is formed in a mesh pattern on the back layer (8th layer) of substrate 8. In this way, by making the 8th layer of substrate 8 a mesh wiring layer, the wiring density is suppressed at a lower level compared to forming it as a flat layer.

[0020] The wiring layer formed on the back layer is also intended to function as a shielding layer to mitigate the impact of leakage from the semiconductor memory system 100 on other devices. Figure 8 illustrates the linewidth and spacing of the wiring pattern formed on the back layer (8th layer) of the substrate. As shown in Figure 8, a mesh wiring with a linewidth L of 0.3 mm and a line spacing S of 0.9 mm is formed on the 8th layer of the substrate 8. In the mesh wiring formed in this manner, the opening width W is 0.9 × √2 = 1.27 mm.

[0021] For example, the shielding effect against high-frequency noise, such as that of the 3 GHz SATA fundamental frequency, is as follows. First, the half wavelength (λ / 2) of the second higher harmonic of the SATA fundamental frequency is calculated using C = f × λ × √ε. Here, C is the speed of light, 3.0 × 10⁸ m / s. f is the frequency of the second higher harmonic, 6.0 × 10⁹ Hz. ε is the dielectric constant, 4.6.

[0022] Based on the above conditions, λ is 23.3 mm, and half the wavelength (λ / 2) is 11.7 mm. That is, half the wavelength (λ / 2) is approximately 10 times the opening width W (1.27 mm). Furthermore, since it is approximately equal to the opening width W at λ / 20 = 1.2 mm, the shielding effect is approximately -20 dB.

[0023] Figure 9 shows the bonding portion filling the gaps in the NAND memory 10. As shown in Figure 9, a bonding portion 31 made of synthetic resin material is filled in the gaps between the NAND memory 10 and the substrate 8, thereby bonding the NAND memory 10 to the substrate 8. Furthermore, a portion of the bonding portion 31 protrudes from the gap between the NAND memory 10 and the substrate 8. This protruding portion fills the gaps between the NAND memory 10s arranged side-by-side along the length of the substrate 8. Therefore, the bonding portion 31 bonds the NAND memory 10s to each other on their sides. Additionally, the bonding portion 31 protrudes to a height not exceeding that of the NAND memory 10, thereby exposing the surface of the NAND memory 10. Also, in Figure 9, although the bonding portion 31 is filled up to approximately the middle of the height of the NAND memory 10, it may be lower, allowing the bonding portion 31 to contact adjacent NAND memory 10s. Of course, the connection portion 31 can be filled between the NAND memory 10 in a manner that is higher than the height shown in Figure 9. Furthermore, the connection portion 31 is also filled between the controller 4 and the NAND memory 10, and between the controller 4 and the DRAM 20.

[0024] Figure 2B is a top view showing a schematic configuration of a semiconductor memory system 100 as another example. Figure 3B is a side view of the semiconductor memory system 100 shown in Figure 2B. Thus, a bonding portion 31 can be filled between the NAND memory 10 and the DRAM 20.

[0025] Figure 10 shows a slit formed on the 7th layer of the substrate 8. Figure 10 shows the state of the substrate 8 viewed from the back layer side, and the 8th layer is omitted. The NAND memory 10 mounted on the surface layer side is indicated by dashed lines. A flat layer is formed on the 7th layer of the substrate 8 as a wiring layer. As shown in Figure 10, on one hand, a wiring pattern is formed over almost the entire 7th layer of the substrate 8 as a flat layer, and a slit 32 (the portion where no wiring layer is formed) is provided on a portion of it. The slit 32 is provided in the wiring pattern formed over almost the entire 7th layer, facing the gap of the NAND memory 10.

[0026] Figure 7 shows the wiring density of each layer of the substrate used as a comparative example. As shown in the comparative example in Figure 7, in the previous substrate, by making the 8th layer a flat layer, the wiring density is approximately 90%. Therefore, the wiring density of the lower layer is approximately 75%, which is significantly different from the wiring density of the upper layer (approximately 60%). Due to the different wiring densities, the ratio of insulating film 8a (synthetic resin) to wiring portion (copper) in the upper layer of substrate 8 is different from the ratio of synthetic resin to copper in the lower layer of substrate 8. Consequently, the coefficients of thermal expansion are different in the upper and lower layers of substrate 8. Based on this difference in coefficients of thermal expansion, as the temperature of substrate 8 changes, bending, such as forming a convex shape (the upper convex shape in Figure 3) along the length direction of substrate 8 on the surface layer side, is likely to occur. Such temperature changes are more likely to occur during the manufacturing process of the semiconductor memory system 100. Furthermore, based on the recent demand for miniaturization of semiconductor memory systems, substrate 8 also tends to be thinner, making it easier to produce such bending.

[0027] On the other hand, in this embodiment, since the wiring density of the 8th layer is adjusted within a range of approximately 30% to 60%, the overall wiring density of the upper layer is approximately equal to that of the lower layer, and therefore the coefficients of thermal expansion are also approximately equal. Thus, bending on the substrate 8 can be suppressed. Furthermore, since the wiring density is adjusted in the 8th layer, which is furthest from the centerline 30 (see also Figure 4), the amount of moment used to suppress bending is increased.

[0028] Furthermore, since the wiring density is adjusted on the 8th layer of the substrate 8, the wiring design is easier compared to adjusting the wiring density on a layer where the wiring layout is limited, thus reducing costs.

[0029] Furthermore, since the gaps between adjacent NAND memory modules 10 are filled with bonding portions 31, the bonding force of the bonding portions 31 generates an attractive force between the NAND memory modules 10, as shown by arrow X in FIG9. Because this attractive force between the NAND memory modules 10 counteracts the force causing the substrate 8 to bend in a way that makes the first layer side convex, bending of the substrate 8 can be suppressed. If bonding portions 31 are filled, such forces are generated between the controller 4 and the NAND memory modules 10, between the controller 4 and the DRAM 20, or between the NAND memory modules 10 and the DRAM 20.

[0030] Furthermore, since the wiring pattern is disposed in the portion facing the gaps of the NAND memory 10 within the wiring pattern formed on the 7th layer of the substrate 8, the bonding force of the wiring pattern is weaker in the slit 32 portion. Therefore, the force resisting the force generated by filling the gaps between the NAND memory 10s with the bonding portion 31 (see also arrow X in Figure 9) is weaker, thereby further effectively suppressing the bending of the substrate 8.

[0031] Furthermore, in this embodiment, although the wiring layer of the 8th layer is a mesh wiring layer to adjust the overall wiring density of the lower layer of the substrate 8, it is not limited to this; for example, wiring layers can be formed on lines. Also, the wiring density of the layers other than the 8th layer in the lower layer, i.e., from the 5th layer to the 7th layer, can be adjusted to adjust the overall wiring density of the lower layer. Of course, the wiring density can be adjusted in all layers from the 5th layer to the 8th layer to adjust the overall wiring density of the lower layer.

[0032] Furthermore, the formation of slit 32 is not limited to the 7th layer. Slits can be formed in layers other than the 7th layer, namely the 5th to 6th layers and the 8th layer.

[0033] Figure 11 is a diagram showing the layer configuration of the substrate of the semiconductor memory system according to the second embodiment. In this embodiment, an outermost layer, designated as the ninth layer, is provided outside the eighth layer of the substrate 8. Furthermore, the entire outermost layer is covered with copper foil as a shielding layer. In this manner, by covering the entire outermost layer with copper foil, leakage of noise from the semiconductor memory system can be further and more reliably prevented. Alternatively, the entire area of ​​a layer further inner than the ninth layer can also be covered with copper foil as a shielding layer.

[0034] Figure 16 shows an example of the configuration of the SATA interface 2. In the semiconductor memory system illustrated in the above embodiment, there are situations where high-speed signal transmission is required. In the case of transmitting high-speed signals, in order to maintain signal quality, it is necessary to match the characteristic impedance of the transmission line, optimize the cutoff frequency of the differential mode insertion loss characteristics, and insert an appropriate current-absorbing coil into the transmission line. Figure 16 shows an example of inserting a current-absorbing coil 34 at the input and output terminals of the SATA interface 2. In addition, although the insertion position of the current-absorbing coil 34 is preferably at the input and output terminals of the SATA interface 2, it can also be near the device (driver control circuit 4, etc.).

[0035] Figure 12 is a perspective view of the holding member used in the handling method of the semiconductor memory system in the third embodiment. Figure 13 is a cross-sectional view showing the holding member shown in Figure 12 being housed in a box. In this embodiment, the semiconductor memory system 100 is handled by bundling it with the holding member 50. The holding member 50 is used to suppress bending of the substrate 8 caused by changes over time.

[0036] The retaining member 50 includes a clamping portion 51 and a connecting portion 52. Two clamping portions 51 are provided for each retaining member 50. The clamping portions 51 clamp and hold a portion along the length direction of the substrate 8. Two clamping portions 51 are provided for each retaining member 50 to hold the substrate 8 from both sides. The clamping portions 51 are formed in a U-shape cross-section, with a portion along the length direction of the substrate 8 clamped in their gaps. The clamping portions 51 resist bending forces that occur along the length direction of the substrate 8 over time, thus suppressing bending of the substrate 8. Therefore, the clamping portions 51 are formed with a strength capable of resisting forces that would bend the substrate 8.

[0037] Furthermore, to suppress bending of the substrate 8, it is preferable that the clamping portion 51 is closely attached to the substrate 8 while holding the substrate 8 in place. Alternatively, the gap formed in the clamping portion 51 may be formed to be slightly narrower than, for example, the thickness of the substrate 8, and the substrate 8 may be inserted into the clamping portion 51 while pressing open the gap. Alternatively, the gap may be formed to be approximately equal to or slightly wider than the substrate 8, and the substrate 8 may be simply inserted into the gap.

[0038] The connecting part 52 connects the two clamping parts 51. In this way, the holding member 50 can be integrated. As shown in FIG13, when multiple semiconductor memory systems 100 are stored in the box, the connecting part 52 also functions as a cushioning material to maintain the spacing between the semiconductor memory systems 100 and mitigate the impact on the semiconductor memory systems 100 during transportation.

[0039] Additionally, a spacing retaining portion 53 is formed on each of the clamping portions 51. The spacing retaining portion 53 is formed such that it extends on the side opposite to the side where the connecting portion 52 is provided, relative to the clamping portion 51. As shown in FIG13, when multiple semiconductor memory systems 100 are housed in a case, the spacing retaining portion 53 also functions as a buffer material to maintain the spacing between the semiconductor memory systems 100, thereby mitigating the impact on the semiconductor memory systems 100 during transportation.

[0040] Furthermore, although it is described in this embodiment that the substrate 8 is clamped by the clamping part 51, electronic components such as resistors or capacitors (not shown) and NAND memory 10 are mounted on the substrate 8. Therefore, when electronic components are mounted around the substrate 8, the clamping part 51 can be formed with a width that can clamp both the substrate 8 and the electronic components.

[0041] Figure 14 is a front view of the retaining member 50 in a variation of the third embodiment. In this variation, the clamping part 51 is configured with a fixed part 51a and a movable part 51b. The fixed part 51a and the movable part 51b are rotatably connected at a portion corresponding to the bottom of the gap formed in the clamping part 51, so that the movable part 51b can be opened and closed.

[0042] A closing portion 55 is formed on each of the movable portions 51b. As shown in FIG14, the closing portions 55 interlock with each other when the movable portions 51b are closed, thereby keeping the movable portions 51b in a closed state. Furthermore, by keeping the movable portions 51b in a closed state, the width of the gap formed in the clamping portion 51 is kept constant.

[0043] Figure 15 shows the state with the movable part 51b of the retaining member 50 shown in Figure 14 open. As shown in Figure 15, by opening the movable part 51b, the gap of the clamping part 51 can be widened. With the gap of the clamping part 51 widened, the semiconductor memory system 100 is placed on the fixed part 51a. If the movable part 51b is closed, compared with the case where the gap is widened and the semiconductor memory system 100 is inserted into the clamping part 51, the semiconductor memory system 100 can be held in the retaining member 50 more easily.

[0044] Further effects or variations can be readily derived by those skilled in the art. Therefore, the invention is not limited to the specific details and representative embodiments shown and described above. Thus, various modifications can be made without departing from the spirit or scope of the general concept of the invention as defined by the appended claims and their equivalents.

[0045] 1: Main unit 2:ATA I / F 3:RS232C I / F 4: Driver control circuit 5: Power supply circuit 6: LED 7: Temperature sensor 8:Substrate 8a: Insulating film 8b: Wiring layer 8c: Solder resist 9: Connector 9a: Slit 10: NAND Memory 20:DRAM 30: Center line 31: Continuing from the previous section 32: Slit 34: Anti-current coil 50: Retaining component 51: Clamping part 51a: Fixing part 51b: Movable part 52: Connecting Part 53: Interval Maintenance Section 55: Closure Section 100: Semiconductor Memory System 200: Error detection machine L: Line width S: Line spacing W: Opening width X: Arrow

Claims

1. A semiconductor device comprising: a substrate; and a plurality of semiconductor memory cells mounted on the substrate; wherein the substrate comprises: a first main surface; a second main surface facing the side opposite to the first main surface; a first wiring layer disposed on the first main surface and on which the plurality of semiconductor memory cells are mounted; and a second wiring layer disposed on the second main surface. A plurality of wiring layers are formed as inner layers; and a plurality of insulating layers are respectively disposed between the wiring layers; and the absolute value of the difference between the average value of the wiring density of the wiring layer formed on the side closer to the first main surface than the center line of the layer structure of the substrate, i.e., the first average value, and the average value of the wiring density of the wiring layer formed on the side closer to the second main surface than the center line of the layer structure of the substrate, i.e., the second average value, i.e., the second average value, is 7.5% or less; and the wiring density of at least one of the plurality of wiring layers formed as inner layers is 80% or more.

2. The semiconductor device of claim 1, wherein the wiring density of the third wiring layer, which is separated from the first wiring layer by an insulating layer, among the plurality of wiring layers formed as inner layers, is 80% or more.

3. The semiconductor device of claim 2, wherein the fourth wiring layer and the first wiring layer, which are separated by an insulating layer from the third wiring layer, are signal layers for transmitting and receiving signals.

4. The semiconductor device of claim 1, wherein the wiring density of the fifth wiring layer, which is separated from the second wiring layer by an insulating layer among the plurality of wiring layers formed as inner layers, is 80% or more.

5. The semiconductor device of claim 1, wherein at least one of the plurality of wiring layers formed as an inner layer is a signal layer for transmitting and receiving signals; and the signal layer is respectively facing the sixth wiring layer and the seventh wiring layer, which have a wiring density of 80% or more, separated by an insulating layer.

6. The semiconductor device of claim 1, wherein both the first average value and the second average value are 60% or more; the absolute value of the difference between the wiring density of the wiring layer formed as an inner layer on the side closer to the first main surface and closest to the center line of the layer structure of the substrate and the wiring density of the wiring layer formed as an inner layer on the side closer to the second main surface and closest to the center line of the layer structure of the substrate, and the second value, is greater than the first value.

7. The semiconductor device of claim 2, wherein the wiring density of the fourth wiring layer, which is separated from the third wiring layer by an insulating layer among the plurality of wiring layers formed as inner layers, is less than the first average value.

8. The semiconductor device of claim 2, wherein among the plurality of wiring layers formed as inner layers, the wiring density of the eighth wiring layer, which is separated from the fifth wiring layer by an insulating layer, is less than the second average value, and the fifth wiring layer is separated from the second wiring layer by an insulating layer.

9. The semiconductor device of claim 8, wherein the first average value and the second average value are both 60% or more; the second average value is greater than the first average value; the wiring density of the second wiring layer is less than the second average value; and the wiring density of the ninth wiring layer, which is separated from the eighth wiring layer by an insulating layer among the plurality of wiring layers formed as inner layers, is 80% or more.

10. The semiconductor device of claim 1, wherein the surface of the first wiring layer is covered with solder resist.

11. The semiconductor device of claim 1, wherein the surface of the second wiring layer is covered with solder resist.

12. The semiconductor device of claim 1, wherein the aforementioned semiconductor memory system is a NAND flash memory.

13. The semiconductor device of claim 12, wherein four NAND flash memory modules are mounted on the first wiring layer side of the substrate.

14. The semiconductor device of claim 1, wherein the substrate is generally rectangular in shape when viewed from above.

15. The semiconductor device of claim 1, wherein the first wiring layer, the second wiring layer and the plurality of wiring layers formed as inner layers comprise eight wiring layers, and four of the eight wiring layers are signal layers for transmitting and receiving signals, and the other four layers are wiring layers comprising ground or power lines.

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