Realignment method, device and system thereof

Abstract

This disclosure article discloses a realignment method for a programmable regulator voltage-controlled ring oscillator. The realignment method includes the following steps: A variable resistance of a resistor array is set based on one or more control strings. A voltage is received from a phase-locked loop circuit, which is received by an operational amplifier coupled to the resistor array. A first signal is generated by the resistor array based on a comparison of the voltages between the phase-locked loop circuit and the resistor array. The operation of the ring oscillator coupled to the resistor array is controlled based on the first signal. The realignment circuit realigns the waveform phase of the ring oscillator with the first signal.

Description

[Technical Field]

[0001] None. [Previous Technology]

[0002] Generally speaking, an integrated circuit (IC) is a circuit in which some or all of its circuit elements are inseparably connected and electrically interconnected; therefore, an IC is generally considered indivisible. ICs are typically contained within a wafer. A wafer can be a slice or disk-shaped structure formed from semiconductor material or semiconductor material deposited on a substrate. Multiple circuits or devices can be fabricated on a wafer, and when multiple devices exist on a wafer, they can then be separated into bare dies. A wafer can have logic circuits that constitute high-speed digital circuits, such as digital logic circuits used in digital phase-locked loop (PLL) circuits. A ring-type voltage-controlled oscillator (RO-VCO) is a component of a PLL circuit. RO-VCOs can be used to generate clocks in various application-specific integrated circuits (ASICs), including but not limited to applications in network controllers, input / output controllers, graphics processors, or similar circuits. [Summary of the Invention]

[0003] None.

Implementation Method

[0005] The following disclosure provides numerous different embodiments or examples to implement different features of the provided object. Specific examples of components and arrangements are described below to simplify the subject matter. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Additionally, element symbols and / or letters may be repeated in various examples. This repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatially relative terms (such as "below," "below," "lower part," "above," "upper part," and the like) may be used herein to describe the relationship between one element or feature illustrated in the figures and another element (or elements) or feature (or features). In addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations) and therefore the spatially relative descriptive terms used herein may be interpreted similarly.

[0007] This disclosure document discloses some embodiments. Additional operations may exist before, during, and / or after the stages described in these embodiments. For different embodiments, some stages described below may be replaced or eliminated. Additional features may be added to the semiconductor device. For different embodiments, some features described below may be replaced or eliminated. Although some embodiments operate in a specific order, these operations may also be performed in another logical order.

[0008] This disclosure discloses a current-mode realignment method that uses a programmable solution to facilitate adjustment of the realignment strength to control the balance of phase noise and / or adjacent cycle jitter. A phase-locked loop (PLL) is a circuit used to generate an output signal with a phase related to an input signal. PLLs have many different applications, such as radio, telecommunications, and other electronic applications that process signals containing noise. For example, PLLs can be used to generate, stabilize, demodulate, filter, or recover signals after they have passed through a noisy communication channel. A ring voltage-controlled oscillator (VCO) is a component of a PLL circuit that helps generate clocks in various specialized integrated circuits, including but not limited to network controllers, input / output controllers, graphics processors, etc. However, ring VCOs may experience degraded jitter performance due to high gain and / or phase noise. Realignment techniques, such as those described in U.S. Patent No. 10,516,385, entitled "Ring Oscillator, Controlling Circuit and Methods for Realignment," and U.S. Patent No. 10,461,723, entitled "Full Range Realignment Ring Oscillator," can suppress in-band noise in ring voltage-controlled oscillators.

[0009] Figure 1 illustrates a block diagram of a programmable regulator voltage-controlled ring oscillator 100 according to various embodiments of this disclosure. The programmable regulator voltage-controlled ring oscillator 100 includes an operational amplifier 110, two PMOS devices (e.g., PMOSREPLICA 120 and PMOSVD 130), a fourth-order ring oscillator 140, a programmable section 150, and a realignment section 160. The operational amplifier 110, PMOSREPLICA 120, and programmable section 150 constitute a regulator 170. As described in Figures 2 and 3, the intensity and / or pulse width can be adjusted by modifying the programmable section 150. The intensity of the realignment is controlled by the amount of current through the fourth-order ring oscillator 140. The regulator 170 is coupled to a programmable regulator voltage-controlled oscillator 180, which includes a PMOSVD 130 and the fourth-order ring oscillator 140. A programmable regulator voltage-controlled oscillator 180 is coupled to a realignment section 160. The realignment section 160 resets the jitter accumulated in the fourth-order ring oscillator 140 by aligning the phase of the waveform of the fourth-order ring oscillator 140 with the clock signal generated by the realignment section 160.

[0010] Figure 2 illustrates a circuit diagram of a programmable regulator voltage-controlled ring oscillator 200 according to various embodiments of this disclosure. The programmable regulator voltage-controlled ring oscillator 200 includes an operational amplifier 210, two PMOS devices (e.g., PMOSREPLICA 220 and PMOSVD 230), a fourth-order ring oscillator 240, a programmable section 250, and a realignment section 260.

[0011] In one embodiment, the programmable portion 150 is a resistor array 250. The resistor array 250 can have any number of resistors and switches. In one embodiment, the resistor array 250 has approximately 16 resistors, each coupled to a switch. In Figure 2, the control bits (e.g., the control string) are referred to as BANK[15:0], which are connected to the digital-top (not shown) of a phase-locked loop such as a hybrid phase-locked loop and / or an analog phase-locked loop. The resistance values ​​of the resistor array 250 can be represented as a function of the total unit resistance value RESUNIT and the number of controlled BANKs: (1)

[0012] The pulse input (e.g., non-inverting input) of operational amplifier 210 is coupled to a voltage-controlled oscillator (VCOIN) input voltage, which is connected to a low-pass filter (not shown) of the phase-locked loop. In some embodiments, the voltage VCOIN can vary between 0.3 volts and 0.6 volts. The inverting input of operational amplifier 210 is coupled to the drain terminal of PMOSREPLICA 220 and resistor array 250. The voltage VREPLICA can be measured at the junction of the inverting input of operational amplifier 210, the drain terminal of PMOSREPLICA 220, and the resistor array 250. The gate terminals of both PMOSREPLICA 220 and PMOSVD 230 are connected to the output of operational amplifier 210. The drain terminal of PMOSVD 230 is coupled to the power supply of a fourth-order differential ring oscillator 140 and generates a voltage VD. The realignment section 160 and the fourth-order differential ring oscillator 140 are both coupled to the PMOVD230.

[0013] The operating current of PMOSREPLICA220 is IREPLLICA. The operating current of PMOSVD230 is IVD. The device size of PMOSVD230 is approximately 4 times that of PMOSREPLICA220. Therefore, the current of operating current IVD is approximately 4 times that of operating current IREPLLICA, and its formula is as follows: (2) The equivalent resistance value of resistor array 250 can be adjusted by using parallel resistors to generate equivalent resistance RESBANK. The operating current IREPLLICA can be calculated by dividing the voltage VREPLICA by the equivalent resistance value RESARRAY of resistor array 250, and its formula is as follows: (3) Due to the nature of the electrical combination of operational amplifier 210 and PMOSREPLICA220, voltage VREPLICA will follow voltage VCOIN. Therefore, operating current IREPLLICA can also be expressed as: (4) The operating current IVD of PMOSVD230 also follows voltage VCOIN, so operating current IVD can be expressed as: (6)

[0014] When the voltage VCOIN of the voltage-controlled oscillator is a fixed voltage, the operating current IVD of the PMOSVD230 can be adjusted by different control strings. The operating current IVD of the PMOSVD230 controls the ring oscillator 140 to generate an oscillation clock with an operating frequency of FVCO. In other words, the operating frequency FVCO varies with the operating current IVD. The operating frequency FVCO of the ring oscillator varies with the control string. However, the operating frequency FVCO adjusted by the control string is discrete (i.e., discontinuous), and in some embodiments, the adjustment range of this discrete operating frequency FVCO is distributed between 4 GHz and 16 GHz. This type of control is considered discrete frequency control and can be used in hybrid phase-locked loop circuits, as described in U.S. Patent No. 10,164,649, entitled "Hybrid Phase Lock Loop," U.S. Patent No. 10,523,221, entitled "Hybrid Phase Lock Loop," and U.S. Patent No. 10,749,537, entitled "Hybrid Phase Lock Loop." The control range of this discrete operating frequency FVCO is distributed between 4 GHz and 16 GHz.

[0015] The realignment section 160 includes a realignment current cell array 261 (e.g., a PMOS device with switches), at least two transmission gates (TG) (e.g., transmission gates 262 and 263), an NMOS 264 connected to a diode, a programmed pulse generator 266, and a signal differential circuit 265. To pull the oscillator signal high at node A, the device size of the realignment current cell array 261 is approximately one-quarter the size of the PMOS VD 230. In some embodiments, the realignment current cell array 261 includes four current cells with switches. The current value of the realignment current cell array 261 can be expressed as: (7)

[0016] The NMOS 264 connected to the diode provides standby current for the realignment current cell array 261. The NMOS 264 connected to the diode ensures that the realignment signal can be quickly switched from the transmission gate 263 to the transmission gate 262. During realignment, the reference frequency FREF (e.g., a high-quality clock) induces the waveform phase of the fourth-order ring oscillator 140 to clear accumulated jitter. The programmed pulse generator 266 converts the high-quality clock into a narrow pulse clock and passes it through the signal differential circuit 265 to generate the realignment clock signal CLKRL and the clock signal CLKBRL. The pulse width is controlled to be less than half the period of the fourth-order ring oscillator 140. When realignment does not occur, the clock signals CLKRL and CLKBRL disable the transmission gate 262 and enable the transmission gate 263 to maintain the realignment signal on the NMOS 264 connected to the diode. When the rising edge of the high-quality clock reaches the programmed pulse generator 266 and the signal differential circuit 265, the clock signals CLKRL and CLKBRL will move from high to low and from low to high, respectively, opening the transmission gate 262 and closing the transmission gate 263. The realignment signal passes through the transmission gate 262 and enters the fourth-order ring oscillator 140, pulling up the oscillation waveform. The waveform phase of the fourth-order ring oscillator 140 is realigned by the high-quality clock to clear the accumulated jitter of the fourth-order ring oscillator 140 and improve in-band noise. The voltage VD of the fourth-order ring oscillator 140 can be expressed as: (5) where RESRO is the resistance value of the fourth-order ring oscillator 140.

[0017] Figure 3 illustrates the control range of a programmable regulator voltage-controlled ring oscillator according to various embodiments of this disclosure. Figure (A) illustrates the discrete frequency control range of the programmable regulator voltage-controlled ring oscillator. In one embodiment, the array block has 16 resistors, a unit resistor RESUNIT with a resistance value of approximately 1000 ohms, and 4 sets of enabled resistor groups. In this embodiment, the resistance value RESARRAY of resistor group array 250, as defined by formula (1), is approximately 250 ohms. The distribution of the discrete frequency control range in Figure (A), coupled with the voltage VD corresponding to the control string BANK[15:0] from 0 to 15, will be distributed between 4 GHz and 16 GHz. In other words, resistor group array 250 will become a voltage DAC controlling voltage VD. When resistor array 250 is fixed on a code, VREPLICA follows VCOIN and VD in a specific ratio, and increases or decreases with the ratio of IREPLICA and IVD. However, when the characters of the control string BANK[15:0] are fixed, the voltage range of VCOIN is 0.3 volts (0.3 volts to 0.6 volts), and the continuous frequency range is 3.3 GHz. This means that the gain KVCO of the voltage VCO is approximately 11 GHz / volt, as shown in Figure (B). However, the frequency range of 4 GHz to 16 GHz is controlled by a voltage VCOIN of 0.3 volts to 0.6 volts, with a gain KVCO of 40 GHz / volt. Therefore, the gain KVCO is reduced by approximately 3.6 times.

[0018] Figure 4 illustrates a timing diagram of clock jitter in an exemplary fourth-order ring oscillator according to various embodiments of this disclosure. As shown in waveform 402 in the upper half of Figure 4, the fourth-order ring oscillator 140 may experience frequency drift during operation due to inherent accumulated noise. For example, the fourth-order ring oscillator 140 may originally have a resonant frequency of 10.0 GHz and a period of 0.1 ns, but due to frequency drift, the resonant frequency may drift to 9.9 GHz, and the period to 0.101 ns. This frequency drift may be partly due to inherent device noise. However, with advancements in manufacturing processes, this inherent device noise may worsen. Noise accumulates in the fourth-order ring oscillator 140, reducing phase noise and clock jitter.

[0019] As shown in waveform 404 in the lower half of Figure 4, and as previously described in Figure 2, clock signals CLKRL and CLKBRL disable transmission gate 263 and enable transmission gate 262 to shunt the realignment signal of the array of NMOS 264 connected to the diodes to the fourth-order ring oscillator 140. The oscillation grid of the fourth-order ring oscillator 140 is pulled up, the voltage VRL increases, and the oscillation phase of the waveform of the fourth-order ring oscillator 140 is aligned by CLKRL, which comes from an external high-quality clock with low jitter and low phase noise. When the oscillation grid of the fourth-order ring oscillator 140 is aligned with the reference frequency FREF (e.g., a high-quality clock), its accumulated jitter is cleared, and its phase noise and clock jitter are also improved. Therefore, the output clock of the fourth-order ring oscillator 140 can be maintained at 10 GHz as shown in waveform 404 in the lower half of Figure 4.

[0020] Figure 5 illustrates a schematic diagram of a pulse generator 500 and a signal differential circuit 524 according to various embodiments of this disclosure. The combination of the programmable pulse generator 500 and the signal differential circuit 524 can be used, for example, as a portion of the realignment section 160 shown in Figure 2 to generate realigned clock signals CLKBRL, CLKRL. The programmable pulse generator 500 converts the high-quality clock signal into a narrow pulse clock with various pulse widths (e.g., three different pulse widths), with the maximum pulse width being less than approximately half the oscillation period. The pulse width can be determined based on the system application. The signal differential circuit 524 converts the single-ended clock signal into a differential clock signal to control the transmission gates (e.g., transmission gates 262 and 263) of the realignment section 160.

[0021] In the pulse generator 500 of Figure 5, the reference clock signal FREF is received by an inverter string 502, which is used to delay and invert the reference clock signal FREF. In some embodiments, the pulse widths of the realignment signals RLB and RL are less than half the period of the oscillator (e.g., a fourth-order ring oscillator 140). The delayed and inverted version of the reference clock signal FREF is received by a width control circuit 504, as shown in Figure 5, which includes electrically coupled inverters 506, 508, 510, 512, and 514, and inverters 516, 518, and 520. The width control circuit 504 also receives a three-bit width control signal [2:0] and uses this signal to control the pulse width generated by the pulse generator 500.

[0022] As shown in the exemplary embodiment of Figure 5, the first bit of the three-bit width control signal [2:0] is received at the inverted gate 506, the second bit of the three-bit width control signal [2:0] is received at the inverted gate 508, and the third bit of the three-bit width control signal [2:0] is received at the inverted gate 510. The table below shows an example scheme that uses the three-bit width control signal [2:0] to control the pulse width generated by the pulse generator 500: Width control signal [2:0] Pulse width 3'b001 Level 0 (Narrow) 3'b010 Level 1 (Intermediate) 3'b100 Level 2 (Width)

[0023] As shown in the table above, in this example, if the first bit (e.g., the least significant bit) is high (e.g., a high logic level or "1"), and the second and third bits are low (e.g., a low logic level or "0"), the pulse signal generated by the pulse generator 500 will have a first width (e.g., the narrowest width). Furthermore, in this example, if the third bit (e.g., the most significant bit) is high, and the first and second bits are low, the pulse signal generated by the pulse generator 500 will have a second width (e.g., the widest width). Furthermore, in this example, if the second bit is high, and the first and third bits are low, the pulse signal generated by the pulse generator 500 will have a third width (e.g., a medium width between the previously mentioned narrowest and widest widths).

[0024] The output of the width control circuit 504 is received by the inverter 522, which also receives the reference clock signal FREF. The inverter 522 processes the two inputs to generate a single-ended output signal, which is received by the signal differential circuit 524.

[0025] Figure 6 illustrates a block diagram of an exemplary system 600 using a programmable regulator voltage-controlled ring oscillator 200 according to various embodiments of this disclosure. In some embodiments, system 600 is a multiple phase-aligned ring oscillator type PLL (RO-PLL) including the programmable regulator voltage-controlled ring oscillator 200. This multiple phase-aligned ring oscillator type PLL 600 also includes an inductance-capacitance PLL (LC-PLL) and a clock tree 610. A fourth-order ring oscillator 140 can provide eight phase outputs (e.g., 14 GHz) to form a high-speed clock of 112 Gbps or 224 Gbps.

[0026] There are many advantages to using the various circuits and methods described in this disclosure. For example, the in-band noise of a ring oscillator can be improved by at least 33 dB with a 10 MHz offset. The ring voltage-controlled oscillator described in this disclosure can meet the jitter requirements of serializer / deserializer systems (e.g., data rates of 112 Gbps or higher). Because the ring voltage-controlled oscillator can directly provide a multi-phase clock output, it can also replace the combination of a conventional multi-phase filter and a proportional-integrator (PI). Using the embodiments described in this disclosure, the gain KVCO of the voltage VCO can be reduced by 70%, and the in-band noise of the voltage VCO can be improved by at least 33 dB with a 10 MHz offset.

[0027] Figure 7 illustrates an exemplary flowchart 700 of a method for realigning a programmable regulator voltage-controlled ring oscillator according to various embodiments of this disclosure. While Figure 7 is illustrated herein with reference to the previously described structure for ease of understanding, it should be understood that this method is also applicable to many other structures. In step 710, the variable resistance RESARRAY of the resistor bank array 250 is set based on one or more control strings (e.g., BANK[15:0]). In step 720, operational amplifier 210 receives a voltage VCOIN from a phase-locked loop circuit (such as the inductor-capacitor phase-locked loop 620 in Figure 6). In step 730, resistor bank array 250 generates a first signal (e.g., IREPLICA) by comparing the voltage (e.g., VCOIN) from the phase-locked loop circuit with the voltage of the resistor bank array (e.g., VREPLICA). In step 740, the operation of the ring oscillator (e.g., fourth-order ring oscillator 140) is controlled based on the first signal (e.g., IREPLICA). In step 750, the signal differential circuit 265 generates a first clock signal (e.g., CLKRL) and a second clock signal (e.g., CLKBRL). In step 760, the realignment current cell array 261 generates a realignment signal (e.g., the current through the realignment current cell array 261) based on the first clock signal (e.g., CLKRL) and the second clock signal (e.g., CLKBRL). In step 770, the waveform phase of the ring oscillator (e.g., fourth-order ring oscillator 140) is aligned with the first clock signal (e.g., CLKBRL) based on the realignment signal (e.g., the current through the realignment current cell array 261).

[0028] In one embodiment, an oscillator includes a resistor array, an operational amplifier, a first transistor, a second transistor, and a realignment circuit. The resistor array has multiple resistors used to generate a first signal. The operational amplifier is coupled to a phase-locked loop (PLL) circuit to compare the voltage of the PLL circuit with the voltage of the resistor array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is used to generate a second signal to control the frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. During the realignment state, the realignment circuit generates a realignment signal such that the ring oscillator is aligned with a first clock signal.

[0029] In another embodiment, a method for realigning a programmable regulator voltage-controlled ring oscillator includes setting the variable resistance of a resistor array using one or more control strings. An operational amplifier receives a voltage from a phase-locked loop circuit. The resistor array compares the voltage from the phase-locked loop circuit with the voltage across the resistor array to generate a first signal. Operation of the ring oscillator is controlled based on the first signal. A differential circuit generates a first clock signal and a second clock signal. A realignment current unit array generates a realignment signal based on the first clock signal and the second clock signal. The waveform phase of the ring oscillator is aligned with the first clock signal based on the realignment signal.

[0030] In yet another embodiment, a system includes a phase-locked loop (PLL) circuit, a clock tree, and a programmable voltage-controlled ring oscillator (VCO). The PLL circuit generates a first voltage. The clock tree generates a first clock signal. The VCO includes a resistor array, an operational amplifier, a first transistor, and a realignment circuit. The resistor array includes multiple resistors for generating a first signal. The operational amplifier is coupled to the PLL circuit and compares the voltage of the PLL circuit with the voltage of the resistor array. The first transistor is coupled between the operational amplifier and the ring oscillator. The first transistor generates a second signal to control the frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. During the realignment state, the realignment circuit generates a realignment signal such that the ring oscillator is aligned with a clock signal based on the first clock signal.

[0031] The foregoing has outlined the features of several embodiments to enable those skilled in the art to better understand the nature of this application. Those skilled in the art should understand that this application can be used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this application, and various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this application. [Simplified Explanation of the Diagram]

[0004] The nature of this invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation. Figure 1 illustrates a block diagram of a programmable regulator voltage-controlled ring oscillator according to various embodiments of this disclosure. Figure 2 illustrates a circuit diagram of a programmable regulator voltage-controlled ring oscillator according to various embodiments of this disclosure. Figure 3 illustrates the control range of a programmable regulator voltage-controlled ring oscillator according to various embodiments of this disclosure. Figure 4 illustrates a timing diagram of the clock jitter of an exemplary fourth-order ring oscillator according to various embodiments of this disclosure. Figure 5 illustrates a schematic diagram of a pulse generator and signal differential circuit according to various embodiments of this disclosure. Figure 6 illustrates a block diagram of an exemplary system using a programmable regulator voltage-controlled ring oscillator according to various embodiments of this disclosure. Figure 7 illustrates an exemplary flowchart of a method for a re-aligned, programmable regulator voltage-controlled ring oscillator according to various embodiments of this disclosure. Unless otherwise stated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale. [Biomaterial Storage]

[0033] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A realignment method for realigning a programmable regulator voltage-controlled ring oscillator, the realignment method comprising: setting a variable resistor of a resistor array based on one or more control strings; receiving a voltage from a phase-locked loop circuit coupled to the resistor array via an operational amplifier; generating a first signal from the resistor array based on a comparison between the voltage from the phase-locked loop circuit and a voltage of the resistor array; controlling the operation of a ring oscillator coupled to the resistor array based on the first signal; and realigning a phase of a waveform of the ring oscillator to a first clock signal of the realignment circuit by a realignment circuit, further comprising: generating the first clock signal and a second clock signal by a signal differential circuit of the realignment circuit; The realignment circuit generates a realignment signal based on the first clock signal and the second clock signal. The current unit array is coupled between the ring oscillator and an output terminal of the signal differential circuit. Based on the realignment signal, the phase of the waveform of the ring oscillator is aligned to the first clock signal.

2. The realignment method as claimed in claim 1, wherein the step of generating the first clock signal and the second clock signal comprises: a programmable pulse generator receiving a third clock signal; the programmable pulse generator generating a first realignment signal and a second realignment signal as differential signals based on the third clock signal; the signal differential circuit generating the first clock signal and the second clock signal; and operating a first transmission gate with the first clock signal and operating a second transmission gate with the second clock signal, wherein the generation of the realignment signal is based on the operation of the first transmission gate.

3. A realignment device for a programmable regulator voltage-controlled ring oscillator, the realignment device comprising: a resistor array including a plurality of resistors for generating a first signal; an operational amplifier coupled to a phase-locked loop circuit for comparing a voltage of the phase-locked loop circuit with a voltage of the resistor array; a first transistor coupled between an output of the operational amplifier and the ring oscillator, wherein the first transistor generates a second signal for controlling a frequency of the ring oscillator during a realignment state; and a realignment circuit coupled to the first transistor and the ring oscillator, wherein the realignment circuit generates a realignment signal for aligning the ring oscillator with a first clock signal during the realignment state, wherein the realignment circuit and the ring oscillator are coupled to each other through at least one direct connection.

4. A realignment system for a programmable voltage-controlled ring oscillator (VCO), the realignment system comprising: a phase-locked loop (PLL) circuit for generating a first voltage; a clock tree for generating a first clock signal; and a programmable VCO comprising: a resistor array including a plurality of resistors for generating a first signal; an operational amplifier coupled to the PLL circuit for comparing the first voltage of the PLL circuit with a voltage of the resistor array; and a realignment circuit coupled to the ring oscillator, wherein the realignment circuit generates a realignment signal for aligning the ring oscillator and the clock signal based on the first clock signal during the realignment state, wherein the realignment circuit further comprises: a realignment current cell array for generating a realignment signal based on a second signal; a first transmission gate coupled to the realignment current cell array; and a second transmission gate coupled to the realignment current cell array. A third transistor, coupled to the second transmission gate, is used to generate a standby current to switch the first transmission gate and the second transmission gate; a signal differential circuit, coupled to the first transmission gate and the second transmission gate respectively, wherein the signal differential circuit is used to generate the first clock signal and a second clock signal; and a programmable pulse generator, used to receive a third clock signal and generate a first realignment signal and a second realignment signal as differential signals based on the third clock signal.

5. A realignment method comprising: setting a variable resistor of a resistor array based on one or more control strings; receiving a voltage from a phase-locked loop circuit coupled to the resistor array via an operational amplifier; generating a first signal from the resistor array based on a comparison between the voltage from the phase-locked loop circuit and a voltage of the resistor array; controlling the operation of a ring oscillator coupled to the resistor array based on a second control signal received from a ring oscillator and the first signal; and realigning a phase of a waveform of the ring oscillator to a first clock signal of the realignment circuit via a realignment circuit based on a realignment signal received from the ring oscillator, wherein the realignment circuit and the ring oscillator are coupled to each other through at least one direct connection.

6. A realignment device comprising: a resistor array including a plurality of resistors for generating a first signal; an operational amplifier coupled to a phase-locked loop circuit for comparing a voltage of the phase-locked loop circuit with a voltage of the resistor array; a first transistor coupled between an output of the operational amplifier and a ring oscillator, wherein the first transistor generates a second signal received by the ring oscillator to control a frequency of the ring oscillator during a realignment state; and a realignment circuit coupled to the first transistor and the ring oscillator, wherein the realignment circuit generates a realignment signal received by the ring oscillator to align the ring oscillator with a first clock signal during the realignment state.

7. A realignment system comprising: a phase-locked loop circuit for generating a first voltage; a clock tree for generating a first clock signal; and a programmable regulator voltage-controlled ring oscillator, comprising: a resistor array including a plurality of resistors for generating a first signal; a ring oscillator for receiving a second signal based on the first signal; an operational amplifier coupled to the phase-locked loop circuit for comparing the first voltage of the phase-locked loop circuit with a voltage of the resistor array; and a realignment circuit coupled to the ring oscillator, wherein the realignment circuit generates a realignment signal received by the ring oscillator to align the ring oscillator and the clock signal based on the first clock signal during a realignment state, wherein the realignment circuit and the ring oscillator are coupled to each other through at least one direct connection.

8. A realignment method comprising: generating a comparison signal by the regulator based on a comparison between a voltage from a first circuit and a voltage of a programmable portion of a regulator, wherein the programmable portion includes an array of resistors; controlling the operation of a ring oscillator based on a first signal generated according to the comparison signal received by the ring oscillator; and realigning a phase of a waveform of the ring oscillator to a first clock signal based on a realignment signal received by the ring oscillator.

9. A realignment device comprising: a regulator for generating a comparison signal based on a comparison between a voltage from a first circuit and a voltage of a programmable portion of the regulator, wherein the programmable portion includes an array of resistors; a ring oscillator; and a first transistor coupled to the regulator and the ring oscillator, wherein the first transistor is configured to generate a first signal received by the ring oscillator based on the comparison signal to control a frequency of the ring oscillator, wherein the ring oscillator further receives a realignment signal to align the ring oscillator with a first clock signal.

10. A realignment system comprising: a regulator including a programmable portion for generating a first signal based on a comparison between a voltage from a first circuit and a voltage of the programmable portion, wherein the programmable portion includes an array of resistors; and a ring oscillator for receiving a second signal based on the first signal, the ring oscillator further receiving a realignment signal to align the ring oscillator and a clock signal.

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