Package comprising inter-substrate gradient interconnect structure

Abstract

An element includes a first package and a second package coupled to the first package. The first package includes a first substrate, at least one gradient interconnect structure coupled to the first substrate, and a first integrated element coupled to the first substrate. The second package includes a second substrate and a second integrated element coupled to the second substrate. The second substrate is coupled to the at least one gradient interconnect structure.

Description

Technical Field

[0001] This patent application claims priority and benefit to pending non-provisional application No. 17 / 093,954, filed on November 10, 2020, with the United States Patent and Trademark Office.

[0002] Various features relate to packaging and substrate. Prior Technology

[0003] Figure 1 illustrates a package 100 including a substrate 102, integrated components 105 and 107. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a plurality of solder interconnects 124. The plurality of solder interconnects 154 are coupled to a first surface of the substrate 102 and the integrated component 105. The plurality of solder interconnects 174 are coupled to the first surface of the substrate 102 and the integrated component 107. The package 100 is coupled to a board 106 via the plurality of solder interconnects 124. There is a continued demand for robust and reliable packages with small form factor. Summary of the Invention

[0004] Various features relate to the package and substrate, but more specifically to the package including the gradient interconnects between substrates.

[0005] One example provides a component including a first package and a second package coupled to the first package. The first package includes a first substrate, at least one gradient interconnect structure coupled to the first substrate, and a first integrated element coupled to the first substrate. The second package includes a second substrate and a second integrated element coupled to the second substrate. The second substrate is coupled to the at least one gradient interconnect structure.

[0006] Another example provides an apparatus including a first package and a second package coupled to the first package. The first package includes a first substrate, a gradient interconnect member coupled to the first substrate, and a first integrated element coupled to the first substrate. The second package includes a second substrate and a second integrated element coupled to the second substrate. The second substrate is coupled to the gradient interconnect member.

[0007] Another example provides a method for fabricating components. The method comprises the following steps: providing a first package comprising a first substrate, at least one gradient interconnect structure coupled to the first substrate, and a first integral element coupled to the first substrate. The method couples the second package to the first package. The second package includes a second substrate, wherein the second substrate is coupled to the at least one gradient interconnected structure. The second package includes a second integral element coupled to the second substrate. Brief explanation of the schema

[0008] In understanding the detailed description elaborated below in conjunction with the drawings, the various features, essences and advantages will become apparent, in the drawings, similar component symbols are always marked accordingly.

[0009] Figure 1 illustrates a cross-sectional view of the package coupled to the plate.

[0010] Figure 2 illustrates a cross-sectional view of a package including a gradient interconnection between substrates.

[0011] 3 illustrates a cross-sectional view of another package including a gradient interconnection between substrates.

[0012] 4 illustrates a cross-sectional view of another package including a gradient interconnection between substrates.

[0013] 5 illustrates a cross-sectional view of another package including a gradient interconnection between substrates.

[0014] Figures 6A–6B illustrate an exemplary process for fabricating a gradient interconnect.

[0015] 7 illustrates an exemplary flowchart of a method for fabricating a gradient interconnect.

[0016] Figures 8A–8C illustrate an exemplary process for fabricating a package including a gradient interconnect between substrates.

[0017] 9 illustrates an exemplary flowchart of a method for fabricating a package including a gradient interconnect between substrates.

[0018] Figure 10 illustrates various electronic devices that can integrate the chips, electronic circuits, integrated components, integrated passive components (IPDs), passive components, packages, and / or component packages described herein. Implementation

[0019] In the following description, specific details are provided to offer a thorough understanding of the various forms of this application. However, those skilled in the art will understand that these forms can be practiced without such specific details. For example, circuits may be illustrated using block diagrams to avoid obscuring the forms in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be illustrated in detail to avoid obscuring the forms of this application.

[0020] This application describes an element comprising a first package and a second package coupled to the first package. The first package includes a first substrate, at least one gradient interconnect structure coupled to the first substrate, and a first integrated element coupled to the first substrate. The second package includes a second substrate and a second integrated element coupled to the second substrate. The second substrate is coupled to the at least one gradient interconnect structure. The element may include a package-on-a-package (PoP). The gradient interconnect structure is located between the first and second substrates. In some implementations, the gradient interconnect structure may include an encapsulation layer and at least one continuous interconnect extending diagonally through the encapsulation layer. In some implementations, the gradient interconnect structure may include an encapsulation layer and at least one continuous interconnect extending vertically and horizontally through the encapsulation layer. The at least one continuous interconnect extending vertically and horizontally through the encapsulation layer may include a leadframe interconnect. Using a gradient interconnect structure helps reduce the spatial thickness between the first and second substrates, which in turn helps reduce the overall height of the package. Exemplary package including gradient interconnects between substrates

[0021] Figure 2 illustrates a cross-sectional view of a component 200 including a gradient interconnect structure. Component 200 includes a first package 290 and a second package 292. Component 200 may include a PoP (PoS) package. The second package 292 is coupled to the first package 290. Component 200 is coupled to a board 209 via a plurality of solder interconnects 226. Specifically, the first package 290 is coupled to the board 209 via a plurality of solder interconnects 226. The first package 290 is located between the second package 292 and the board 209. The board 209 may include a printed circuit board (PCB).

[0022] The first package 290 includes a first substrate 202, an integrated element 203, a gradient interconnect structure 206, and a plurality of solder interconnects 226. The first substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. The first substrate 202 may include an embedded trace substrate (ETS), a laminated substrate, and / or a coreless substrate. The integrated element 203 is coupled to a first surface (e.g., a bottom surface) of the first substrate 202 via a plurality of solder interconnects 234. The plurality of solder interconnects 226 are coupled to the first surface of the first substrate 202.

[0023] A gradient interconnect structure 206 is coupled to a second surface (e.g., top surface) of a first substrate 202. A plurality of solder interconnects 244 may be used to couple the gradient interconnect structure 206 to the first substrate 202. The gradient interconnect structure 206 includes an encapsulation layer 260 and at least one interconnect 262 extending through the encapsulation layer 260. The encapsulation layer 260 may be an encapsulation member. The encapsulation layer 260 may be formed using compression and transfer molding processes, sheet molding processes, or liquid molding processes. At least one interconnect 262 may extend in the encapsulation layer 260 in different directions. Each of the at least one interconnect 262 may be a continuous interconnect extending through the encapsulation layer 260. In the example of FIG. 2, at least one interconnect 262 includes at least one continuous interconnect extending diagonally in the encapsulation layer 260. The diagonal direction is relative to the facing of the encapsulation layer 260 and / or coupled to the surface of the first substrate 202. Examples of diagonal orientations include, for example, between approximately 1 degree and 89 degrees (inclusive). The at least one continuous interconnect may include leadframe interconnects. At least one interconnect 262 is coupled to the first substrate 202 via a plurality of solder interconnects 244. The gradient interconnect structure 206 may be a gradient interconnect component. As will be further described below in at least Figures 3–5, the gradient interconnect structure 206 may include interconnects with different shapes, sizes, designs, and / or orientations. A thinner first substrate 202 is provided using the gradient interconnect structure 206 (and / or any gradient interconnect structure described herein), which can be converted into a thinner PoP (PoP). The gradient interconnect structure 206 may be positioned along the periphery of the first substrate 202.

[0024] As mentioned above, the second package 292 is coupled to the first package 290. The second package 292 includes a second substrate 204, integrated element 201, integrated element 205, element 207, and encapsulation layer 208. The second substrate 204 includes at least one dielectric layer 240 and a plurality of interconnects 242. The second substrate 204 may include an embedded trace substrate (ETS), a core substrate, a laminated substrate, and / or a coreless substrate. The integrated element 201 is coupled to a first surface (e.g., the bottom surface) of the second substrate 204 via a plurality of solder interconnects 212. The plurality of solder interconnects 212 may be coupled to the plurality of interconnects 242 via a plurality of solder interconnects. The integrated element 205 is coupled to a second surface (e.g., the top surface) of the second substrate 204 via a plurality of solder interconnects 254. The element 207 is coupled to the second surface of the second substrate 204 via a plurality of solder interconnects 274. The element 207 may include a passive element (e.g., a surface mount capacitor). Encapsulation layer 208 is formed on the second surface of the second substrate 204, over the integrated element 205 and element 207. Encapsulation layer 208 can be an encapsulation component. Encapsulation layer 208 can be formed using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0025] The second substrate 204 is coupled to the gradient interconnect structure 206 via a plurality of solder interconnects 264. A plurality of interconnects 242 are coupled to at least one interconnect 262 via a plurality of solder interconnects 264. The second substrate 204 is coupled to the first substrate 202 such that the gradient interconnect structure 206 is between the first substrate 202 and the second substrate 204. The second package 292 is coupled to the first package 290 such that the integrated element 201 is located laterally to the gradient interconnect structure 206. The gradient interconnect structure 206 may be laterally positioned around (e.g., laterally surrounding) the integrated element 201.

[0026] Component 200 is coupled to plate 209 such that integrated component 203 (at least partially) is located in cavity 250 of plate 209. First substrate 202 includes a first width and / or a first length. Second substrate 204 includes a second width and / or a second length. The first width may be equal to or less than the second width. The first length may be equal to or less than the second length. However, as will be further illustrated and described below, the first width may be equal to or greater than the second width, and / or the first length may be equal to or greater than the second length.

[0027] Integrated components (e.g., 201, 203, 205) may include dies (e.g., semiconductor bare dies). Integrated components may include radio frequency (RF) components, passive components, filters, capacitors, inductors, antennas, transmitters, receivers, GaAs-based integrated components, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated components, silicon (Si)-based integrated components, silicon carbide (SiC)-based integrated components, processors, memory, and / or combinations thereof. Integrated components (e.g., 201, 203, 205) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). Passive components may include surface mount devices (SMDs). Passive components may include capacitors or resistors.

[0028] The configuration and design of component 200 provide a robust and reliable package with relatively low thickness. In addition to the low thickness of the gradient interconnect structure 206, the thickness of the first package 290 can be further reduced by using the gradient interconnect structure 206, because the first substrate 202 may require fewer metal layers.

[0029] Figure 3 illustrates a component 300 including a gradient interconnect structure. Component 300 is similar to component 200 and may therefore include components identical or similar to those in component 200. Component 300 may include a stacked package (PoP). The component includes a first package 390 and a second package 292. The second package 292 is coupled to the first package 390. The first package 390 is similar to the first package 290 and includes components and configurations similar to those in the first package 290. The first package 390 includes a first substrate 202, an integrated component 203, and a gradient interconnect structure 306. The gradient interconnect structure 306 is similar to the gradient interconnect structure 206. However, the gradient interconnect structure 306 includes interconnects with different designs and / or shapes.

[0030] A gradient interconnect structure 306 is coupled to a second surface (e.g., top surface) of a first substrate 202. A plurality of solder interconnects 244 may be used to couple the gradient interconnect structure 306 to the first substrate 202. The gradient interconnect structure 306 includes an encapsulation layer 260 and at least one interconnect 362 extending through the encapsulation layer 260. The at least one interconnect 362 may extend in different directions within the encapsulation layer 260. Each of the at least one interconnect 362 may be a continuous interconnect extending through the encapsulation layer 260. In the example of FIG3, the at least one interconnect 362 includes at least one continuous interconnect extending horizontally and vertically within the encapsulation layer 260. The at least one continuous interconnect may be an interconnect that has been bent to extend horizontally and vertically. The at least one interconnect 362 may have at least one bend 363. The bend (e.g., 363) may cause the continuous interconnect to be compressed at one corner of the bend and extended at the other corner of the bend. For example, the interior (e.g., interior corner) of the bend may be compressed, while the exterior (e.g., exterior corner) of the bend may be extended. The compression and expansion of the various portions of the bend can originate from a stamping process that produces the form and shape of the leadframe interconnect. Note that at least one continuous interconnect 362 may have more than one bend and / or may extend in different directions and / or combinations of different directions. The at least one continuous interconnect may include a leadframe interconnect. At least one interconnect 362 is coupled to the first substrate 202 via a plurality of solder interconnects 244. The gradient interconnect structure 306 may be a gradient interconnect member. The gradient interconnect structure 306 may be positioned along the periphery of the first substrate 202. The gradient interconnect structure 306 may be positioned laterally around (e.g., laterally surrounding) the integrated element 201.

[0031] Figure 4 illustrates a component 400 including a gradient interconnect structure. Component 400 is similar to component 200 and may therefore include components identical or similar to those in component 200. Component 400 may include a stacked package (PoP). The component includes a first package 490 and a second package 292. The second package 292 is coupled to the first package 490. The first package 490 is similar to the first package 290 and includes components and configurations similar to those in the first package 290. The first package 490 includes a first substrate 202, an integrated component 203, and a gradient interconnect structure 406. The gradient interconnect structure 406 is similar to the gradient interconnect structure 206. However, the gradient interconnect structure 406 includes interconnects with different designs and / or shapes.

[0032] A gradient interconnect structure 406 is coupled to a second surface (e.g., top surface) of a first substrate 202. A plurality of solder interconnects 244 may be used to couple the gradient interconnect structure 406 to the first substrate 202. The gradient interconnect structure 406 includes an encapsulation layer 260 and at least one interconnect 462 extending through the encapsulation layer 260. The at least one interconnect 462 may extend in different directions within the encapsulation layer 260. Each of the at least one interconnect 462 may be a continuous interconnect extending through the encapsulation layer 260. In the example of FIG. 4, the at least one interconnect 462 includes at least one continuous interconnect extending vertically and horizontally within the encapsulation layer 260. This at least one continuous interconnect may be an interconnect that has been bent to extend vertically and horizontally. The at least one interconnect 462 may have at least one bend 463. The bend (e.g., 463) may cause the continuous interconnect to be compressed at one corner of the bend and extended at the other corner of the bend. For example, the interior (e.g., interior corner) of the bend may be compressed, while the exterior (e.g., exterior corner) of the bend may be extended. The compression and expansion of the various portions of the bend can originate from a stamping process that produces the form and shape of the leadframe interconnect. Note that at least one continuous interconnect 362 may have more than one bend and / or may extend in different directions and / or combinations of different directions. The at least one continuous interconnect may include a leadframe interconnect. At least one interconnect 462 is coupled to the first substrate 202 via a plurality of solder interconnects 244. The gradient interconnect structure 406 may be a gradient interconnect member. The gradient interconnect structure 406 may be positioned along the periphery of the first substrate 202. The gradient interconnect structure 406 may be positioned laterally around (e.g., laterally surrounding) the integrated element 201.

[0033] The first substrate 202 includes a first width and / or a first length. The second substrate 204 includes a second width and / or a second length. The first width may be equal to or greater than the second width. The first length may be equal to or greater than the second length.

[0034] Figure 5 illustrates an element 500 including a gradient interconnect structure. Element 500 is similar to element 400 and may therefore include elements identical or similar to those in element 400. Element 500 may include a stacked package (PoP). The element includes a first package 590 and a second package 292. The second package 292 is coupled to the first package 590. The first package 590 is similar to the first package 490 and includes elements and configurations similar to those in the first package 490. The first package 590 includes a first substrate 202, an integrated element 203, a gradient interconnect structure 406, and a gradient interconnect structure 506. The gradient interconnect structure 506 is similar to the gradient interconnect structure 406. However, the gradient interconnect structure 506 includes interconnects with different designs and / or shapes. The gradient interconnect structure 506 includes an encapsulation layer 260 and at least one continuous interconnect extending vertically through the encapsulation layer 260. The gradient interconnect structure 506 may be a gradient interconnect component. The gradient interconnect structure 406 and / or the gradient interconnect structure 506 may be positioned along the periphery of the first substrate 202. The gradient interconnect structure 406 and gradient interconnect structure 506 may be positioned laterally around (e.g., laterally surrounding) the integrated element 201.

[0035] The gradient interconnect structure used in this application includes a structure comprising at least one gradient interconnect. The gradient interconnect may be located within an encapsulation layer. The gradient interconnect may include continuous interconnects extending vertically, horizontally, and / or diagonally. The at least one continuous interconnect may have homogeneous components. The at least one continuous interconnect extending through the encapsulation layer (e.g., 262, 362, 462, 562) may have the shape of a metal plate or strip (e.g., a rectangular strip, a square strip). Thus, for example, the planar profile of the continuous interconnect (e.g., 262, 362, 462, 562) within the encapsulation layer may have a rectangular shape (e.g., a square). The planar profile of the continuous interconnect may be a profile on the top and / or bottom surface of the encapsulation layer and / or along a plane parallel to the top and / or bottom surface of the encapsulation layer (e.g., a horizontal plane, an XY plane). The gradient interconnect may be formed by a lead frame (e.g., a lead frame interconnect). The gradient interconnect may include at least one bend (e.g., one or more bends) in the continuous interconnect. A bend can cause a continuous interconnect to be compressed (e.g., more densely packed) at one corner of the bend and expanded (e.g., less densely packed) at the other corner. For example, the interior (e.g., inner corner) of the bend can be compressed, while the exterior (e.g., outer corner) can be expanded. The interior of the bend can be compressed more (e.g., more densely packed) relative to the unbent portion of the continuous interconnect. The exterior of the bend can be compressed less (e.g., less densely packed) relative to the unbent portion of the continuous interconnect. The compression and expansion of the various portions of the bend can originate from a stamping process that produces the form and shape of the lead frame interconnect. Note that the at least one continuous interconnect of a gradient interconnect (e.g., 262, 362, 462, 562) can have more than one bend and / or can extend in different directions and / or combinations of different directions. For example, at least one continuous interconnect can extend in a combination of vertical, horizontal, and / or diagonal directions. In some implementations, at least one continuous interconnect can extend in different diagonal directions. For example, a first continuous interconnect can extend in a first diagonal direction, while a second continuous interconnect can extend in a second diagonal direction. Continuous interconnects can extend in multiple different diagonal directions.

[0036] Various packages and gradient interconnect structures with improved configurations have been described, and the process for manufacturing gradient interconnect structures will now be described below. Exemplary process for manufacturing gradient interconnect structures

[0037] Figures 6A–6B illustrate exemplary steps for providing or manufacturing a gradient interconnect structure. In some implementations, the steps of Figures 6A–6B may be used to provide or manufacture gradient interconnect structure 206, or any gradient interconnect structure described herein.

[0038] It should be noted that the processes in Figures 6A–6B can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the gradient interconnect structure. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of these processes can be substituted or replaced without departing from the spirit of this invention. Different implementations can manufacture gradient interconnect structures differently.

[0039] As shown in Figure 6A, stage 1 illustrates the state after the conductive material 600 has been provided. The conductive material 600 includes electrically conductive materials (e.g., metals, copper). The conductive material 600 may include conductive material sheets (e.g., metal sheets).

[0040] Phase 2 illustrates the state after the conductive material 600 has been etched and / or stamped to form the leadframe interconnect 262. The leadframe interconnect 262 may have different shapes, angles, and / or dimensions. The leadframe interconnect 262 may include various continuous interconnects. Various continuous interconnects may have different shapes, angles, and / or dimensions.

[0041] Phase 3 illustrates the state after the lead frame interconnect 262 is coupled to the tape 602 (e.g., adhesive tape).

[0042] As shown in Figure 6B, stage 4 illustrates the state after the encapsulation layer 260 is formed over the tape 602 and the lead frame interconnect 262. The encapsulation layer 260 encapsulates the lead frame interconnect 262. The encapsulation layer 260 can be formed using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0043] Phase 5 illustrates the state after the tape 602 is decoupled from the lead frame interconnect 262 and the encapsulation layer 260.

[0044] Stage 6 illustrates the state after at least one cavity 610 has been formed in the encapsulation layer 260. The cavity 610 can be formed using laser processing and / or etching processes. The cavity 610 may expose portions of the leadframe interconnects 262. When the gradient interconnect structure is coupled to the substrate, the cavity 610 may include solder interconnects. In some implementations, stage 6 may illustrate a gradient interconnect structure 206. Note that the structure of stage 6 may be cut into smaller individual gradient interconnect structures. Exemplary flowchart of a method for fabricating gradient interconnect structures

[0045] In some implementations, fabricating a package with a gradient interconnect structure includes several processes. Figure 7 illustrates an exemplary flowchart of a method 700 for providing or fabricating a gradient interconnect structure. In some implementations, the method 700 of Figure 7 can be used to provide or fabricate the gradient interconnect structure of Figure 2. However, the method of Figure 7 can be used to fabricate any gradient interconnect structure in this case.

[0046] It should be noted that the method in Figure 7 can combine one or more procedures to simplify and / or clarify the method used to provide or manufacture the package. In some implementations, the order of the procedures can be changed or modified.

[0047] This method (at 705) provides leadframe interconnects (e.g., 262). Providing leadframe interconnects may include providing a conductive material 600. The conductive material 600 includes electrically conductive materials (e.g., metals, copper). Stage 1 of Figure 6A illustrates and describes an example of providing an electrically conductive material. Providing leadframe interconnects may include using stamping and / or etching processes to form various interconnects (e.g., continuous interconnects). Leadframe interconnects 262 may have different shapes, sizes, and / or configurations. Stage 2 of Figure 6A illustrates and describes an example of the state after the conductive material 600 has been etched and / or stamped to form the leadframe interconnects.

[0048] This method (at 710) couples the leadframe interconnect to the adhesive tape (e.g., 602). Phase 3 of Figure 6A illustrates and describes an example of the leadframe interconnect coupled to the tape (e.g., adhesive tape).

[0049] This method (at 715) forms an encapsulation layer (e.g., 260) over tape 602 and leadframe interconnect 262. Encapsulation layer 260 encapsulates leadframe interconnect 262. Encapsulation layer 260 can be formed using compression and transfer molding processes, sheet molding processes, or liquid molding processes. Stage 4 of Figure 6B illustrates and describes an example of forming an encapsulation layer.

[0050] This method (at 720) decouples the tape (e.g., 602) from the lead frame interconnect 262 and the encapsulation layer 260. Phase 5 of Figure 6B illustrates and describes an example of the tape that has been decoupled from the lead frame interconnect and the encapsulation layer.

[0051] The method (at 725) forms at least one cavity (e.g., 610) in the encapsulation layer 260. A laser process and / or an etching process can be used to form the cavity. The cavity in the encapsulation layer exposes portions of the leadframe interconnect 262. Stage 6 of Figure 6B illustrates and describes an example of at least one cavity formed in the encapsulation layer.

[0052] This method can (at 730) cut the encapsulation layer (e.g., 260) and the leadframe interconnect (e.g., 262) to form several gradient interconnect structures. A mechanical process (e.g., a sawing process) can be used to cut the encapsulation layer and the leadframe interconnect. Exemplary process for manufacturing a package including a gradient interconnect structure

[0053] Figures 8A–8C illustrate exemplary steps for providing or manufacturing a package including a gradient interconnect structure. In some implementations, the steps of Figures 8A–8C may be used to provide or manufacture a substrate, which may then be implemented in the components and packages of Figure 5 or any components and packages described herein.

[0054] It should be noted that the processes in Figures 8A–8C can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the components. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of these processes can be substituted or replaced without departing from the spirit of this invention. Different implementations may manufacture the components differently.

[0055] As shown in Figure 8A, stage 1 illustrates the state after the first substrate 202 has been provided. The first substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. The first substrate 202 may include different numbers of metal layers. The first substrate 202 may include a laminated substrate and / or a coreless substrate (e.g., ETS).

[0056] Phase 2 illustrates the state after the integrated component 203 has been coupled to a first surface (e.g., the bottom surface) of the first substrate 202. The integrated component 203 may be coupled to the first substrate 202 via a plurality of solder interconnects 234. Phase 2 also illustrates a plurality of solder interconnects 226 coupled to the first surface of the first substrate 202. One or more solder reflow processes may be used to couple the plurality of solder interconnects 226 and the integrated component 203 to the first substrate 202.

[0057] Phase 3 illustrates the state after the gradient interconnect structure 406 is coupled to the second surface (e.g., the top surface) of the first substrate 202. Phase 3 also illustrates the state after the gradient interconnect structure 506 is coupled to the second surface of the first substrate 202. Phase 3 may illustrate a first package 590 including the first substrate 202, integrated element 203, gradient interconnect structure 406, and gradient interconnect structure 506. The gradient interconnect structure 406 is coupled to the first substrate 202 via a plurality of solder interconnects 244. The gradient interconnect structure 406 includes an encapsulation layer 260 and a plurality of interconnects 462. The plurality of interconnects 462 may include lead frame interconnects. The plurality of interconnects 462 may include continuous interconnects extending in different directions (e.g., vertical, horizontal, diagonal) and / or in different combinations of directions (e.g., vertical, horizontal, diagonal). The plurality of solder interconnects 264 may be coupled to the gradient interconnect structure 406. The gradient interconnect structure 506 includes an encapsulation layer (e.g., 260) and a plurality of interconnects 562. The gradient interconnect structures 406 and 506 can be manufactured using the same (or similar) process as described for the gradient interconnect structure 206 in Figures 6A–6B.

[0058] As shown in Figure 8B, stage 4 illustrates the state after the second substrate 204 has been provided. The second substrate 204 includes at least one dielectric layer 240 and a plurality of interconnects 242. The second substrate 204 may include different numbers of metal layers. The second substrate 204 may include a laminated substrate, a core substrate, and / or a coreless substrate (e.g., ETS).

[0059] Phase 5 illustrates the state after the integrated component 201 is coupled to a first surface (e.g., the bottom surface) of the second substrate 204. The integrated component 201 may be coupled to the second substrate 204 via a plurality of solder interconnects 212 and / or solder interconnects. Phase 5 also illustrates the state after the integrated component 205 is coupled to a second surface (e.g., the top surface) of the second substrate 204 and component 207 is coupled to the second surface of the second substrate 204. The integrated component 205 may be coupled to the second substrate 204 via a plurality of solder interconnects 254. Component 207 (e.g., a passive component) may be coupled to the second substrate 204 via a plurality of solder interconnects 274. One or more solder reflow processes may be used to couple the integrated component 205 and component 207 to the second substrate 204.

[0060] Stage 6 illustrates the state after an encapsulation layer 208 is formed on the second substrate 204, integrated component 205, and component 207. The encapsulation layer 208 encapsulates integrated component 205 and component 207. The encapsulation layer 208 can be formed using compression and transfer molding processes, sheet molding processes, or liquid molding processes. Stage 6 may also illustrate a second package 292.

[0061] As shown in Figure 8C, Stage 7 illustrates the state after the second package 292 is coupled to the first package 590. One or more solder reflow processes can be used to couple the second package 292 to the first package 590. The second package 292 may be located on top of the first package 590. The second substrate 204 may be coupled to the first substrate 202 via gradient interconnect structures 406 and 506. The integrated component 201 may be laterally surrounded by the gradient interconnect structures 406 and 506. The gradient interconnect structures 406 and 506 may be located between the first substrate 202 and the second substrate 204. The gradient interconnect structure 406 may be coupled to the second substrate 204 via a plurality of solder interconnects 264. Stage 7 may illustrate a component 500 including the first package 590 and the second package 292. Component 500 may include a PoP (PoP) package.

[0062] Phase 8 illustrates the state after component 500 is coupled to board 209 via a plurality of solder interconnects 226. Component 500 is coupled to board 209 such that integrated component 203 is at least partially located in cavity 250 of board 209. Solder reflow process can be used to couple component 500 to board 209. Exemplary flowchart of a method for manufacturing a package including a gradient interconnect structure

[0063] In some implementations, manufacturing a package with a gradient interconnect structure includes several processes. Figure 9 illustrates an exemplary flowchart of a method 900 for providing or manufacturing a package including a gradient interconnect structure. In some implementations, the method 900 of Figure 9 can be used to provide or manufacture an element having the gradient interconnect structure of Figure 5. For example, the method of Figure 9 can be used to manufacture element 500. However, the method of Figure 9 can be used to manufacture any element and / or package in this case.

[0064] It should be noted that the method in Figure 9 can combine one or more procedures to simplify and / or clarify the methods used to provide or manufacture components and / or packages. In some implementations, the order of the procedures can be changed or modified.

[0065] The method (at 905) provides a first substrate (e.g., 202). The first substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. The first substrate 202 may include different numbers of metal layers. The first substrate 202 may include a laminated substrate and / or a coreless substrate (e.g., ETS). Phase 1 of FIG8A illustrates and describes an example of providing a first substrate.

[0066] This method (at 910) couples an integrated component (e.g., 203) and solder interconnects to a first substrate 202. The integrated component 203 may be coupled to the first substrate 202 via a plurality of solder interconnects 234. A plurality of solder interconnects 226 may be coupled to a first surface of the first substrate 202. One or more solder reflow processes may be used to couple the plurality of solder interconnects 226 and the integrated component 203 to the first substrate 202. Stage 2 of Figure 8A illustrates and describes an example of coupling an integrated component to the first substrate.

[0067] The method (at 915) couples at least one gradient interconnect structure (e.g., 406, 506) to a first substrate (e.g., 202). The gradient interconnect structure (e.g., 406, 506) may be coupled to the first substrate 202 via a plurality of solder interconnects (e.g., 244). The gradient interconnect structure 406 includes an encapsulation layer 260 and a plurality of interconnects 462. The plurality of interconnects 462 may include leadframe interconnects. The plurality of interconnects 462 may include continuous interconnects extending in different directions (e.g., vertical, horizontal, diagonal) and / or in combinations of different directions (e.g., vertical, horizontal, diagonal). A plurality of solder interconnects 264 may be coupled to the gradient interconnect structure 406. The gradient interconnect structure 506 includes an encapsulation layer (e.g., 260) and a plurality of interconnects 562. The gradient interconnect structures 406 and 506 may be manufactured using the same (or similar) process as described for the gradient interconnect structure 206 in Figures 6A–6B. Figure 8A illustrates and describes an example of a gradient interconnect structure 406 coupled to a first substrate in stage 3.

[0068] The method (at 920) provides a second substrate (e.g., 204). The second substrate 204 includes at least one dielectric layer 240 and a plurality of interconnects 242. The second substrate 204 may include different numbers of metal layers. The second substrate 204 may include a laminated substrate, a core substrate, and / or a coreless substrate (e.g., ETS). Stage 4 of Figure 8B illustrates and describes the state after the second substrate 204 has been provided.

[0069] This method (at 925) couples at least one component (e.g., 201, 205, 207) to a second substrate (e.g., 204). For example, integrated component 201 may be coupled to the second substrate 204 via a plurality of solder interconnects 212 and / or solder interconnects. One or more solder reflow processes may be used to couple the components to the second substrate 204. Stage 5 of Figure 8C illustrates and describes an example of a component coupled to the second substrate.

[0070] The method (at 930) forms an encapsulation layer (e.g., 208) on a second substrate (e.g., 204). The encapsulation layer 208 may be formed on one or more components (e.g., 205, 207). The encapsulation layer 208 may be formed using compression and transfer molding processes, sheet molding processes, or liquid molding processes. Stage 6 of FIG8B illustrates and describes an example of forming an encapsulation layer on the second substrate and(s) of the components.

[0071] This method (at 935) couples a second package (e.g., 292) to a first package (e.g., 290, 390, 490, 590). One or more solder reflow processes can be used to couple the second package (e.g., 292) to the first package (e.g., 590). The second package 292 may be located on top of the first package 590. A second substrate 204 may be coupled to the first substrate 202 via gradient interconnect structures 406 and 506. An integrated element 201 may be laterally surrounded by gradient interconnect structures 406 and 506. Gradient interconnect structures 406 and 506 may be located between the first substrate 202 and the second substrate 204. Gradient interconnect structure 406 may be coupled to the second substrate 204 via a plurality of solder interconnects 264. Phase 7 of Figure 8C illustrates and describes an example of a second package coupled to a first package. Exemplary electronic devices

[0072] Figure 10 illustrates various electronic devices that can integrate any of the aforementioned components, integrated components, integrated circuit (IC) packages, integrated circuit (IC) components, semiconductor components, integrated circuits, dies, intermediaries, packages, stacked packages (PoP), system-in-package (SiP), or systems-on-a-chip (SoC). For example, mobile phone device 1002, laptop device 1004, fixed-location terminal device 1006, wearable device 1008, or motor vehicle 1010 may include components 1000 as described herein. Component 1000 may be any of the components and / or integrated circuit (IC) packages described herein. Devices 1002, 1004, 1006, and 1008, and vehicle 1010 illustrated in Figure 10 are merely exemplary. Other electronic devices may also be characterized by element 1000, including but not limited to the group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablets, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0073] One or more of the elements, programs, features, and / or functions illustrated in Figures 2–5, 6A–6B, 7, 8A–8C, and / or 9–10 may be rearranged and / or combined into a single element, program, feature, or function, or implemented in several elements, programs, or functions. Additional elements, components, programs, and / or functions may also be added without departing from this invention. It should also be noted that Figures 2–5, 6A–6B, 7, 8A–8C, and / or 9–10 and their corresponding descriptions in this invention are not limited to dies and / or ICs. In some implementations, Figures 2–5, 6A–6B, 7, 8A–8C, and / or 9–10 and their corresponding descriptions may be used to manufacture, build, provide, and / or produce elements and / or integrate elements. In some implementations, the components may include dies, integrated components, integrated passive components (IPDs), die packages, integrated circuit (IC) components, component packages, integrated circuit (IC) packages, wafers, semiconductor components, stacked package (PoP) components, thermal components, and / or intermediaries.

[0074] Note that the accompanying drawings in this application may represent actual and / or conceptual representations of various components, elements, objects, packages, integrated components, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all elements and / or components are illustrated for clarity. In some instances, the positioning, location, size, and / or shape of the various components and / or elements in the drawings may be exemplary. In some implementations, the various components and / or elements in the drawings may be optional.

[0075] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or manner described herein as "exemplary" need not be construed as superior to or better than other manners in this case. Similarly, the term "manner" does not require that all manners in this case include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect coupling between two objects (e.g., mechanical coupling). For example, if object A physically contacts object B, and object B contacts object C, then objects A and C can still be considered coupled to each other—even if objects A and C are not in direct physical contact with each other. The term "electrical coupling" can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can be transmitted between the two objects. Electrically coupled objects may or may not have current transmitted between them. The use of the terms "first," "second," "third," and "fourth" (and / or anything higher than fourth) is arbitrary. Any element described can be a first element, a second element, a third element, or a fourth element. For example, an element referred to as a second element can be a first element, a second element, a third element, or a fourth element. The term "enclosure" means that an object can partially or completely enclose another object. The terms "top" and "bottom" are arbitrary. An element located at the top can be situated on top of an element located at the bottom. A top element can be considered a bottom element, and vice versa. As described in this case, a first element situated "above" a second element can mean that the first element is located above or below the second element, depending on how the bottom or top is arbitrarily defined. In another instance, a first element can be situated above (e.g., above) a first surface of a second element, while a third element can be situated above (e.g., below) a second surface of a second element, where the second surface is opposite the first surface. It should be further noted that the term "above," as used in this case in the context of an element being above another element, can be used to indicate that an element is on and / or in another element (e.g., on the surface of an element or embedded in an element). Thus, for example, "first element on second element" can mean: (1) the first element is on the second element but does not directly contact the second element; (2) the first element is on the second element (e.g., on the surface of the second element); and / or (3) the first element is in the second element (e.g., embedded in the second element). A first element located "in" the second element can be partially or completely located in the second element. As used in this case, the terms "about "value X" or "approximately value X" mean within ten percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0076] In some implementations, an interconnect is a component or assembly within a element or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some implementations, an interconnect may include traces, vias, pads, solder pillars, redistributed metal layers, and / or under-bump metallization (UBM) layers. An interconnect may include one or more metal compositions (e.g., a seed layer + metal layer). In some implementations, an interconnect is a conductive material that can be configured to provide an electrical path for signals (e.g., data signals, ground, or power). An interconnect may be part of a circuit. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. Different implementations may use similar or different processes to form interconnects. In some implementations, chemical vapor deposition (CVD) processes and / or physical vapor deposition (PVD) processes are used to form interconnects. For example, sputtering, spraying, and / or plating processes may be used to form interconnects.

[0077] It should also be noted that the various disclosures contained herein can be described as programs illustrated as flowcharts, schematic diagrams, block diagrams, or block diagrams. Although flowcharts can describe operations as a sequential procedure, many operations can be executed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The program terminates when its operations are completed.

[0078] The various features of this case described herein can be implemented in different systems without departing from this case. It should be noted that the foregoing examples are merely illustrative and should not be construed as limiting this case. The descriptions of the various examples are intended to be illustrative, not to limit the scope of the appended claims. Therefore, the teachings of this case can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

[0079] According to a first embodiment, an element includes a first package and a second package. The first package includes a first substrate, at least one gradient interconnect structure coupled to the first substrate, and a first integrated element coupled to the first substrate. The second package is coupled to the first package. The second package includes a second substrate, wherein the second substrate is coupled to the at least one gradient interconnect structure. The second package includes a second integrated element coupled to the second substrate. The gradient interconnect structure may be located between the first substrate and the second substrate. The gradient interconnect structure may include an encapsulation layer and at least one continuous interconnect extending diagonally through the encapsulation layer. The gradient interconnect structure may include an encapsulation layer and at least one continuous interconnect extending vertically and horizontally through the encapsulation layer. The at least one continuous interconnect extending vertically and horizontally through the encapsulation layer includes a lead frame interconnect. The gradient interconnect structure may be coupled to the first substrate via a first plurality of solder interconnects. The gradient interconnect structure may be coupled to the second substrate via a second plurality of solder interconnects. The element may include a PoP (PoP) package. The first substrate may have a first width, and the second substrate may have a second width equal to or less than the first width. The first substrate may have a first width, and the second substrate may have a second width greater than the first width. The component may be selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablets, computers, wearable devices, laptops, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0080] According to a second embodiment, an apparatus includes a first package and a second package. The first package includes a first substrate, a gradient interconnect member coupled to the first substrate, and a first integrated element coupled to the first substrate. The second package is coupled to the first package. The second package includes a second substrate, wherein the second substrate is coupled to the gradient interconnect member. The second package includes a second integrated element coupled to the second substrate. The gradient interconnect member may be located between the first substrate and the second substrate. The gradient interconnect member may include an encapsulation layer and at least one continuous interconnect extending diagonally through the encapsulation layer. The gradient interconnect member may include an encapsulation layer and at least one continuous interconnect extending vertically and horizontally through the encapsulation layer. The at least one continuous interconnect extending vertically and horizontally through the encapsulation layer includes a lead frame interconnect. The gradient interconnect member may be coupled to the first substrate via a first plurality of solder interconnects. The gradient interconnect member may be coupled to the second substrate via a second plurality of solder interconnects. The element includes a stacked package (PoP). The first substrate may have a first width, and the second substrate may have a second width equal to or less than the first width. The first substrate may have a first width, and the second substrate may have a second width greater than the first width. The device may be selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablets, computers, wearable devices, laptops, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0081] According to a third embodiment, a method for manufacturing a component is provided. The method includes the steps of: providing a first package, the first package including a first substrate, at least one gradient interconnect structure coupled to the first substrate, and a first integrated element coupled to the first substrate. The method couples a second package to the first package. The second package includes a second substrate, wherein the second substrate is coupled to the at least one gradient interconnect structure. The second package includes a second integrated element coupled to the second substrate. The gradient interconnect structure may be located between the first substrate and the second substrate. The gradient interconnect structure includes an encapsulation layer and at least one continuous interconnect extending diagonally through the encapsulation layer. The gradient interconnect structure includes an encapsulation layer and at least one continuous interconnect extending vertically and horizontally through the encapsulation layer. The at least one continuous interconnect extending vertically and horizontally through the encapsulation layer includes a lead frame interconnect. The gradient interconnect structure may be coupled to the first substrate via a first plurality of solder interconnects. The gradient interconnect structure may be coupled to the second substrate via a second plurality of solder interconnects. The first substrate may have a first width. The second substrate has a second width equal to or less than the first width. The first substrate may have a first width. The second substrate may have a second width greater than the first width.

[0082] Phase 1: Phase 2 Phase 3 4: Stage 5: Stage 6: Stage 7: Stage 8: Stage 100: Package 102:Substrate 105: Integrated Components 106: Board 107: Integrated Components 120: Dielectric layer 122: Interconnection 124: Solder Interconnect 154: Solder Interconnect 174: Solder interconnect 200: Components 201: Integrated Components 202: First substrate 203: Integrated Components 204: Second substrate 205: Integrated Components 206: Gradient Interconnect Structure 207: Components 208: Encapsulation layer 209: Board 212: Welded column interconnection 220: Dielectric layer 222: Interconnection 226: Solder interconnect 234: Solder interconnect 240: Dielectric layer 242: Interconnection 244: Solder interconnect 250: cavity 254: Solder interconnect 260: Encapsulation layer 262: Interconnection 264: Solder Interconnect 274: Solder interconnect 290: First Package 292: Second Package 300: Components 306: Gradient Interconnect Structure 362: Interconnection 363: Bend 390: First Package 400: Components 406: Gradient Interconnect Structure 462: Interconnection 463: Bend 490: First Package 500: Components 506: Gradient Interconnect Structure 562: Interconnection 590: First Package 600: Conductive material 602: Adhesive tape 610: cavity 700: Method 705: Steps 710: Steps 715: Steps 720: Steps 725: Steps 730: Steps 900: Method 905: Steps 910: Steps 915: Steps 920: Steps 925: Steps 930: Steps 935: Steps 1000: Components 1002: Mobile phone equipment 1004: Laptop devices 1006: Fixed-location terminal equipment 1008: Wearable devices 1010: Motor vehicles

[0083] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An electronic component, comprising: A first package, the first package comprising: a first substrate; at least one gradient interconnect structure coupled to the first substrate, wherein the at least one gradient interconnect structure includes a first gradient interconnect structure comprising: a first encapsulation layer; and at least one continuous first interconnect extending diagonally through the first encapsulation layer, wherein the at least one continuous first interconnect includes a lead frame interconnect; and a first integrated element coupled to the first substrate; and a second package coupled to the first package, the second package comprising: a second substrate, wherein the second substrate is coupled to the at least one gradient interconnect structure; and a second integrated element coupled to the second substrate.

2. The element of claim 1, wherein the at least one gradient interconnect structure is located between the first substrate and the second substrate.

3. The element of claim 1, wherein the at least one gradient interconnect structure includes a second gradient interconnect structure, the second gradient interconnect structure comprising: a second encapsulation layer; and at least one continuous second interconnect extending diagonally through the second encapsulation layer.

4. The element of claim 1, wherein the at least one gradient interconnect structure includes a second gradient interconnect structure, the second gradient interconnect structure comprising: a second encapsulation layer; and at least one continuous second interconnect extending vertically and horizontally through the second encapsulation layer.

5. The element of claim 4, wherein the at least one continuous second interconnect extending vertically and horizontally through the second encapsulation layer comprises a lead frame interconnect.

6. The element of claim 1, wherein the first gradient interconnect structure is coupled to the first substrate via a first plurality of solder interconnects; and wherein the first gradient interconnect structure is coupled to the second substrate via a second plurality of solder interconnects.

7. The element of claim 1, wherein the element includes a PoP (PoP) package.

8. The element of claim 1, wherein the first substrate has a first width, and wherein the second substrate has a second width equal to or less than the first width.

9. The element of claim 1, wherein the first substrate has a first width, and wherein the second substrate has a second width greater than the first width.

10. The element of claim 1, wherein the element is selected from a group comprising: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

11. A method for manufacturing an electronic component, comprising the following steps: A first package is provided, the first package comprising: a first substrate; at least one gradient interconnect structure coupled to the first substrate, wherein the at least one gradient interconnect structure includes a first gradient interconnect structure comprising: a first encapsulation layer; and at least one continuous first interconnect extending diagonally through the first encapsulation layer, wherein the at least one continuous first interconnect includes a lead frame interconnect; and a first integrated element coupled to the first substrate; and a second package coupled to the first package, the second package comprising: a second substrate, wherein the second substrate is coupled to the at least one gradient interconnect structure; and a second integrated element coupled to the second substrate.

12. The method of claim 11, wherein the at least one gradient interconnect structure is located between the first substrate and the second substrate.

13. The method of claim 11, wherein the at least one gradient interconnect structure includes a second gradient interconnect structure, the second gradient interconnect structure comprising: a second encapsulation layer; and at least one continuous second interconnect extending diagonally through the second encapsulation layer.

14. The method of claim 11, wherein the at least one gradient interconnect structure comprises: First, the second package is sealed; and at least one continuous second interconnect extending vertically and horizontally through the second encapsulation layer.

15. The method of claim 14, wherein the at least one continuous second interconnect extending vertically and horizontally through the second encapsulation layer comprises a lead frame interconnect.

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