Method for forming layer on substrate, and semiconductor processing system

Abstract

A method for forming a layer on a substrate includes providing a substrate in a reactor of a semiconductor processing system, the reactor having a separator that separates an upper chamber from a lower chamber and a substrate holder therebetween, the substrate having an upper surface and a lower surface. A wafer is positioned within the reactor using the substrate holder such that the upper surface defines the upper chamber, a silicon-containing gas flows through the upper chamber to deposit a layer on the upper surface, and simultaneously, a halogen-containing gas flows through the lower chamber to etch a deposited film on at least one wall defining the lower chamber. A semiconductor processing system is also described.

Description

[Technical Field]

[0001] This disclosure generally relates to the deposition of silicon onto a substrate using a semiconductor processing system. More specifically, this disclosure relates to confining the deposition of silicon onto the inner surfaces and structures of a semiconductor processing system while depositing silicon onto a substrate in such an apparatus. [Previous Technology]

[0002] Silicon deposition technology is widely used to deposit silicon on wafers to manufacture semiconductor devices, such as power electronic components and very large-scale integrated circuits. Silicon deposition can be achieved by techniques such as flowing silicon precursors through a reactor housing the wafer. Typically, the reactor maintains an environment conducive to silicon deposition, allowing silicon to be deposited on the wafer surface by the silicon precursors flowing through the reactor. Once a silicon layer of suitable thickness has been deposited on the substrate surface, the wafer is unloaded from the reactor and transported for further processing.

[0003] One challenge of this technology is that silicon deposition on the wafer surface is typically accompanied by silicon deposition on other surfaces and structures within the reactor. For example, in some reactors, silicon films may be deposited on internal surfaces and / or movable parts located within the reactor, such as on reactor walls and / or on movable structures used for loading and unloading wafers. These concurrent silicon depositions can reduce the reliability of process tools, for example by reducing the transmittance of the reactor walls (and thus limiting the ability to communicate heat from externally located heat sources through the reactor walls), and / or by creating interference between movable structures and adjacent structures within the reactor. Silicon nodule defects may also (or alternatively) occur between the back side of the wafer and a chuck used to support the wafer during deposition. Such silicon nodule defects may hold the wafer to the chuck, potentially causing substrate damage during wafer unloading and / or during subsequent wafer processing. In deposition operations used to deposit relatively thick silicon layers, the development of silicon films and stamen-like defects can be particularly problematic.

[0004] Various countermeasures exist for silicon bud defects and / or silicon film tendencies within the reactor during deposition operations. For example, some silicon deposition operations may include prior and / or subsequent cleaning events to remove silicon films that have formed within the reactor during previous deposition operations. Scheduled maintenance may also be employed to periodically remove silicon films from within the reactor, such as through reactor disassembly, to provide access to internal surfaces and structures that previously had no access to silicon film removal. In some techniques, the deposition operation itself may be divided into two or more deposition events to allow for reactor cleaning between deposition events. This limits the size of silicon bud defects formed between the wafer and chuck during deposition operations, limiting the tendency of bud defects to hold the wafer to the chuck and / or cause wafer damage.

[0005] Such methods and apparatus are generally considered suitable for their intended purpose. However, there is still a need in the art for improved methods and semiconductor processing systems for depositing silicon layers on substrates. This disclosure provides solutions to one or more of these needs. [Summary of the Invention]

[0006] The provided method is for forming a silicon layer on a substrate. The method includes providing a substrate in a reactor of a semiconductor processing system, the reactor including a substrate holder and a separator separating an upper chamber from a lower chamber. The substrate has an upper surface and a lower surface opposite to the upper surface. The substrate is positioned in the upper chamber of the reactor using this substrate, and a silicon-containing gas flows through the upper chamber to deposit a layer on the upper surface of the substrate. Simultaneously, a halogen-containing gas flows through the lower chamber to etch a deposited film on at least one wall defining the lower chamber of the reactor. The halogen-containing gas etches the upper surface of the substrate to control the thickness of the silicon layer at a periphery of the upper surface of the substrate.

[0007] In some instances, this method may include etching the lower surface of the substrate with the halogen-containing gas to limit the deposition of silicon on the lower surface of the substrate.

[0008] In some instances, this method may include allowing the halogenated gas to flow through a gap defined between the substrate and the separator into the upper chamber, the separator separating the upper chamber of the reactor from the lower chamber.

[0009] In some instances, this method may include tuning the edge thickness of the silicon layer at a peripheral portion of the upper surface of the substrate to a target profile. Tuning may, for example, be achieved by adjusting the mass flow rate of the halogenated gas through the lower chamber of the reactor.

[0010] In some instances, this method may include flowing a purge gas through the lower chamber of the reactor, the halogenated gas being mixed with the purge gas.

[0011] In some instances, this method may include flowing a carrier gas, comprising a halogen-containing gas, through the upper chamber of the reactor.

[0012] In some instances, this method may include activating the halogen-containing gas before allowing the halogen-containing gas to flow through the lower chamber of the reactor.

[0013] In some instances, this method may include allowing a dopant-containing gas to flow through the upper chamber of the reactor while the halogen-containing gas flows through the lower chamber of the reactor.

[0014] In some instances, this method may include selecting the halogen-containing gas to include at least one of the following: hydrogen chloride (HCl), chlorine (Cl2); and fluorine (F2).

[0015] In some instances, this method may include selecting the silica-containing gas to include at least one of the following: silane (SiH4); disylane (Si2H6); trisilane (Si3H8); and tetrasilane (Si4H10).

[0016] In some instances, the method may include selecting a carrier gas to include at least one of the following: nitrogen (N2), hydrogen (H2), helium (He), argon (Ar) and any other rare gas; the method further includes flowing the silicon-containing gas and the carrier gas through the upper chamber of the reactor.

[0017] In some instances, the method may further include selecting a dopant gas comprising at least one of the following: diborane (B2H6); phosphine (PH3); and arsine (AsH3), and the method further includes flowing the silicon-containing gas and the dopant gas through the upper chamber of the reactor.

[0018] In some instances, this method may include maintaining the reactor at a temperature between about 300 °C and about 750 °C, or between about 550 °C and about 750 °C, while allowing the halogenated gas to flow through the lower chamber of the reactor.

[0019] In some instances, this method may include maintaining a pressure between about 10 Torr and about 900 Torr within the reactor while allowing the halogenated gas to flow through the lower chamber of the reactor.

[0020] In some instances, this method may include a duration for which the halogen-containing gas flows through the lower chamber is substantially equal to the duration for which the silicon-containing gas flows through the upper chamber of the reactor.

[0021] In some instances, this method may include allowing the halogenated gas to flow through the lower chamber of the reactor for between about 2 minutes and about 25 minutes.

[0022] A semiconductor processing system is also provided. This system includes a reactor having an upper chamber and a lower chamber. The reactor is configured to support a substrate having an upper surface and a lower surface opposite the upper surface therein. A silicon-containing gas source is connected to the upper chamber of the reactor and configured to supply a silicon-containing gas to the reactor. A halogen-containing gas source is connected to the lower chamber of the reactor and configured to supply a halogen-containing gas to the reactor. A controller is operatively connected to the silicon-containing gas source and the halogen-containing gas source. This controller, in response to instructions stored in a memory, positions the substrate in the upper chamber of the reactor using a substrate holder, allows a silicon-containing gas from a silicon-containing gas source to flow through the upper chamber of the reactor to deposit a layer on the upper surface of the substrate, and simultaneously allows a halogen-containing gas from a halogen-containing gas source to flow through the lower chamber of the reactor to etch a deposited film from at least one wall defining the lower chamber of the reactor. These instructions further cause the controller to allow the halogen-containing gas to flow through the lower chamber of the reactor to etch the upper surface of the substrate with the halogen-containing gas, thereby controlling the edge thickness of the silicon layer deposited on the surface of the substrate.

[0023] In some instances, the halogen gas source may be independently connected to the upper chamber and the lower chamber of the reactor.

[0024] In some embodiments, the semiconductor device may include a first mass flow controller (MFC) and a second mass flow controller. The first mass flow controller connects the halogen-containing gas source to the upper chamber of the reactor. The second mass flow controller connects the halogen-containing gas source to the lower chamber of the reactor.

[0025] In some instances, the semiconductor device may include a purge gas source connected to the lower chamber of the reactor to allow a purge gas flow to flow into the lower chamber along with the halogen-containing gas flowing through the lower chamber of the reactor.

[0026] This disclosure is provided to introduce a series of concepts in a simplified form. These concepts are further described in detail in the following detailed examples of this disclosure. This disclosure is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

Implementation Method

[0029] Reference is now made to the accompanying drawings, in which similar structural features or configurations are disclosed, as indicated by similar reference numerals. For purposes of explanation and illustration, and not limitation, partial views of an example of a semiconductor processing system according to this disclosure are shown in Figure 1 and are generally designated by reference character 100. As will be described, Figures 2 through 10 provide other embodiments, or configurations, of the semiconductor processing system and method for forming a silicon layer on a substrate according to this disclosure. The apparatus and methods described herein may use low-pressure chemical vapor deposition (CVD) or epitaxial techniques to deposit silicon layers on a substrate (such as a silicon wafer) for the fabrication of very large scale integrated (VLSI) circuits. However, this disclosure is not limited to low-pressure chemical vapor deposition, VLSI circuits, or epitaxy in its entirety.

[0030] Referring to Figure 1, a semiconductor processing system 100 is shown. The semiconductor processing system 100 may include a reactor 102, a separator 104, and a substrate holder 106. The semiconductor processing system 100 may also include a silicon-containing gas source 108, a halogen-containing gas source 110, a purge gas source 144, and a substrate transporter 136. In the illustrated example, the semiconductor processing system 100 is a chemical vapor deposition (CVD) semiconductor processing system, such as an atmospheric pressure chemical vapor deposition apparatus. However, those skilled in the art will appreciate that low-pressure chemical vapor deposition apparatuses, high-pressure chemical vapor deposition apparatuses, and atomic layer deposition apparatuses may also benefit from this disclosure.

[0031] Reactor 102 is formed of a transmissive material 114 (e.g., a ceramic material like quartz) and has a hollow interior 116 containing a separator 104. The separator 104 is fixed within the interior 116 of reactor 102, dividing the interior 116 into an upper chamber 118 and a lower chamber 120, and defining a separator orifice 122 therethrough. The separator orifice 122 connects the lower chamber 120 to the upper chamber 118, providing fluid communication between the upper chamber 118 and the lower chamber 120. One or more lamps (or lamp arrays) 124 may be positioned outside reactor 102 to transmit thermal energy into reactor 102 through the transmissive material 114 forming reactor 102.

[0032] A substrate holder 106 is supported within the interior 116 of the reactor 102 and configured to hold the substrate 10. The substrate holder 106 is operatively connected to a substrate holder drive 128. The substrate holder drive 128 is configured to displace the substrate holder 106 along a rotation axis 126 between a first position A (shown in Figure 2) and a second position B (Figure 3) for loading the substrate 10 into the reactor 102, positioning the substrate 10 for silicon deposition on the substrate 10, and unloading the substrate 10 from the reactor 102. The substrate holder drive 128 is also configured to rotate the substrate holder 106 about the rotation axis 126 by a radius R during silicon deposition onto the substrate 10. In some embodiments, one or more lifter pins 130 (shown in Figure 2) may be movably supported by the substrate holder 106 to allow the substrate 10 to sit on or leave the substrate holder 106. Reactor 102 may be as shown and described in U.S. Patent No. 7,462,239 to Brabant et al., published on December 9, 2009, the contents of which are incorporated herein by reference in their entirety.

[0033] The substrate 10 has an upper surface 12, an opposing lower surface 14, and an edge or bevel 16. The edge or bevel 16 of the substrate 10 couples the upper surface 12 of the substrate 10 to the lower surface 14 of the substrate 10. Considered herein, when mounted on a substrate holder 106, the upper surface 12 of the substrate 10 is disposed along a rotation axis 126 at a portion axially overlapping with the substrate holder 106, the lower surface 14 of the substrate 10 is disposed along the rotation axis 126 at a portion between the upper surface 12 and the substrate holder 106, and the edge or bevel 16 of the substrate 10 extends about the rotation axis 126 for depositing a silicon layer 18 on the upper surface 12 of the substrate 10. In some embodiments, the substrate 10 is a silicon wafer. According to some embodiments, the substrate 10 may include at least a portion of a power electronic device or a very large-scale integrated circuit formed thereon.

[0034] The purge gas source 144 may be connected to the reactor 102, may include a purge gas 34, and may be configured to flow through the lower chamber 120 of the reactor 102 and mix with the halogen-containing gas 28. The purge gas 34 may include, for example, nitrogen (N2) or argon (Ar).

[0035] A silicon-containing gas source 108 is connected to reactor 102 and includes silicon-containing gas 20. The silicon-containing gas source 108 may be connected to reactor 102 and configured to provide flow of silicon-containing gas 20 to reactor 102. Reactor 102 may be configured to allow silicon-containing gas 20 received from silicon-containing gas source 108 to flow through an upper chamber 118 of reactor 102. Reactor 102 may be further configured to maintain an environment suitable for depositing silicon layer 18 onto the upper surface 12 of substrate 10. Silicon layer 18 may be deposited using epitaxial techniques, such as those shown and described in U.S. Patent No. 10,446,393 to Bhargava et al., published October 15, 2019, the contents of which are incorporated herein by reference in their entirety. The silica-containing gas 20 may include, for example, silane (SiH4), disilane (Si2H6), trisilane (Si3H8) or tetrasilane (Si4H10).

[0036] As discussed above, allowing silicon-containing gas 20 to flow through the upper chamber 118 of reactor 102 may cause silicon bud defects to form within the reactor used for deposition. For example, as shown in Figure 1, silicon bud defects 22 may form between the lower surface 14 of substrate 10 and substrate holder 106. Such silicon bud defects can cause damage to substrate 10 during unloading from reactor 102. Such silicon bud defects can also cause damage to substrate 10 in subsequent processing operations.

[0037] As discussed above, allowing the silicon-containing gas 20 to flow through the upper chamber 118 can (alternatively or additionally) cause a silicon film 24 to form on the wall 132 defining the lower chamber 120 of the reactor 102. A silicon film 26 (shown in Figure 2) can also be formed on the surface of one or more lift pins 130 supported by the substrate holder 106. Such silicon films can potentially reduce the reliability of the semiconductor processing system 100, for example by limiting the transmittance of the wall 132 and / or by creating interference between one or more lift pins 130 and the substrate holder 106.

[0038] To limit the risk of damage to the substrate 10 and / or reliability liability caused by such silicon bud defects and / or silicon films to the silicon processing system 100, the semiconductor processing system 100 includes a halogen-containing gas source 110. The halogen-containing gas source 110 is connected to a reactor 102 and includes a halogen-containing gas 28. It is understood herein that the halogen-containing gas source 110 is connected to the lower chamber 120 of the reactor 102 and configured to provide the halogen-containing gas 28 to the reactor 102. The reactor 102 is then configured to allow the halogen-containing gas 28 to flow through the lower chamber 118 of the reactor 102 while the silicon-containing gas 20 flows through the upper chamber 118 of the reactor 102, to etch a deposited film on at least one inner surface and / or structure within the reactor 102. The halogen-containing gas 28 may include, for example, hydrochloric acid or hydrogen chloride (HCl), chlorine (Cl2), or fluorine (F2).

[0039] In some instances, the flow of halogen-containing gas 28 etches a deposited film on at least one of the walls 132 of the lower chamber 120, limiting (or completely eliminating) film deposition, such as silicon film 24, on at least one of the walls 132. According to some instances, the flow of halogen-containing gas 28 may (alternatively or additionally) etch silicon on the lower surface 14 of the substrate 10, limiting (or completely eliminating) the formation of silicon bud-like defects, such as silicon bud-like defects 22 between the substrate 10 and the substrate holder 106. It is also considered herein that, according to some instances, the flow of halogen-containing gas 28 may etch a peripheral portion 40 of the silicon layer 18 (shown in Figure 5) during the deposition of the silicon layer 18 onto the upper surface 12 of the substrate 10, for example, to tune the thickness profile 42 of the silicon layer 18 at the peripheral portion 40 of the silicon layer 18 (shown in Figure 5).

[0040] Referring to Figures 2 through 6, a semiconductor processing system 100 is shown forming a silicon layer 18 on the upper surface 12 of a substrate 10 (shown in Figure 1). As shown in Figure 2, the substrate 10 is first provided in a reactor 102 for depositing the silicon layer 18 on the upper surface 12 of the substrate 10. Specifically, the substrate holder 106 is first translated along the rotation axis 126 to a first position A, for example, a loading / unloading position. Next, a gate valve 134 connecting the reactor 102 to the external environment is opened to provide access for the substrate transporter 136 to the interior 116 of the reactor 102. The substrate transporter 136 extends an arm / end effector 138 that supports the substrate 10 across the upper chamber 118 via the gate valve 134 and aligns the substrate 10 above the substrate holder 106.

[0041] Once the substrate 10 is aligned with the substrate holder 106, one or more lifting pins 130 are then deployed from the substrate holder 106. As the lifting pins 130 are deployed from the surface of the substrate holder 106, they contact the lower surface 14 of the substrate 10, transferring the substrate 10 from the arm / end effector 138 to the lifting pins 130. Once the substrate 10 has been transferred, the substrate transporter 136 retracts the arm / end effector 138 from the interior 116 of the reactor 102 via the gate valve 134. The gate valve 134 then closes, isolating the interior 116 of the reactor 102 from the external environment.

[0042] As shown in Figure 3, the substrate 10 is then positioned in the reactor 102 for deposition of the silicon layer 18 (shown in Figure 1). Specifically, one or more lift pins 130 (shown in Figure 2) are retracted into the substrate holder 106 to allow the substrate 10 to rest against the substrate holder 106. The substrate holder 106 can then be displaced along the rotation axis 126 from a first position A (shown in Figure 2) to a second position B, for example, the deposition position. In the second position B, the substrate 10 is positioned within the upper chamber 118 of the reactor 102, and the substrate holder 106 itself is at least partially disposed in the separator aperture 122. Next, the substrate holder drive 128 rotates the substrate holder 106 (and the substrate 10) about the rotation axis 126, and the temperature and pressure within the interior 116 of the reactor 102 are adjusted for deposition of the silicon layer 18 (shown in Figure 1) onto the upper surface 12 of the substrate 10.

[0043] As shown in Figure 4, the silicon-containing gas source 108 then supplies silicon-containing gas 20 to the reactor 102. The silicon-containing gas 20 flows through the upper chamber 118 of the reactor 102. As the silicon-containing gas 20 flows through the upper chamber 118, a silicon layer 18 is deposited on the upper surface 12 of the substrate 10.

[0044] While silicon-containing gas 20 flows through reactor 102 and silicon layer 18 is deposited on the upper surface 12 of substrate 10, halogen-containing gas source 110 supplies halogen-containing gas 28 to reactor 102. Reactor 102 allows halogen-containing gas 28 to flow through lower chamber 120 of reactor 102. As halogen-containing gas 28 flows through lower chamber 120 of reactor 102, halogen-containing gas 28 etches a film deposited on at least one of: (a) the wall 132 (shown in Figure 1) defining lower chamber 120 of reactor 102, (b) the lower surface 14 of substrate 10, and (c) and / or the peripheral portion 40 of silicon layer 18 (shown in Figure 5) when silicon layer 18 is deposited on upper surface 12 of substrate 10.

[0045] In some embodiments, the halogen-containing gas 28 and the silicon-containing gas 20 flow simultaneously through the upper chamber 118 and the lower chamber 120, respectively. This can improve the throughput of the semiconductor processing system 100, for example, by limiting (or completely eliminating) the need for etching a deposited film on at least one of the walls 132 defining the lower chamber 120 of the reactor 102 between deposition events. According to some embodiments, the halogen-containing gas 28 may begin flowing through the lower chamber 120 before the silicon-containing gas 20 begins flowing through the upper chamber 118, or after the flow of the silicon-containing gas 20 through the upper chamber 118 of the reactor 102 has begun. It is also considered that, according to some embodiments, the halogen-containing gas 28 may stop flowing through the lower chamber 120 before the flow of the silicon-containing gas 20 through the upper chamber 118 has ceased, or after the flow of the silicon-containing gas 20 through the upper chamber 118 of the reactor 102 has ceased.

[0046] In some embodiments, the semiconductor processing system 100 may include a dopant gas source 140. In such embodiments, the dopant gas source 140 may be connected to the reactor 102 and configured to allow dopant gas 30 and silicon-containing gas 20 to flow through an upper chamber 118 for doping a silicon layer 18 deposited on the upper surface 12 of the substrate 10. The dopant gas 30 may include, for example, diborane (B2H6), phosphine (PH3), or arsene (AsH3).

[0047] According to certain embodiments, the semiconductor processing system 100 may include a carrier gas source 142. In such embodiments, the carrier gas source 142 may be connected to the reactor 102 and may be configured to allow a carrier gas 32 to flow through an upper chamber 118 to carry silicon-containing gas 20 and / or dopant gas 30 through the upper chamber 118 of the reactor 102. The dopant gas 30 may include, for example, diborane (B2H6), phosphine (PH3), or arsine (AsH3).

[0048] This document takes into consideration that reactor 102 may be configured to maintain a temperature between about 300 °C and about 750 °C or between about 550 °C and about 1220 °C within reactor 102 while allowing halogen-containing gas 28 to flow through the lower chamber 120 of reactor 102. More specifically, reactor 102 may be configured to maintain a temperature between about 300 °C and about 750 °C or between about 550 °C and about 1220 °C within reactor 102 while allowing halogen-containing gas 28 to flow through the lower chamber 120 within the upper chamber 118 of reactor 102, and while allowing halogen-containing gas 28 to flow through the lower chamber 120 of reactor 102.

[0049] This document also considers that reactor 102 can be configured to maintain a pressure between about 10 Torr and about 800 Torr within reactor 102 while halogen-containing gas 28 flows through the lower chamber 118 of reactor 102. More specifically, reactor 102 can be configured to maintain a pressure between about 10 Torr and about 800 Torr within the upper chamber 118 of reactor 102 while halogen-containing gas 28 flows through the lower chamber 120 of reactor 102.

[0050] This document further considers that, according to certain examples, reactor 102 may be configured to allow silicon-containing gas 20 to flow through upper chamber 118 while simultaneously allowing halogen-containing gas 28 to flow through lower chamber 120 for approximately 2 minutes to approximately 25 minutes. In some examples, reactor 102 may be configured to allow silicon-containing gas 20 to flow through upper chamber 118 while simultaneously allowing halogen-containing gas 28 to flow through lower chamber 120 for approximately 35 seconds to approximately 65 seconds.

[0051] As shown in Figure 5, the simultaneous flow of silicon-containing gas 20 through the upper chamber 118 of reactor 102 and the flow of halogen-containing gas 28 through the lower chamber 120 enables etching of deposited films at least on surfaces and / or features located within reactor 102. For example, as indicated by flow arrow 34, halogen-containing gas 28 can etch deposited films (e.g., silicon film 24) on at least one of the walls 132 defining the lower chamber 120 of reactor 102. Furthermore, as indicated by flow arrow 36, halogen-containing gas 28 can also (or alternatively) etch silicon on the lower surface 14 of substrate 10, such as silicon dovetail defects 22 thereon (shown in Figure 1). Etching of silicon on the lower surface 14 of substrate 10 can, for example, be achieved by a hole 146 extending through substrate holder 106 and fluidly coupled to the lower chamber 120 of reactor 102 and the lower surface 14 of substrate 10.

[0052] In some instances, the silicon layer 18 may be etched by the flow of halogen-containing gas 28 through the lower chamber 120, since the silicon layer 18 is deposited on the upper surface 12 of the substrate 10. Specifically, as indicated by flow arrow 38, it is considered that a portion of the halogen-containing gas 28 flowing through the lower chamber 120 may flow through the gap 148 defined between the substrate holder 106 and the separator 104 and enter the upper chamber 118. Once in the upper chamber 118, the halogen-containing gas 28 slows down the deposition of silicon within the peripheral portion 40 of the silicon layer 18, reducing the thickness of the silicon layer 18 within the peripheral portion 40 relative to the nominal thickness of the silicon layer 18 deposited within the peripheral portion 40 in other cases.

[0053] This document also considers that the flow of the halogen-containing gas 28 through the lower chamber 120 can be used to tune the thickness of the silicon layer 18 within the peripheral portion 40 of the silicon layer 18. For example, the halogen-containing gas 28 can make the thickness of the silicon layer 18 within the peripheral portion 40 more uniform than that formed by the silicon-containing gas 20 flowing through the upper chamber 118 of the reactor 102 in other cases, as indicated by reference letter A in Figure 5. Alternatively, the halogen-containing gas 28 can make the thickness of the silicon layer 18 within the peripheral portion 40 more concave or convex than that formed by the silicon-containing gas 20 flowing through the upper chamber 118 of the reactor 102 in other cases, as indicated by reference letter B in Figure 5.

[0054] As shown in Figure 6, once the silicon layer 18 is deposited on the upper surface 14 of the substrate 10, the substrate 10 is unloaded from the reactor 102. Unloading can be achieved by first stopping (a) the flow of silicon-containing gas 20 (shown in Figure 1) to the upper chamber 118 of the reactor 102, and (b) the flow of halogen-containing gas 28 (shown in Figure 1) to the lower chamber 120 of the reactor 102. The rotation R (shown in Figure 1) of the substrate holder 106 about the rotation axis 126 can be stopped. The substrate holder 106 can be translated from the second position B (shown in Figure 3) to the first position A, and one or more lifting pins 130 can be deployed from the substrate transporter 136 to displace the substrate 10 from the substrate holder 106.

[0055] Movement of one or more lift pins 130 can displace the substrate 10 from the upper surface 12 of the substrate holder 106. A gate valve 134 can be opened, allowing the substrate transporter 136 to extend the arm / end effector 138 into the upper chamber 118 of the reactor 102, with the arm / end effector 138 inserted between the substrate 10 and the substrate holder 106. Subsequently, one or more lift pins 130 can retract to transfer the substrate 10 to the arm / end effector 138, and the arm / end effector 138 with the substrate 10 can then retract from the reactor 102. The reactor 102 can then be used in subsequent deposition operations by loading another substrate into the reactor 102.

[0056] Referring to Figure 7, a semiconductor processing system 200 is shown. The semiconductor processing system 200 is similar to the semiconductor processing system 100 (shown in Figure 1) and additionally includes a remote plasma unit 202. The remote plasma unit 202 connects a halogen-containing gas source 110 to the lower chamber 120 of the reactor 102 and can be configured to activate the halogen-containing gas 28. As will be understood by those skilled in the art, the connection between the remote plasma unit 202 and the lower chamber 120 allows the use of activated halogen-containing gases, such as fluorine (F2), to etch deposited films onto one or more of the walls 132 defining the lower chamber 120 of the reactor 102. Such gases enable the silicon layer 18 to be deposited at relatively low temperatures, allowing the substrate 10 to include materials that cannot withstand relatively high deposition temperatures.

[0057] Referring to Figure 8, a semiconductor processing system 300 is shown. The semiconductor processing system 300 is similar to the semiconductor processing system 100 (shown in Figure 1), and additionally includes a controller 302, a silicon-containing gas mass flow controller (MFC) 304, and a halogen-containing gas mass flow controller 306. The controller 302 is operatively connected to the semiconductor processing system 300 to allow halogen-containing gas 28 to flow through the lower chamber 120 while silicon-containing gas 20 flows through the upper chamber 118 of the reactor 102.

[0058] In the illustrated example, controller 302 is operatively connected to semiconductor processing system 300 via silicon-containing gas mass flow controller 304 and halogen-containing gas mass flow controller 306. Halogen-containing gas mass flow controller 306 then connects halogen-containing gas source 110 to the lower chamber 120 of reactor 102 to allow halogen-containing gas 28 to flow through the lower chamber 120 of reactor 102. Silicon-containing gas mass flow controller 304 further connects this silicon-containing gas source 108 to the upper chamber 118 of reactor 102 to allow silicon-containing gas 20 to flow through the upper chamber 118 of reactor 102. One (or both) of halogen-containing gas mass flow controller 304 and silicon-containing gas mass flow controller 306 may include, for example, a metering valve for metering the gas flowing through it.

[0059] The controller 302 includes a device interface 308, a user interface 310, a processor 312, and a memory 314. The device interface 308 connects the controller 302 to the semiconductor processing system 300, for example, via one or more of a halogen-containing gas mass flow controller 304, a silicon-containing gas mass flow controller 306, a substrate holder driver 128 (shown in Figure 1), and a substrate transporter 136 (shown in Figure 1). The user interface 310 is configured to display output to a user and / or receive input from a user, such as recipe selection. The processor 312 is operatively connected to the user interface 310 and configured to communicate with the semiconductor processing system 300 via the device interface 308. The processor 312 is also configured to communicate with the memory 314.

[0060] Memory 314 includes a non-transitory machine-readable medium having a plurality of program modules 316 recorded thereon. Each program module 316 has instructions recorded therein, which, when read by processor 312, cause processor 312 to perform certain operations, thereby responding to the instructions recorded thereon by controller 302. The operation includes method 500 (shown in Figure 10), which is used to deposit silicon onto a substrate, for example, to deposit a silicon layer 18 onto the upper surface 12 of substrate 10.

[0061] Referring to Figure 9, a semiconductor processing system 400 is shown. The semiconductor processing system 400 is similar to the semiconductor processing system 100 (shown in Figure 1) and is configured to provide independent flows of halogen-containing gas 28 to both the upper chamber 118 of the reactor 102, for example, a lower chamber halogen-containing gas flow and an upper chamber halogen-containing gas flow. The independent flow enables the halogen-containing gas 28 to be provided to the lower chamber 120 as a lower chamber halogen-containing gas flow to etch a deposited film on at least one inner surface and / or structure within the reactor 102, while the halogen-containing gas 28 is further provided to the upper chamber 118 to serve as a carrier gas for the silicon-containing gas 20.

[0062] In the illustrated example, independent halogenated gas flows are provided to the semiconductor processing system 400 by a first halogenated gas mass flow controller (MFC) 402, a first halogenated gas conduit 404, a second halogenated gas mass flow controller 406, and a second halogenated gas conduit 408. The first halogenated gas mass flow controller 402 connects the halogenated gas source 110 to the lower chamber 120 of the reactor 102 via the first halogenated gas conduit 404. The second halogenated gas mass flow controller 406 connects the halogenated gas source 110 to the upper chamber 118 of the reactor 102 via the second halogenated gas conduit 408.

[0063] In some embodiments, the first halogenated gas mass flow controller 402 and the second halogenated gas mass flow controller 406 are operatively associated with the controller 410 to provide halogenated gas flow from the upper chamber to the upper chamber 118 and halogenated gas flow from the lower chamber to the lower chamber 120 of the reactor 102. As will be appreciated by those skilled in the art in light of this disclosure, other configurations may be used to provide independent flow of halogenated gas 28 to the lower chamber 120 and the upper chamber 118, and remain within the scope of this disclosure.

[0064] Referring to Figure 10, a method 500 for forming a silicon layer on a substrate is shown. As shown in block 510, a substrate is provided in a reactor of a semiconductor processing system, for example, substrate 10 (shown in Figure 1) provided in reactor 102 (shown in Figure 1) of semiconductor processing system 100 (shown in Figure 1). The substrate is then positioned within the reactor using a substrate holder, such as substrate holder 106 (shown in Figure 1), as shown in block 520. It is understood that the substrate can be positioned in the upper chamber of the reactor, for example, such that substrate 10 (shown in Figure 1) is in the upper chamber 118 (shown in Figure 1) of reactor 102 (shown in Figure 1).

[0065] Once the substrate is positioned within the reactor, a silicon-containing gas, such as silicon-containing gas 20 (shown in Figure 1), is flowed through the upper chamber of the reactor to deposit a layer on the upper surface of the substrate, as shown in block 530. The silicon-containing gas causes a silicon layer, such as silicon layer 18 (shown in Figure 1), to be deposited on the upper surface of the substrate, as shown in block 532. Simultaneously with the silicon-containing gas flowing through the upper chamber of the reactor, a halogen-containing gas is flowed through the lower chamber of the reactor; for example, while the silicon-containing gas flows through the upper chamber of the reactor, halogen-containing gas 28 (shown in Figure 1) flows through the lower chamber 120 (shown in Figure 1) of the reactor 102, as shown in block 540. In some embodiments, a purge gas may flow through the lower chamber of the reactor along with the halogen-containing gas; for example, purge gas 34 (shown in Figure 4), as shown in block 550.

[0066] This document considers that halogen-containing gases can etch the upper surface of a substrate to control the thickness of a silicon layer deposited on the upper surface of the substrate, for example, controlling the thickness of silicon layer 18 (shown in Figure 1) within the peripheral portion 40 (shown in Figure 5), as shown in block 580. In some instances, method 500 may include etching silicon on the lower surface of the substrate, for example, lower surface 14 (shown in Figure 1), as shown in block 570. According to some instances, method 500 includes etching a deposited film on at least one wall defining a lower chamber of the reactor, for example, wall 132 (shown in Figure 1) of lower chamber 120 (shown in Figure 1), as shown in block 560. Etching the upper surface of the silicon layer may include controlling the thickness of the silicon layer within a peripheral portion of the silicon layer, for example, peripheral portion 40 (shown in Figure 5), as shown in block 582. Etching the surface above the silicon layer may include tuning the thickness profile of the silicon layer within the peripheral portion of the silicon layer, as shown in block 584.

[0067] The specific embodiments shown and described are illustrative of this disclosure and its best mode, and are not intended to limit the scope of the embodiments in any other way. In fact, for the sake of brevity, the conventional manufacturing, connection, preparation, and other functional aspects of the system are not described in detail. Furthermore, the connecting lines shown in the different figures are intended to represent illustrative functional relationships and / or physical couplings between different elements. Many alternative or additional functional relationships or physical connections may exist in the actual system and / or may not exist in some embodiments.

[0068] It should be understood that the configurations and / or methods described herein are exemplary in nature, and these specific embodiments or instances should not be considered limiting, as numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Therefore, the various actions described may be performed in the described sequence, in other sequences, or in some cases omitted.

[0069] The subject matter of this disclosure includes all novel and non-obvious combinations and sub-combinations of the various processes, systems and configurations, and other features, functions, actions and / or properties disclosed herein, as well as any and all equivalents thereof. [Simplified Explanation of the Diagram]

[0027] These and other features, features and advantages of the present disclosure will now be described with reference to the accompanying drawings, which are intended to illustrate and not limit certain embodiments of the present disclosure. Figure 1 is a schematic diagram of a semiconductor processing system having a reactor constructed according to the present disclosure, showing a halogen-containing gas source connected to the lower chamber of the reactor and a silicon-containing gas source connected to the upper chamber of the reactor; Figure 2 is a schematic diagram of the semiconductor processing system of Figure 1, showing a substrate provided to the reactor for depositing a silicon layer onto the upper surface of the substrate; Figure 3 is a schematic diagram of the semiconductor processing system of Figure 1, showing the substrate positioned in the upper chamber of the reactor using a substrate holder; Figure 4 is a schematic diagram of the semiconductor processing system of Figure 1, showing the halogen-containing gas source causing silicon-containing gas to flow through the upper chamber of the reactor while the silicon-containing gas source causes halogen-containing gas to flow through the lower chamber of the reactor; Figure 5 is a schematic diagram of a portion of the semiconductor processing system of Figure 1 including the reactor, showing a halogen-containing gas etching deposition film from at least one wall defining the lower chamber of the reactor, the lower surface of the substrate, and the periphery of the silicon layer being deposited on the upper surface of the substrate. Figure 6 is a schematic diagram of the semiconductor processing system of Figure 1, showing the unloading of the substrate from the reactor after the halogen-containing gas flows through the lower chamber of the reactor; Figure 7 is a schematic diagram of the semiconductor processing system of Figure 1 according to one example, showing the activation of the halogen-containing gas by a distal plasma unit before the halogen-containing gas flows through the lower chamber of the reactor; Figure 8 is a schematic diagram of the semiconductor processing system of Figure 1 according to another example, showing the halogen-containing gas flowing through the upper chamber of the reactor as a carrier gas for silicon-containing gas while the halogen-containing gas flows through the lower chamber of the reactor; Figure 9 is a schematic diagram of the semiconductor processing system of Figure 1 according to another example, showing a controller operatively connected to the silicon-containing gas source and the halogen-containing gas source for causing the halogen-containing gas to flow through the lower chamber of the reactor while the silicon-containing gas flows through the upper chamber of the reactor; and Figure 10 is a block diagram of a method for forming a silicon layer on a substrate using a semiconductor processing system, showing the operation of the method according to illustrative and non-limiting examples.

[0028] It is worth noting that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the relative dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve the understanding of the illustrated embodiments of this disclosure.

Claims

1. A method for forming a layer on a substrate, the method comprising: A substrate is provided in a reactor of a semiconductor processing system, the reactor having a separator that separates an upper chamber from a lower chamber and a substrate holder in the reactor, wherein the substrate has an upper surface and an opposite lower surface; the substrate is positioned in the upper chamber of the reactor using the substrate holder; a silicon-containing gas is flowed through the upper chamber of the reactor to deposit a layer on the upper surface of the substrate; and while the silicon-containing gas is flowed through the upper chamber of the reactor, a halogen-containing gas is flowed through the lower chamber to etch a deposited film on at least one wall defining the lower chamber of the reactor.

2. The method of claim 1 further includes etching the upper surface of the substrate with the halogen-containing gas to control the thickness of the layer at a periphery of the upper surface of the substrate.

3. The method of claim 1 further includes etching the lower surface of the substrate with the halogen-containing gas to limit the deposition of silicon on the lower surface of the substrate.

4. The method of claim 1 further includes allowing the halogen-containing gas to flow through a gap defined between the substrate and the separator into the upper chamber, the separator separating the upper chamber from the lower chamber of the reactor.

5. The method of claim 1 further includes tuning the edge thickness of the layer to a target profile by adjusting the mass flow rate of the halogen-containing gas.

6. The method of claim 1 further includes flowing a purge gas through the lower chamber of the reactor, wherein the halogen-containing gas and the purge gas are mixed together.

7. The method of claim 1 further includes activating the halogen-containing gas before allowing the halogen-containing gas to flow through the lower chamber of the reactor.

8. The method of claim 1 further includes, while allowing the halogen-containing gas to flow through the lower chamber of the reactor, allowing a dopant-containing gas to flow through the upper chamber of the reactor.

9. The method of claim 1 further includes selecting the halogen-containing gas to include at least one of the following: hydrogen chloride (HCl); chlorine (Cl2); or fluorine (F2).

10. The method of claim 1 further includes selecting the silicon-containing gas to include at least one of the following: silane (SiH4); disilane (Si2H6); trisilane (Si3H8); or tetrasilane (Si4H10).

11. The method of request item 1 further includes: Choose a carrier gas that includes at least one of the following: nitrogen (N2); hydrogen (H2); helium (He); Argon (Ar); or a rare gas; and the upper chamber through which the carrier gas and the silicon-containing gas flow through the reactor.

12. The method of request item 1 further includes: The selection includes one of the following dopant gases: diborane (B2H6); phosphine (PH3); or arsine (AsH3); and the dopant gas and the silicon-containing gas are allowed to flow through the upper chamber of the reactor.

13. The method of claim 1 further includes maintaining the temperature inside the reactor between about 300°C and about 750°C or between about 550°C and about 1220°C while allowing the halogenated gas to flow through the lower chamber of the reactor.

14. The method of claim 1 further includes maintaining the reactor pressure between about 10 Torr and about 800 Torr while allowing the halogenated gas to flow through the lower chamber of the reactor.

15. The method of claim 1, wherein the flow of the halogen-containing gas through the lower chamber of the reactor has a duration between about 2 minutes and about 25 minutes, or wherein the duration of the flow of the halogen-containing gas is substantially equal to the duration of the flow of the silicon-containing gas through the upper chamber of the reactor.

16. A semiconductor processing system, comprising: A reactor having an upper chamber and a lower chamber, the reactor being configured to support a substrate therein, the substrate having an upper surface and an opposing lower surface; a silicon-containing gas source connected to the upper chamber of the reactor and configured to provide a silicon-containing gas to the reactor; a halogen-containing gas source connected to the lower chamber of the reactor and configured to provide a halogen-containing gas to the reactor; and a controller operatively connected to the semiconductor processing system and responsive to instructions recorded in a non-transitory machine-readable memory to: position a substrate in the upper chamber of the reactor; allow the silicon-containing gas to flow through the upper chamber of the reactor to deposit a layer on the upper surface of the substrate; and allow the halogen-containing gas to flow through the lower chamber while simultaneously allowing the silicon-containing gas to flow through the upper chamber of the reactor to etch a deposited film on at least one wall defining the lower chamber of the reactor.

17. The semiconductor processing system of claim 16, wherein the instructions further cause the controller to etch the upper surface of the substrate with the halogen-containing gas to control the thickness of a layer deposited on the periphery of the upper surface of the substrate.

18. The semiconductor processing system of claim 16, wherein the halogen gas source is connected to the upper chamber and the lower chamber of the reactor.

19. The semiconductor processing system of claim 16 further includes a purge gas source connected to the lower chamber of the reactor to allow a purge gas to flow through the lower chamber of the reactor, the lower chamber of the reactor having the halogen-containing gas passing through the lower chamber of the reactor.

20. The semiconductor processing system of claim 16 further includes: A first mass flow controller (MFC) connects the halogen gas source to the upper chamber of the reactor to allow the halogen-containing gas to flow through the upper chamber of the reactor as a carrier gas for the flow of the silicon-containing gas; and a second mass flow controller connects the halogen gas source to the lower chamber of the reactor to allow the halogen-containing gas to flow through the lower chamber of the reactor to etch at least one internal surface and / or structure within the reactor.

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