Device, apparatus and method for improved power distribution network (PDN) performance

Abstract

An element includes: a first substrate including a first plurality of solder interconnects; a second substrate including a second plurality of solder interconnects, wherein the second plurality of solder interconnects are coupled to the first plurality of solder interconnects via a plurality of solder interconnects; a passive element located between the first substrate and the second substrate; and an integrated element coupled to the first substrate.

Description

Technical Field

[0001] This patent application claims priority and benefit to non-provisional application No. 17 / 225,949, filed April 8, 2021, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as fully set forth herein in their entirety and for all applicable purposes.

[0002] Various features relate to packaging and substrate. Prior Technology

[0003] Figure 1 illustrates a package 100 including a substrate 102 and an integrated element 105. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a plurality of solder interconnects 124. The plurality of solder interconnects 124 are coupled to a first surface of the substrate 102 and the integrated element 105. The package 100 is coupled to a board 106 via the plurality of solder interconnects 124. There is a continued need to improve the overall performance of the package 100. Summary of the Invention

[0004] Various features relate to packaging and substrate.

[0005] One example provides an element comprising: a first substrate including a first plurality of solder interconnects; a second substrate including a second plurality of solder interconnects, wherein the second plurality of solder interconnects are coupled to the first plurality of solder interconnects via a plurality of solder interconnects; a passive element located between the first substrate and the second substrate; and an integrated element coupled to the first substrate.

[0006] Another example provides an apparatus comprising: a first substrate including components for a first solder joint interconnect; a second substrate including components for a second solder joint interconnect, wherein the components for the second solder joint interconnect are coupled to the components for the first solder joint interconnect via a plurality of solder interconnects; a passive element located between the first substrate and the second substrate; and an integration element coupled to the first substrate.

[0007] Another example provides a method for fabricating components. The method provides a first substrate comprising a first complex number of welded columns interconnected. The method couples the passive element to the first substrate. The method couples a second substrate to a first substrate comprising a second complex number of welding posts interconnected. Coupling a second substrate to a first substrate includes: Coupling a second complex of solder string interconnects to a first complex of solder post interconnects via a complex number of solder interconnects. The second substrate is coupled to the first substrate such that the passive element is located between the first substrate and the second substrate. The method couples the integral element to the first substrate. Brief explanation of the schema

[0008] In understanding the detailed description elaborated below in conjunction with the drawings, the various features, essences and advantages will become apparent, in the drawings, similar component symbols are always marked accordingly.

[0009] Figure 1 illustrates a cross-sectional view of the package coupled to the plate.

[0010] 2 illustrates a cross-sectional view of a package including two substrates and a passive element located between those two substrates.

[0011] 3 illustrates a close-up cross-sectional view of a package including two substrates and a passive element located between those two substrates.

[0012] 4 illustrates a close-up cross-sectional view of a package including two substrates and a passive element located between those two substrates.

[0013] 5 illustrates a close-up cross-sectional view of a package including two substrates and a passive element located between those two substrates.

[0014] 6A to 6D illustrate an exemplary process for fabricating a package including two substrates and a passive element located between those two substrates.

[0015] 7 illustrates an exemplary flowchart of a method for fabricating a package comprising two substrates and a passive element located between those two substrates.

[0016] 8A to 8C illustrate exemplary processes used to fabricate substrates.

[0017] 9 illustrates an exemplary flowchart of a method for fabricating a substrate.

[0018] Figure 10 illustrates a cross-sectional view of a package including three substrates and a passive component located between two substrates.

[0019] Figure 11 illustrates a cross-sectional view of a package comprising three substrates.

[0020] Figure 12 illustrates a cross-sectional view of a package that includes two substrates.

[0021] Figure 13 illustrates various electronic devices that can integrate the chips, electronic circuits, integrated components, integrated passive components (IPDs), passive components, packages, and / or component packages described herein. Implementation

[0022] In the following description, specific details are provided to offer a thorough understanding of the various forms of this application. However, those skilled in the art will understand that these forms can be practiced without such specific details. For example, circuits may be illustrated using block diagrams to avoid obscuring the forms in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be illustrated in detail to avoid obscuring the forms of this application.

[0023] This application describes a component comprising: a first substrate including a first plurality of bond interconnects; a second substrate including a second plurality of bond interconnects; a passive component located between the first and second substrates; and an integrated component coupled to the first substrate. The second plurality of bond interconnects are coupled to the first plurality of bond interconnects via a plurality of solder interconnects. As part of a power distribution network (PDN), the integrated component is configured to be electrically coupled to the passive component. The component may further include an encapsulation layer located between the first and second substrates, wherein the encapsulation layer at least partially encapsulates the passive component, the first plurality of bond interconnects, the second plurality of bond interconnects, and the plurality of solder interconnects. Placing the passive component between the first and second substrates can help improve the PDN performance of the package. An exemplary package that includes passive components between substrates.

[0024] Figure 2 illustrates a cross-sectional view of a package 200 including passive components between two substrates. Package 200 can be implemented as part of a component. Package 200 includes: an integrated component 201, substrate 202, substrate 204, integrated component 203, integrated component 205, encapsulation layer 208, passive components 211, 213, and 215, a plurality of solder interconnects 226, and encapsulation layer 260. Package 200 is coupled to board 209 (e.g., a printed circuit board) via the plurality of solder interconnects 226. As will be further described below, at least one of the passive components (e.g., 213, 215) is located between substrate 202 and substrate 204, which can help improve the power distribution network (PDN) performance of package 200.

[0025] Substrate 202 may be a first substrate. Substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. Substrate 202 may also include a plurality of bond interconnects 261. The plurality of bond interconnects 261 may include components for bonding the bond interconnects (e.g., components for the first bond interconnect). Different substrates may have different numbers of metal layers. In some implementations, substrate 202 may include 7 or fewer metal layers. Different implementations may use different substrates for substrate 202. Substrate 202 may include embedded trace substrates (ETS), laminated substrates, and / or coreless substrates. Substrate 202 may be manufactured using different processes, including ETS process, semi-additive process (SAP), and modified semi-additive process (mSAP).

[0026] Substrate 204 may be a second substrate. Substrate 204 includes at least one dielectric layer 240 and a plurality of interconnects 242. Substrate 204 may also include a plurality of bond interconnects 263. The plurality of bond interconnects 263 may include components for bonding the bond interconnects (e.g., components for second bond interconnects). Different substrates may have different numbers of metal layers. In some implementations, substrate 204 may include four or fewer metal layers. Different implementations may use different substrates for substrate 204. Substrate 204 may include embedded trace substrates (ETS), laminated substrates, and / or coreless substrates. Substrate 204 may be manufactured using different processes, including ETS process, semi-additive process (SAP), and modified semi-additive process (mSAP).

[0027] Using two substrates with 11 or fewer combined metal layers can help improve overall package yield during substrate and / or package manufacturing processes. Furthermore, using two substrates instead of one allows at least one of the passive components (e.g., 213, 215) to be located closer to the integrated component. For example, if a single substrate with a similar number of combined metal layers as substrates 202 and 204 were used instead of substrates 202 and 204, passive components 213 and 215 might have to be located on a surface similar to that of passive component 211, which would place passive components 213 and 215 further away from the integrated component 201. Placing passive components 213 and / or 215 further away from the integrated component 201 could result in reduced PDN performance of package 200.

[0028] Integrated element 203, integrated element 205, and passive element 211 are coupled to a first surface (e.g., top surface) of substrate 202. For example, integrated element 203 is coupled to substrate 202 via a plurality of solder interconnects 234. Similarly, integrated element 205 is coupled to substrate 202 via a plurality of solder interconnects 254. Passive element 211 is coupled to substrate 202 via a plurality of solder interconnects 231. Encapsulation layer 208 is formed on and located over substrate 202 (e.g., the first surface of substrate 202), integrated element 203, integrated element 205, and / or passive element 211. Encapsulation layer 208 may include a molding compound, resin, and / or epoxy resin. Encapsulation layer 208 may be a component for encapsulation.

[0029] Passive components 213 and 215, and encapsulation layer 260 are located between substrate 202 and substrate 204. Substrate 202 and substrate 204 are each coupled to encapsulation layer 260. Encapsulation layer 260 may include molding parts, underfill, adhesive, non-conductive paste (NCP), and / or non-conductive film (NCF). Encapsulation layer 260 may be a component for encapsulation. Substrate 202 is coupled to substrate 204 via a plurality of solder interconnects 261, a plurality of solder interconnects 264, and a plurality of solder interconnects 263. Encapsulation layer 260 may encapsulate passive components 213, passive components 215, a plurality of solder interconnects 261, a plurality of solder interconnects 264, and a plurality of solder interconnects 263.

[0030] The integrated element 201 is coupled to a second surface (e.g., the bottom surface) of the substrate 204 via a plurality of solder interconnects 214. The integrated element 201 may be located to the side of the plurality of solder interconnects 226.

[0031] Package 200 includes a power distribution network (PDN). In some implementations, integrated element 201, passive element 213, passive element 215, passive element 211, integrated element 203, and / or integrated element 205 may be part of the PDN of package 200 and / or configured to be electrically coupled to the PDN. In one example, integrated element 201 and passive element 213 are configured to be electrically coupled to the PDN of package 200. In another example, integrated element 203 and passive element 213 are configured to be electrically coupled to the PDN of package 200. In the example where integrated element 201 and passive element 213 are part of the package's PDN, the fact that passive element 213 is close to integrated element 201 helps improve the PDN performance of package 200. If passive element 213 is located on the same plane as passive element 211, the PDN performance of package 200 will be less good due to the increased distance and / or separation between passive element 213 and integrated element 201. In some implementations, the vertical distance between passive element 213 and integrated element 201 can be four metal layers or fewer. Those skilled in the art can use any combination of integrated elements and passive elements as part of the package's PDN. It should be noted that passive elements 213 and / or 215 can be located at different locations within package 200. For example, passive elements 213 and / or 215 can be coupled to the top surface of substrate 202. It should also be noted that in some implementations, there may be no passive element between substrate 202 and substrate 204. It should be noted that package 200 can include two or more substrates. For example, package 200 can include substrate 202, substrate 204, and a third substrate. The third substrate can be similar to substrate 202 and / or substrate 204. Figure 10, further described below, illustrates an example of a package including more than two substrates.

[0032] Figures 3 through 5 illustrate various examples of how passive components can be placed and coupled between two substrates. The configurations illustrated in Figures 3 through 5 are applicable to the package 200 of Figure 2.

[0033] Figure 3 illustrates an example of a passive element 215 coupled to substrates 202 and 204. The top portion of the passive element 215 is coupled (e.g., mechanically coupled) to the bottom surface of substrate 202. An encapsulation layer 260 facilitates coupling the passive element 215 to substrate 202. In some implementations, an adhesive may be used to couple the passive element 215 to substrate 202. The bottom portion of the passive element 215 is coupled (e.g., mechanically, electrically coupled) to the top surface of substrate 204 via solder interconnects 366b. The passive element 215 may be coupled to interconnect 242b via solder interconnects 366b. In some implementations, current through the packaged PDN may pass through the passive element 215, solder interconnects 366b, interconnect 242b, interconnect 242a, pillar interconnect 263a, solder interconnect 264a, pillar interconnect 261a, and interconnect 222a. It should be noted that current through the packaged PDN may pass through other interconnects and / or in different directions.

[0034] Figure 4 illustrates another example of a passive element 215 coupled to substrates 202 and 204. The bottom portion of the passive element 215 is coupled (e.g., mechanically coupled) to the top surface of substrate 204. An encapsulation layer 260 facilitates coupling the passive element 215 to substrate 204. In some implementations, an adhesive may be used to couple the passive element 215 to substrate 204. The top portion of the passive element 215 is coupled (e.g., mechanically, electrically coupled) to the bottom surface of substrate 202 via solder interconnect 364b. The passive element 215 may be coupled to interconnect 222b via solder interconnect 364b. In some implementations, current through the packaged PDN may pass through interconnect 242a, pillar interconnect 263a, solder interconnect 264a, pillar interconnect 261a, interconnect 222a, interconnect 222b, solder interconnect 364b, and passive element 215. It should be noted that current through the packaged PDN may pass through other interconnects and / or in different directions.

[0035] Figure 5 illustrates another example of a passive component 215 coupled to substrates 202 and 204. The bottom portion of the passive component 215 is coupled (e.g., mechanically or electrically) to the bottom surface of substrate 204 via solder interconnect 366b. The passive component 215 may be coupled to interconnect 242b via solder interconnect 366b. The top portion of the passive component 215 is coupled (e.g., mechanically or electrically) to the bottom surface of substrate 202 via solder interconnect 364b. The passive component 215 may be coupled to interconnect 222b via solder interconnect 364b.

[0036] It should be noted that the passive element 213 can be coupled (e.g., electrically coupled, mechanically coupled) to substrates 202 and 204 in a similar manner and / or configuration as described in Figures 3 to 5. Different implementations may have different spacing (e.g., minimum spacing) between substrates 202 and 204. In some implementations, the minimum spacing between the bottom surface of substrate 202 and the top surface of substrate 204 may be approximately 120 micrometers. In some implementations, the encapsulation layer 260 may have a minimum thickness of 120 micrometers. In some implementations, the passive element located between substrates 202 and 204 may have a thickness of 100 micrometers or less. In some implementations, a plurality of bond interconnects 261 may have a thickness of 60 micrometers or less (e.g., approximately 50 micrometers). In some implementations, a plurality of bond interconnects 263 may have a thickness of 60 micrometers or less (e.g., approximately 50 micrometers).

[0037] Integrated components (e.g., 201, 203, 205) may include dies (e.g., semiconductor bare dies). Integrated components may include radio frequency (RF) components, passive components, filters, capacitors, inductors, antennas, transmitters, receivers, GaAs-based integrated components, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated components, silicon (Si)-based integrated components, silicon carbide (SiC)-based integrated components, processors, memory, power management integrated components, and / or combinations thereof. Integrated components (e.g., 201, 203, 205) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). Passive components (e.g., 211, 213, 215) may include surface mount devices (SMDs). Passive components may include individual passive components. Passive components may include integrated passive components (IPDs). Passive components may include capacitors or resistors.

[0038] The configuration and design of package 200 provide a package with improved PDN performance due to the fact that at least one passive component can be physically located close to at least some integrated components. Furthermore, using a substrate with a fewer number of metal layers helps increase substrate yield, which in turn helps reduce substrate cost. In some implementations, different substrate combinations can be used between the first and second substrates. For example, the first substrate may have a lower density interconnect, while the second substrate may have a higher density interconnect.

[0039] Various packages have been described; the processes used to manufacture these packages will now be described below. Exemplary process for manufacturing a package that includes passive components between substrates.

[0040] Figures 6A through 6D illustrate exemplary steps for providing or manufacturing a package that includes passive components between substrates. In some implementations, the steps of Figures 6A through 6D may be used to provide or manufacture the package 200 of Figure 2, or any package described herein.

[0041] It should be noted that the processes in Figures 6A to 6D can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of these processes can be substituted or replaced without departing from the spirit of this invention. Different implementations can manufacture the package differently.

[0042] As shown in Figure 6A, stage 1 illustrates the state after substrate 202 has been provided. Substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. Substrate 202 may include different numbers of metal layers. Substrate 202 may include a laminated substrate and / or a coreless substrate (e.g., ETS). Substrate 202 may be a first substrate.

[0043] Phase 2 illustrates the state after a plurality of solder pillar interconnects 261 have been formed on substrate 202. A plating process can be used to form the plurality of interconnects 261. The plurality of solder pillar interconnects 261 can be considered as part of substrate 202.

[0044] Phase 3 illustrates the state after passive components 213 and 215 are coupled to substrate 202. A pick-and-place process can be used to place the passive components onto substrate 202. In some implementations, an adhesive can be used to couple the passive components to substrate 202. In some implementations, a solder reflow process can be used to couple the passive components to substrate 202.

[0045] Stage 4 illustrates the state after a plurality of solder interconnects 264 have been formed on a plurality of solder pillar interconnects 261. A solder reflow process can be used to form a plurality of solder interconnects 264 on a plurality of solder pillar interconnects 261.

[0046] As shown in Figure 6B, stage 5 illustrates the state after substrate 204 has been provided. Substrate 204 includes at least one dielectric layer 240 and a plurality of interconnects 242. Substrate 204 may include different numbers of metal layers. Substrate 204 may include a laminated substrate and / or a coreless substrate (e.g., ETS). Substrate 204 may be a second substrate.

[0047] Stage 6 illustrates the state after a plurality of solder pillar interconnects 263 have been formed on substrate 204. A plating process can be used to form the plurality of interconnects 263. The plurality of solder pillar interconnects 263 can be considered as part of substrate 204.

[0048] Phase 7 illustrates the state after substrate 202 is coupled to substrate 204 such that passive components 213 and 215 are located between substrates 202 and 204. Substrate 202 is coupled to substrate 204 via a plurality of solder interconnects 261, a plurality of solder interconnects 264, and a plurality of solder interconnects 263. An encapsulation layer 260 may be formed between substrates 202 and 204 during the coupling process or after the coupling. Substrate 202 and substrate 204 may be coupled using a large-scale reflow process, a flip-chip attachment process, and / or a thermo-pressed flip-chip (TCFC) process. Encapsulation layer 260 may include a molding compound, underfill, adhesive, non-conductive paste (NCP), and / or non-conductive film (NCF). In some implementations, compression and transfer molding processes, sheet molding processes, or liquid molding processes can be used to form the encapsulation layer 260.

[0049] As shown in Figure 6C, stage 8 illustrates the state after the integrated component 201 is coupled to the second surface (e.g., the bottom surface) of the substrate 202. The integrated component 201 can be coupled to the substrate 204 via a plurality of solder interconnects 214. A solder reflow process can be used to couple the integrated component 201 to the substrate 204.

[0050] Phase 9 illustrates the state after integrated component 203, integrated component 205, and passive component 211 are coupled to a first surface (e.g., the top surface) of substrate 202. Integrated component 203 may be coupled to substrate 202 via a plurality of solder interconnects 234. Integrated component 205 may be coupled to substrate 202 via a plurality of solder interconnects 254. Passive component 211 may be coupled to substrate 202 via a plurality of solder interconnects 231. One or more solder reflow processes may be used to couple the plurality of solder interconnects (e.g., 231, 234, 254) to substrate 202.

[0051] As shown in Figure 6D, stage 10 illustrates the state after an encapsulation layer 208 is formed on substrate 202, integrated component 203, integrated component 205, and / or passive component 211. The encapsulation layer 208 encapsulates integrated component 203, integrated component 205, and / or passive component 211. The encapsulation layer 208 can be formed using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0052] Phase 11 illustrates a state where a plurality of solder interconnects 226 are coupled to the bottom surface of substrate 204. A solder reflow process can be used to couple the plurality of solder interconnects 226 to substrate 204. The plurality of solder interconnects 226 may be coupled to pad interconnects in a plurality of interconnects 242. The plurality of solder interconnects 226 may be located on the side of integrated component 201. Phase 11 may also illustrate a package 200 including at least one passive component located between two substrates. An exemplary flowchart of a method for manufacturing a package that includes passive components between substrates.

[0053] In some implementations, manufacturing a package includes several procedures. Figure 7 illustrates an exemplary flowchart of a method 700 for providing or manufacturing a package comprising at least one passive element located between two substrates. In some implementations, the method 700 of Figure 7 can be used to provide or manufacture the package 200 of Figure 2. However, the method 700 of Figure 7 can be used to manufacture any package in this case.

[0054] It should be noted that the method in Figure 7 can combine one or more procedures to simplify and / or clarify the method used to provide or manufacture the package. In some implementations, the order of the procedures can be changed or modified.

[0055] The method (at 705) provides a first substrate (e.g., substrate 202), forms bond interconnects on the first substrate, and couples at least one passive element (e.g., 213, 215) to the first substrate. Substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 222. Substrate 202 may include different numbers of metal layers. Substrate 202 may include a laminated substrate and / or a coreless substrate (e.g., ETS). Stage 1 of FIG6A illustrates and describes an example of providing a substrate. Forming a plurality of bond interconnects on the substrate may include using a plating process. Stage 2 of FIG6A illustrates and describes an example of forming bond interconnects. (A) Passive elements may be coupled to the surface of the substrate. Stage 3 of FIG6A illustrates and describes an example of coupling at least one passive element to the substrate. In some implementations, a plurality of solder interconnects (e.g., 264) may be formed on the plurality of bond interconnects. Stage 4 of FIG6A illustrates and describes an example of forming solder interconnects.

[0056] The method (at 710) provides a second substrate (e.g., substrate 204) and forms bond interconnects on the second substrate. Substrate 204 includes at least one dielectric layer 240 and a plurality of interconnects 242. Substrate 204 may include different numbers of metal layers. Substrate 204 may include a laminated substrate and / or a coreless substrate (e.g., ETS). Stage 5 of Figure 6B illustrates and describes an example of providing a substrate. Forming a plurality of bond interconnects on the substrate may include using a plating process. Stage 6 of Figure 6B illustrates and describes an example of forming bond interconnects.

[0057] The method (at 715) couples a second substrate (e.g., substrate 204) to a first substrate (e.g., 202). The second substrate may be coupled to the first substrate via an encapsulation layer (e.g., 260). The encapsulation layer 260 may be formed between the first and second substrates during the coupling process or after the coupling of the first and second substrates. The encapsulation layer 260 may include a molding compound, underfill, adhesive, non-conductive paste (NCP), and / or non-conductive film (NCF). In some implementations, the encapsulation layer 260 may be formed using compression and transfer molding processes, sheet molding processes, or liquid molding processes. The second substrate is coupled to the first substrate such that at least one passive element (e.g., 213, 215) is located between the first and second substrates. The first substrate is coupled to the second substrate via a plurality of solder interconnects (e.g., 261), a plurality of solder interconnects (e.g., 264), and a plurality of solder interconnects (e.g., 263). Phase 7 of Figure 6B illustrates and describes an example of coupling the second substrate to the first substrate.

[0058] This method (at 720) couples integrated components and / or passive components to a first substrate and a second substrate. For example, integrated component 201 may be coupled to the second substrate (e.g., substrate 204), and integrated component 203 and passive component 211 may be coupled to the first substrate (e.g., substrate 202). Coupling integrated components and / or passive components may include using a solder reflow process. Stages 8 and 9 of FIG6C illustrate and describe examples of coupling integrated components and passive components to substrates.

[0059] The method (at 725) forms an encapsulation layer (e.g., 208) on a first substrate. Encapsulation layer 208 may be formed on substrate 202, integrated device 203, integrated device 205, and / or passive device 211. Encapsulation layer 208 may encapsulate integrated device 203, integrated device 205, and / or passive device 211. Compression and transfer molding processes, sheet molding processes, or liquid molding processes can be used to form encapsulation layer 208. Stage 10 of Figure 6D illustrates and describes an example of forming an encapsulation layer.

[0060] This method (at 730) couples solder interconnects (e.g., 226) to a second substrate (e.g., substrate 204). A plurality of solder interconnects 226 may be coupled to the bottom surface of substrate 204. A solder reflow process can be used to couple the plurality of solder interconnects 226 to substrate 204. The plurality of solder interconnects 226 may be coupled to pad interconnects in a plurality of interconnects 242. Stage 11 of Figure 6D illustrates and describes an example of coupling solder interconnects to a substrate. Exemplary process for manufacturing a substrate

[0061] In some implementations, manufacturing the substrate includes several processes. Figures 8A to 8C illustrate exemplary processes for providing or manufacturing the substrate. In some implementations, the processes of Figures 8A to 8C can be used to provide or manufacture the substrate 202 and / or substrate 204 of Figure 2. However, the processes of Figures 8A to 8C can be used to manufacture any substrate described in this case.

[0062] It should be noted that the processes in Figures 8A to 8C can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the scope of this application.

[0063] As illustrated in Figure 8A, stage 1 depicts the state after a carrier 800 is provided and a metal layer is formed on the carrier 800. This metal layer can be patterned to form interconnects 802. The metal layer and interconnects can be formed using plating and etching processes. In some implementations, the carrier 800 may be provided with a metal layer that is patterned to form the interconnects 802.

[0064] Phase 2 illustrates the state after a dielectric layer 820 has been formed over the carrier 800 and interconnect 802. The dielectric layer 820 may include polyimide. However, different implementations may use different materials for the dielectric layer.

[0065] Stage 3 illustrates the state after the plurality of cavities 810 are formed in the dielectric layer 820. The plurality of cavities 810 can be formed using an etching process (e.g., a photolithography process) or a laser process.

[0066] Stage 4 illustrates the state after interconnects 812 are formed in and over the dielectric layer 820 (including in and over the plurality of cavities 810). For example, vias, pads, and / or traces may be formed. These interconnects may be formed using a plating process.

[0067] Stage 5 illustrates the state after another dielectric layer 822 is formed on top of dielectric layer 820. Dielectric layer 822 can be made of the same material as dielectric layer 820. However, different implementations may use different materials for the dielectric layers.

[0068] As illustrated in Figure 8B, stage 6 shows the state after a plurality of cavities 830 have been formed in the dielectric layer 822. The cavities 830 can be formed using an etching process or a laser process.

[0069] Stage 7 illustrates the state after interconnects 814 are formed in and over dielectric layer 822 (including in and over the plurality of cavities 830). For example, vias, pads, and / or traces may be formed. These interconnects may be formed using a plating process.

[0070] Stage 8 illustrates the state after another dielectric layer 824 is formed on top of dielectric layer 822. Dielectric layer 824 can be made of the same material as dielectric layer 820. However, different implementations may use different materials for the dielectric layers.

[0071] Stage 9 illustrates the state after multiple cavities 840 have been formed in the dielectric layer 824. The cavities 840 can be formed using an etching process or a laser process.

[0072] As shown in Figure 8C, stage 10 illustrates the state after interconnects 816 are formed in and over the dielectric layer 824 (including in and over the plurality of cavities 840). For example, vias, pads, and / or traces may be formed. These interconnects may be formed using a plating process.

[0073] Some or all of interconnects 802, 812, 814 and / or 816 may define a plurality of interconnects 852 of substrate 801. Dielectric layers 820, 822, 824 may be represented by at least one dielectric layer 850.

[0074] Phase 11 illustrates the state after the carrier 800 is decoupled from the dielectric layer 850 (e.g., removed, ground away) to leave a substrate 801 comprising at least one dielectric layer 850 and a plurality of interconnects 852. The substrate 801 may represent substrate 202 and / or substrate 204.

[0075] Phase 12 illustrates the state after the formation of a first solder mask 860 and a second solder mask 862 on the substrate 801. The first solder mask 860 and the second solder mask 862 can be formed using a deposition process. In some implementations, a solder mask layer may not be formed or may be formed over at least one dielectric layer 850.

[0076] Different implementations may use different processes to form the metal layers. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form the metal layers. For example, sputtering, spraying, and / or plating processes may be used to form the metal layers. Exemplary flowchart of a method for manufacturing a substrate

[0077] In some implementations, manufacturing the substrate includes several procedures. Figure 9 illustrates an exemplary flowchart of a method 900 for providing or manufacturing a substrate. In some implementations, the method 900 of Figure 9 can be used to provide or manufacture the substrates(s) of Figure 2. For example, the method of Figure 9 can be used to manufacture substrate 202 and / or substrate 204.

[0078] It should be noted that the method in Figure 9 can combine one or more procedures to simplify and / or clarify the method for providing or manufacturing the substrate. In some implementations, the order of the procedures can be changed or modified.

[0079] The method (at 905) provides a carrier 800. Different implementations may use different materials for the carrier. The carrier may include a substrate, glass, quartz, and / or a carrier strip. Figure 8A illustrates and describes an example of the carrier provided in stage 1.

[0080] This method (at 910) forms a metal layer on a carrier 800. This metal layer can be patterned to form interconnects. A plating process can be used to form the metal layer and interconnects. In some implementations, the carrier may include a metal layer. The metal layer on the carrier can be patterned to form interconnects (e.g., 802). Stage 1 of Figure 8A illustrates and describes an example of forming a metal layer and interconnects on a carrier.

[0081] The method (at 915) forms a dielectric layer 820 over a carrier 800 and an interconnect 802. The dielectric layer 820 may comprise polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 810) within the dielectric layer 820. These cavities may be formed using an etching process (e.g., photolithography) or a laser process. Stages 2 to 3 of Figure 8A illustrate and depict examples of forming a dielectric layer and forming cavities within it.

[0082] This method (at 920) forms interconnects in and over the dielectric layer. For example, interconnect 812 may be formed in and over the dielectric layer 820. Such interconnects may be formed using a plating process. Forming interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Forming interconnects may also include forming interconnects in cavities within the dielectric layer. Stage 4 of Figure 8A illustrates and describes an example of forming interconnects in and over the dielectric layer.

[0083] The method (at 925) forms a dielectric layer 822 over a dielectric layer 820 and the interconnects thereon. The dielectric layer 822 may comprise polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 830) within the dielectric layer 822. These cavities may be formed using an etching process or a laser process. Figures 8A to 8B, stages 5 and 6, illustrate and describe examples of forming a dielectric layer and forming cavities within it.

[0084] This method (at 930) forms interconnects in and / or on the dielectric layer. For example, interconnect 814 can be formed. Such interconnects can be formed using a plating process. Forming interconnects may include providing a patterned metal layer on and in the dielectric layer. Forming interconnects may also include forming interconnects in cavities of the dielectric layer. Stage 7 of Figure 8B illustrates and describes an example of forming interconnects in and on the dielectric layer.

[0085] This method can form additional dielectric layers and additional interconnects, as described at 925 and 930. Figures 8B to 8C, stages 8 to 10, illustrate and depict examples of forming additional dielectric layers and forming interconnects in and on the dielectric layers.

[0086] Once all dielectric layers and additional interconnects are formed, the method can decouple (e.g., remove, grind away) the carrier (e.g., 800) from dielectric layer 820, leaving the substrate. In some implementations, the method can form a solder mask layer (e.g., 860, 862) on the substrate.

[0087] Different implementations may use different processes to form the metal layers. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form the metal layers. For example, sputtering, spraying, and / or plating processes may be used to form the metal layers. Exemplary package including passive components

[0088] As mentioned above, a package may include more than three substrates. Figure 10 illustrates a cross-sectional view of a package 1000 including three substrates and a passive component located between two substrates. Package 1000 may be implemented as part of a component. Package 1000 may be similar to package 200. Package 1000 includes: integrated component 201, substrate 202, substrate 204, substrate 1002, integrated component 203, integrated component 205, encapsulation layer 208, passive component 211, passive component 213, passive component 215, a plurality of solder interconnects 226, encapsulation layer 260, and encapsulation layer 1060. Package 1000 is coupled to board 209 (e.g., printed circuit board) via the plurality of solder interconnects 226. As will be further described below, for similar reasons as described above with respect to package 200, at least one passive element (e.g., 213, 215) is located between substrate 1002 and substrate 204, which can help improve the power distribution network (PDN) performance of package 1000.

[0089] Substrate 1002 may be a third substrate. Substrate 1002 includes at least one dielectric layer 1020 and a plurality of interconnects 1022. Substrate 1002 may also include a plurality of bond interconnects 1061 and a plurality of bond interconnects 1063. The plurality of bond interconnects 1061 and / or the plurality of bond interconnects 1063 may include components for bonding the bond interconnects (e.g., components for the first bond interconnects). Different substrates may have different numbers of metal layers. Different implementations may use different substrates for substrate 1002. Substrate 1002 may include embedded trace substrate (ETS), laminated substrate, and / or coreless substrate. Substrate 1002 may be manufactured using different processes, including ETS process, semi-additive process (SAP), and modified semi-additive process (mSAP).

[0090] Substrate 202 is coupled to substrate 1002. For example, substrate 202 is coupled to substrate 1002 via a plurality of solder interconnects 261, a plurality of solder interconnects 1064, and a plurality of solder interconnects 1063. The plurality of solder interconnects 1063 or the plurality of solder interconnects 261 may be optional. Thus, for example, substrate 202 may be coupled to substrate 1002 via a plurality of solder interconnects 261 and a plurality of solder interconnects 1064. The plurality of solder interconnects 1064 may be coupled to interconnects (e.g., pads) in a plurality of interconnects 1022 from substrate 1002. Encapsulation layer 1060 may be located between substrate 202 and substrate 1002. Encapsulation layer 1060 may be similar to or different from encapsulation layer 260. Encapsulation layer 1060 may be a component for encapsulation.

[0091] Substrate 1002 is coupled to substrate 204. For example, substrate 1002 is coupled to substrate 204 via a plurality of solder interconnects 1061, a plurality of solder interconnects 264, and a plurality of solder interconnects 263. Encapsulation layer 260 may be located between substrate 1002 and substrate 204. It should be noted that any of substrate 202, substrate 204, and substrate 1002 may be a first substrate, a second substrate, or a third substrate.

[0092] Passive elements 213 and 215 may be coupled to substrates 1002 and 204 in a manner similar to that described in Figures 2 through 5. Passive elements 213 and 215 may be part of the PDN of package 1000. In some implementations, one or more passive elements may be located between substrate 202 and substrate 1002. One or more passive elements may be part of the PDN of package 1000. Note that passive elements 213 and / or 215 may be located at different locations within package 1000. For example, passive elements 213 and / or 215 may be coupled to the top surface of substrate 202. It should also be noted that in some implementations, passive elements may not be present between (1) substrate 1002 and substrate 204 and (2) substrate 202 and substrate 1002.

[0093] Figure 11 illustrates a cross-sectional view of package 1100 comprising three substrates. Package 1100 is similar to package 1000 of Figure 10 and thus includes the same and / or similar components as package 1000. Package 1100 illustrates a configuration in which there are no passive components between (1) substrate 1002 and substrate 204 and (2) substrate 202 and substrate 1002. Passive components 213 and 215 are coupled to the top surface of substrate 202. Passive components 213 and 215 may be closer to integrated component 203 and / or integrated component 205. This may be beneficial to the overall performance of package 1100 when integrated component 203, integrated component 205, passive components 213 and / or 215 are part of the PDN of package 1100.

[0094] Figure 12 illustrates a cross-sectional view of package 1200 comprising two substrates. Package 1200 is similar to package 200 of Figure 2 and thus includes the same and / or similar components as package 200. Package 1200 is illustrated in a configuration in which no passive components are present between substrates 202 and 204. Passive components 213 and 215 are coupled to the top surface of substrate 202. Passive components 213 and 215 may be closer to integrated component 203 and / or integrated component 205. This may be beneficial to the overall performance of package 1200 when integrated component 203, integrated component 205, and passive components 213 and / or 215 are part of the PDN of package 1200.

[0095] It should be noted that for each of packages 200, 1000, 1100, and / or 1200, the total number of combined metal layers on all substrates can be substantially the same. For example, each of packages 200, 1000, 1100, and / or 1200 may have a total of approximately 10 or 11 combined metal layers. However, different packages may have different numbers of metal layers. Exemplary electronic devices

[0096] Figure 13 illustrates various electronic devices that can integrate any of the aforementioned components, integrated components, integrated circuit (IC) packages, integrated circuit (IC) components, semiconductor components, integrated circuits, dies, intermediaries, packages, stacked packages (PoP), system-in-package (SiP), or systems-on-a-chip (SoC). For example, mobile phone device 1302, laptop device 1304, fixed-location terminal device 1306, wearable device 1308, or motor vehicle 1310 may include the component 1300 as described herein. Component 1300 may be any of the components and / or integrated circuit (IC) packages described herein, for example. The devices 1302, 1304, 1306, and 1308, and vehicle 1310 illustrated in Figure 13 are merely exemplary. Other electronic devices may also feature element 1300, including but not limited to the group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablets, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0097] One or more of the elements, programs, features, and / or functions illustrated in Figures 2 to 5, 6A to 6D, 7, 8A to 8C, and / or 9 to 13 may be rearranged and / or combined into a single element, program, feature, or function, or implemented in several elements, programs, or functions. Additional elements, components, programs, and / or functions may also be added without departing from this invention. It should also be noted that Figures 2 to 5, 6A to 6D, 7, 8A to 8C, and / or 9 to 13 and their corresponding descriptions in this invention are not limited to dies and / or ICs. In some implementations, Figures 2 to 5, 6A to 6D, 7, 8A to 8C, and / or 9 to 13 and their corresponding descriptions may be used to manufacture, build, provide, and / or produce elements and / or integrate elements. In some implementations, the components may include dies, integrated components, integrated passive components (IPDs), die packages, integrated circuit (IC) components, component packages, integrated circuit (IC) packages, wafers, semiconductor components, stacked package (PoP) components, thermal components, and / or intermediaries.

[0098] Note that the accompanying drawings in this application may represent actual and / or conceptual representations of various components, elements, objects, devices, packages, integrated components, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all elements and / or components are illustrated for clarity. In some instances, the positioning, location, size, and / or shape of the various components and / or elements in the drawings may be exemplary. In some implementations, the various components and / or elements in the drawings may be optional.

[0099] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or manner described herein as "exemplary" need not be construed as superior to or better than other manners in this case. Similarly, the term "manner" does not require that all manners in this case include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, then objects A and C can still be considered coupled to each other—even if objects A and C are not in direct physical contact with each other. The term "electrical coupling" can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can be transmitted between the two objects. Electrically coupled objects may or may not have current transmitted between them. The use of the terms "first," "second," "third," and "fourth" (and / or anything higher than fourth) is arbitrary. Any element described can be a first element, a second element, a third element, or a fourth element. For example, an element referred to as a second element can be a first element, a second element, a third element, or a fourth element. The term "enclosure" means that an object can partially or completely enclose another object. The terms "top" and "bottom" are arbitrary. An element located at the top can be situated on top of an element located at the bottom. A top element can be considered a bottom element, and vice versa. As described in this case, a first element situated "above" a second element can mean that the first element is located above or below the second element, depending on how bottom or top is arbitrarily defined. In another instance, a first element can be situated above (e.g., above) a first surface of a second element, while a third element can be situated above (e.g., below) a second surface of a second element, where the second surface is opposite the first surface. Further note that the term "above," as used in this case in the context of one element being above another element, can be used to mean that an element is on and / or in another element (e.g., on the surface of an element or embedded in an element). Thus, for example, "first element on second element" can mean: (1) the first element is on the second element but does not directly contact the second element; (2) the first element is on the second element (e.g., on the surface of the second element); and / or (3) the first element is in the second element (e.g., embedded in the second element). A first element located "in" the second element can be partially or completely located in the second element. As used in this case, the terms "about "value X" or "approximately value X" mean within ten percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0100] In some implementations, an interconnect is a component or assembly within a element or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some implementations, an interconnect may include traces, vias, pads, solder pillars, redistributed metal layers, and / or under-bump metallization (UBM) layers. An interconnect may include one or more metal compositions (e.g., a seed layer + metal layer). In some implementations, an interconnect is a conductive material that can be configured to provide an electrical path for signals (e.g., data signals, ground, or power). An interconnect may be part of a circuit. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. Different implementations may use similar or different processes to form interconnects. In some implementations, chemical vapor deposition (CVD) processes and / or physical vapor deposition (PVD) processes are used to form interconnects. For example, sputtering, spraying, and / or plating processes may be used to form interconnects.

[0101] It should also be noted that the various disclosures contained herein can be described as programs illustrated as flowcharts, schematic diagrams, block diagrams, or block diagrams. Although flowcharts can describe operations as a sequential procedure, many operations can be executed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The program terminates when its operations are completed.

[0102] The following provides an overview of the various aspects of this case:

[0103] Version 1: An element includes: a first substrate including a first plurality of solder interconnects; a second substrate including a second plurality of solder interconnects; a passive element located between the first substrate and the second substrate; and an integrated element coupled to the first substrate. The second plurality of solder interconnects are coupled to the first plurality of solder interconnects via a plurality of solder interconnects.

[0104] State 2: The element as in State 1, wherein: as part of a power distribution network (PDN), the integrated element is configured to be electrically coupled to the passive element.

[0105] State 3: The element of states 1 to 2 further includes: an encapsulation layer located between the first substrate and the second substrate, wherein the encapsulation layer at least partially encapsulates the passive element, the first plurality of solder interconnects, the second plurality of solder interconnects and the plurality of solder interconnects.

[0106] State 4: Components as in State 3, wherein: the encapsulation layer includes a molded part, a bottom filler, an adhesive, a non-conductive paste (NCP) and / or a non-conductive film (NCF).

[0107] State 5: Components as in states 1 to 4, wherein the first substrate and the second substrate are separated by a minimum pitch of approximately 120 micrometers.

[0108] State 6: The element as in states 1 to 5, further comprising: a second integrated element coupled to the second substrate.

[0109] State 7: The element is the same as in State 6, wherein the second integrated element is configured to be electrically coupled to the passive element.

[0110] State 8: An element of states 1 to 7, wherein the first substrate comprises 7 or fewer metal layers, and wherein the second substrate comprises 4 or fewer metal layers.

[0111] Type 9: Components of types 1 to 8, wherein a first plurality of bond interconnects comprises a height of about 60 micrometers or less, and wherein a second plurality of bond interconnects comprises a height of about 60 micrometers or less.

[0112] State 10: The element as in State 9, wherein the passive element comprises a height of about 100 micrometers or less.

[0113] Version 11: An apparatus includes: a first substrate including components for a first solder joint interconnect; a second substrate including components for a second solder joint interconnect; a passive element located between the first substrate and the second substrate; and an integrated element coupled to the first substrate. The components for the second solder joint interconnect are coupled to the components for the first solder joint interconnect via a plurality of solder interconnects.

[0114] State 12: The device as in State 11, wherein: as part of a power distribution network (PDN), the integrated element is configured to be electrically coupled to the passive element.

[0115] Version 13: The apparatus of versions 11 to 12 further includes: a component for encapsulation located between the first substrate and the second substrate, wherein the component for encapsulation at least partially encapsulates the passive element, the component for the first solder post interconnect, the component for the second solder post interconnect, and the plurality of solder interconnects.

[0116] Version 14: The apparatus of Version 13, wherein: the components for encapsulation include a molded part, a bottom filler, an adhesive, a non-conductive paste (NCP), and / or a non-conductive film (NCF).

[0117] State 15: The apparatus of states 11 to 14, wherein the first substrate and the second substrate are separated by a minimum pitch of about 120 micrometers.

[0118] State 16: The apparatus of states 11 to 15 further includes: a second integrated element coupled to a second substrate.

[0119] State 17: A device as in State 16, wherein: the second integrated element is configured to be electrically coupled to the passive element.

[0120] Version 18: An apparatus as described in versions 11 to 17, wherein the first substrate comprises seven or fewer metal layers, and wherein the second substrate comprises four or fewer metal layers.

[0121] Specimen 19: The apparatus of Specimens 11 to 18, wherein the component for the first weld post interconnect includes a height of about 60 micrometers or less, and wherein the component for the second weld post interconnect includes a height of about 60 micrometers or less.

[0122] State 20: A device as in State 19, wherein the passive element comprises a height of about 100 micrometers or less.

[0123] Type 21: Devices of types 11 to 20, wherein the device is selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptops, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0124] Sample 22: A method for manufacturing a component. The method provides a first substrate including a first plurality of solder interconnects. The method couples a passive component to the first substrate. The method couples a second substrate to the first substrate, the second substrate including a second plurality of solder interconnects. Coupling the second substrate to the first substrate includes: coupling the second plurality of solder interconnects to the first plurality of solder interconnects via a plurality of solder interconnects. The second substrate is coupled to the first substrate such that the passive component is located between the first substrate and the second substrate. The method integrates a component to the first substrate.

[0125] State 23: The method of State 22, wherein the integrated element, as part of the power distribution network (PDN), is configured to be electrically coupled to the passive element.

[0126] Version 24: The method of Versions 22 to 23 further includes the following steps: forming an encapsulation layer between a first substrate and a second substrate, wherein the encapsulation layer at least partially encapsulates the passive element, a first plurality of solder interconnects, a second plurality of solder interconnects and the plurality of solder interconnects.

[0127] Version 25: The method of Version 24, wherein the encapsulation layer includes a molded part, a bottom filler, an adhesive, a non-conductive paste (NCP), and / or a non-conductive film (NCF).

[0128] State 26: The method of states 22 to 25, wherein the first substrate and the second substrate are separated by a minimum pitch of about 120 micrometers.

[0129] State 27: The method of states 22 to 26 further includes the step of coupling a second integrated element to a second substrate.

[0130] State 28: The method of State 27, wherein the second integrated element is configured to be electrically coupled to the passive element.

[0131] Version 29: The method of versions 22 to 28, wherein the first substrate comprises 7 or fewer metal layers, and wherein the second substrate comprises 4 or fewer metal layers.

[0132] State 30: The method of State 29, wherein the first plurality of bond interconnects includes a height of about 60 micrometers or less, wherein the second plurality of bond interconnects includes a height of about 60 micrometers or less, and wherein the passive element includes a height of about 100 micrometers or less.

[0133] Version 31: The method of versions 22 to 30 further includes the step of coupling a third substrate to a second substrate, wherein the third substrate includes a third plurality of interconnected bonding pillars.

[0134] State 32: The element of states 1 to 10 further includes: a third substrate coupled to the second substrate, wherein the third substrate includes a third plurality of interconnected bonding pillars.

[0135] Version 33: The apparatus of versions 11 to 21 further includes: a third substrate coupled to the second substrate, wherein the third substrate includes a third plurality of interconnected bonding pillars.

[0136] Version 34: An element includes: a first substrate including a first plurality of solder interconnects; a second substrate including a second plurality of solder interconnects; a passive element coupled to the second substrate; and an integrated element coupled to the first substrate. The second plurality of solder interconnects are coupled to the first plurality of solder interconnects via a plurality of solder interconnects.

[0137] State 35: The element of State 34, wherein: as part of a power distribution network (PDN), the integrated element is configured to be electrically coupled to the passive element.

[0138] Type 36: The element of types 34 to 35 further includes: an encapsulation layer located between the first substrate and the second substrate, wherein the encapsulation layer at least partially encapsulates the first plurality of solder interconnects, the second plurality of solder interconnects and the plurality of solder interconnects.

[0139] State 37: Components as in State 36, wherein: the encapsulation layer includes a molded part, a bottom filler, an adhesive, a non-conductive paste (NCP), and / or a non-conductive film (NCF).

[0140] State 38: Components as in states 34 to 37, wherein the first substrate and the second substrate are separated by a minimum pitch of approximately 120 micrometers.

[0141] State 39: The element of states 34 to 38 further includes: a second integrated element coupled to the second substrate.

[0142] State 40: The element of State 39, wherein: the second integrated element is configured to be electrically coupled to the passive element.

[0143] Type 41: An element of types 34 to 40, wherein the first substrate comprises 7 or fewer metal layers, and wherein the second substrate comprises 4 or fewer metal layers.

[0144] State 42: The element as described in states 34 to 41 further includes: a third substrate coupled to the second substrate, wherein the third substrate includes a third plurality of interconnected bonding pillars.

[0145] The various features of this case described herein can be implemented in different systems without departing from this case. It should be noted that the above examples are merely illustrative and should not be construed as limiting this case. The descriptions of the various forms of this case are intended to be illustrative, not to limit the scope of the appended claims. Therefore, the teachings of this case can be readily applied to other types of devices, and many substitutions, modifications, and variations will be readily apparent to those skilled in the art.

[0146] Phase 1: Phase 2 Phase 3 4: Stage 5: Stage 6: Stage 7: Stage 8: Stage 9: Stage 10: Stage 11: Stage 12: Stage 100: Package 102:Substrate 105: Integrated Components 106: Board 120: Dielectric layer 122: Interconnection 124: Solder Interconnect 154: Solder Interconnect 200: Package 201: Integrated Components 202:Substrate 203: Integrated Components 204:Substrate 205: Integrated Components 208: Encapsulation layer 209: Board 211: Passive components 213: Passive components 214: Solder Interconnect 215: Passive components 220: Dielectric layer 222: Interconnection 222a: Interconnection 222b: Interconnection 226: Solder interconnect 231: Solder interconnect 234: Solder interconnect 240: Dielectric layer 242: Interconnection 242a: Interconnection 242b: Interconnection 254: Solder interconnect 260: Encapsulation layer 261: Welded column interconnection 261a: Welded post interconnection 263: Interconnected weld columns 263a: Welded column interconnection 264: Solder Interconnect 264a: Solder Interconnect 364b: Solder Interconnect 366b: Solder Interconnect 700: Method 705: Steps 710: Steps 715: Steps 720: Steps 725: Steps 730: Steps 800: Carrier 801:Substrate 802: Interconnect 810: cavity 812: Interconnection 814: Interconnection 816: Interconnection 820: Dielectric layer 822: Dielectric layer 824: Dielectric layer 830: cavity 840: cavity 850: Dielectric layer 852: Interconnection 860: First solder mask layer 862: Second solder resist layer 900: Method 905: Steps 910: Steps 915: Steps 920: Steps 925: Steps 930: Steps 1000: Package 1002:Substrate 1020: Dielectric layer 1022: Interconnection 1060: Encapsulation layer 1061: Welded Column Interconnection 1063: Interconnected weld pillars 1064: Solder Interconnect 1100: Package 1200: Package 1300: Components 1302: Mobile phone equipment 1304: Laptop devices 1306: Fixed-location terminal equipment 1308: Wearable devices 1310: Motor vehicles

[0147] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A packaged and integrated component, comprising: A first substrate, the first substrate comprising: a first dielectric layer; a first plurality of interconnects at least partially located in the first dielectric layer; and a first plurality of solder interconnects coupled to the first plurality of interconnects; a second substrate, the second substrate comprising: a second dielectric layer; a second plurality of interconnects at least partially located in the second dielectric layer; and a second plurality of solder interconnects coupled to the second plurality of interconnects, wherein the second plurality of solder interconnects are coupled to the first plurality of solder interconnects via a plurality of solder interconnects; a passive element located between the first substrate and the second substrate, wherein the passive element directly contacts a surface of the first substrate or a surface of the second substrate; A first integrated element coupled to a first surface of the first substrate, wherein the first surface is a surface facing away from the second substrate; and a second integrated element coupled to a second surface of the second substrate, wherein the second surface faces away from the first substrate.

2. The element of claim 1, wherein the first integrated element, as part of a power distribution network (PDN), is configured to be electrically coupled to the passive element.

3. The element as claimed in claim 1 further includes: An encapsulation layer located between the first substrate and the second substrate, wherein the encapsulation layer at least partially encapsulates the passive component, the first plurality of solder interconnects, the second plurality of solder interconnects, and the plurality of solder interconnects.

4. The element of claim 3, wherein the encapsulation layer comprises a molding part, a bottom filler, an adhesive, a non-conductive paste (NCP) and / or a non-conductive film (NCF).

5. The element of claim 1, wherein the first substrate and the second substrate are separated by a minimum pitch of about 120 micrometers.

6. The element of claim 1 further includes a third plurality of solder interconnects coupled to the second surface of the second substrate, wherein the third plurality of solder interconnects are located to the side of the second integrated element, and wherein the second integrated element is coupled to the second substrate such that the second integrated element is not located between the first substrate and the second substrate.

7. The element of claim 6, wherein the second integrated element is configured to be electrically coupled to the passive element.

8. The element of claim 1, wherein the first substrate comprises 7 or fewer metal layers, and wherein the second substrate comprises 4 or fewer metal layers.

9. The element of claim 1, wherein the first plurality of bond interconnects includes a height of about 60 micrometers or less, and wherein the second plurality of bond interconnects includes a height of about 60 micrometers or less.

10. The element of claim 9, wherein the passive element comprises a height of about 100 micrometers or less.

11. A packaged and integrated device, comprising: A first substrate, the first substrate comprising: a first dielectric layer; a first plurality of interconnects; and a component for a first solder joint interconnect; a second substrate, the second substrate comprising: a second dielectric layer; a second plurality of interconnects; and a component for a second solder joint interconnect, wherein the component for the second solder joint interconnect is coupled to the component for the first solder joint interconnect via a plurality of solder interconnects; a passive element located between the first substrate and the second substrate; wherein the passive element is coupled to the first substrate via a first plurality of solder interconnects; and wherein the passive element is coupled to the second substrate via a second plurality of solder interconnects; a first integrated element coupled to a first surface of the first substrate, wherein the first surface is a surface facing away from the second substrate; and a second integrated element coupled to a second surface of the second substrate, wherein the second surface faces away from the first substrate.

12. The apparatus of claim 11, wherein the first integrated element, as part of a power distribution network (PDN), is configured to be electrically coupled to the passive element.

13. The apparatus of claim 11, further comprising: A component for encapsulation located between the first substrate and the second substrate, wherein the component for encapsulation at least partially encapsulates the passive element, the component for the first solder interconnect, the component for the second solder interconnect, and the plurality of solder interconnects.

14. The apparatus of claim 13, wherein the encapsulation component comprises a molding part, a bottom filler, an adhesive, a non-conductive paste (NCP), and / or a non-conductive film (NCF).

15. The apparatus of claim 11, wherein the first substrate and the second substrate are separated by a minimum pitch of about 120 micrometers.

16. The apparatus of claim 11 further includes a third plurality of solder interconnects coupled to the second surface of the second substrate, wherein the third plurality of solder interconnects are located to the side of the second integrated element, and wherein the second integrated element is coupled to the second substrate such that the second integrated element is not located between the first substrate and the second substrate.

17. The apparatus of claim 16, wherein the second integrated element is configured to be electrically coupled to the passive element.

18. The apparatus of claim 11, wherein the first substrate comprises seven or fewer metal layers, and wherein the second substrate comprises four or fewer metal layers.

19. The apparatus of claim 11, wherein the component for the first weld post interconnect includes a height of about 60 micrometers or less, and wherein the component for the second weld post interconnect includes a height of about 60 micrometers or less.

20. The device of claim 19, wherein the passive element comprises a height of about 100 micrometers or less.

21. The device of claim 11, wherein the device is selected from a group comprising: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

22. A method for manufacturing a component, comprising the steps of: providing a first substrate including a first plurality of solder interconnects; coupling a passive component to the first substrate; coupling a second substrate to the first substrate, the second substrate including a second plurality of solder interconnects, wherein the second substrate is coupled to the first substrate such that the passive component directly contacts a surface of the first substrate or a surface of the second substrate; wherein the step of coupling the second substrate to the first substrate includes the steps of: coupling the second plurality of solder interconnects to the first plurality of solder interconnects via a plurality of solder interconnects, and wherein the second substrate is coupled to the first substrate such that the passive component is located between the first substrate and the second substrate; coupling a second integrated component to a second surface of the second substrate, wherein the second surface is remote from the first substrate; and coupling a first integrated component to a first surface of the first substrate, wherein the first surface is a surface remote from the second substrate.

23. The method of claim 22, wherein the first integrated element, as part of a power distribution network (PDN), is configured to be electrically coupled to the passive element.

24. The method of claim 22 further includes the step of forming an encapsulation layer between the first substrate and the second substrate, wherein the encapsulation layer at least partially encapsulates the passive element, the first plurality of solder interconnects, the second plurality of solder interconnects and the plurality of solder interconnects.

25. The method of claim 24, wherein the encapsulation layer comprises a molding compound, a bottom filler, an adhesive, a non-conductive paste (NCP), and / or a non-conductive film (NCF).

26. The method of claim 22, wherein the first substrate and the second substrate are separated by a minimum pitch of about 120 micrometers.

27. The method of claim 22 further includes the step of: coupling a third plurality of solder interconnects to the second surface of the second substrate, wherein the third plurality of solder interconnects are located to the side of the second integrated element, and wherein the second integrated element is coupled to the second substrate such that the second integrated element is not located between the first substrate and the second substrate.

28. The method of claim 27, wherein the second integrated element is configured to be electrically coupled to the passive element.

29. The method of claim 22, wherein the first substrate comprises seven or fewer metal layers, and wherein the second substrate comprises four or fewer metal layers.

30. The method of claim 29, wherein the first plurality of bond interconnects includes a height of about 60 micrometers or less, wherein the second plurality of bond interconnects includes a height of about 60 micrometers or less, and wherein the passive element includes a height of about 100 micrometers or less.

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