Semiconductor device, semiconductor component and display panel including the same

Abstract

This invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a first semiconductor layer, an active region, a contact layer, and a structure containing a first metal element. The first semiconductor layer has a surface. The surface includes a first portion and a second portion. The active region is located on the first portion and includes AlGaInAs, InGaAsP, AlGaAsP, or AlGaInP. The contact layer includes oxygen (O) and a fifth metal element and is located on the second portion. The structure containing the first metal element is located on the contact layer. The contact layer directly contacts the structure containing the first metal element and the first semiconductor layer.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices, particularly semiconductor light-emitting devices, such as light-emitting diodes (LEDs). This disclosure also relates to methods for manufacturing semiconductor devices, semiconductor devices containing semiconductor devices, and display panels. [Previous Technology]

[0002] Semiconductor components are widely used in various products, and research and development of related materials for various semiconductor components continues. For example, III-V compound semiconductor materials containing group III and group V elements can be widely used in the manufacture of various semiconductor components, such as light-emitting diodes (LEDs), laser diodes (LDs), photoelectric detectors, solar cells, or power devices such as switches or rectifiers. In recent years, these semiconductor components have been widely used in lighting, medical, display, communication, and sensing systems. Among them, light-emitting diodes are widely used in various fields due to their low power consumption and long lifespan. [Summary of the Invention]

[0003] This invention provides a semiconductor device including a first semiconductor layer, an active region, a contact layer, and a structure containing a first metal element. The first semiconductor layer has a surface. The surface includes a first portion and a second portion. The active region is located on the first portion and includes AlGaInAs, InGaAsP, AlGaAsP, or AlGaInP. The contact layer is located on the second portion and includes oxygen (O) and a fifth metal element. The structure containing the first metal element is located on a p-type or n-type layer. The contact layer directly contacts the structure containing the first metal element and the first semiconductor layer.

[0004] In one embodiment of the present invention, the structure containing the first metal element does not directly contact the first semiconductor layer, and the structure containing the first metal element is electrically connected to the first semiconductor layer through a contact layer.

[0005] In one embodiment of the present invention, a bonding structure is further included, located below the first semiconductor layer.

[0006] In one embodiment of the present invention, the contact layer contains only a single metal element.

[0007] In one embodiment of the present invention, the first semiconductor layer comprises a phosphide or an arsenide. The present invention provides a method for manufacturing a semiconductor device, comprising the following steps: providing a growth substrate; forming a semiconductor stack on the growth substrate, the semiconductor stack comprising a first semiconductor layer and an active region; bonding the semiconductor stack to a bonding substrate; removing the growth substrate; removing a portion of the semiconductor stack to expose the first semiconductor layer; forming a contact layer on the first semiconductor layer, the contact layer comprising oxygen (O) and a fifth metal element; and forming a structure containing the first metal element on the contact layer.

[0008] In one embodiment of the present invention, a bonding structure is further formed between the first semiconductor layer and the bonding substrate.

[0009] In one embodiment of the present invention, the bonding structure comprises a thermosetting polymer.

[0010] In one embodiment of the present invention, the step of forming a structure containing a first metal element on the contact layer includes: performing a heating step at a first temperature, wherein the thermosetting polymer has a thermal decomposition temperature, the first temperature is less than the thermal decomposition temperature, or the difference between the first temperature and the thermal decomposition temperature is less than or equal to 50°C.

[0011] In one embodiment of the present invention, the structure containing the first metallic element includes an alloy.

Implementation Method

[0023] The following embodiments will be illustrated with drawings to explain the concept of the present invention. In the drawings or description, similar or identical components will be described using similar or identical reference numerals. Unless otherwise specified, the shape or size of each element in the drawings is only illustrative and is not actually limited thereto. It should be noted that elements not shown or described in the drawings may be in forms known to those skilled in the art.

[0024] In this disclosure, unless otherwise specified, the general formula InGaP represents Inx0Ga1-x0P, where 0 < x0 < 1; the general formula AlInP represents Alx1In1-x1P, where 0 < x1 < 1; the general formula AlGaInP represents Alx2Gax3In1-x2-x3P, where 0 < x2 < 1 and 0 < x3 < 1; the general formula InGaAsP represents Inx4Ga1-x4Asx5P1-x5, where 0 < x4 < 1 and 0 < x5 < 1; the general formula AlGaInAs represents Alx6Gax7In1-x6-x7As, where 0 < x6 < 1 and 0 < x7 < 1; the general formula InGaAs represents Inx8Ga1-x8As, where 0 < x8 < 1; and the general formula AlGaAs represents Alx9Ga1-x9As, where... 0 < x9 < 1; the general formula InGaN represents Inx10Ga1-x10N, where 0 < x10 < 1; the general formula AlGaN represents Alx11Ga1-x11N, where 0 < x11 < 1; the general formula AlGaAsP represents Alx12Ga1-x12Asx13P1-x13, where 0 < x12 < 1 and 0 < x13 < 1; the general formula InGaAsN represents Inx14Ga1-x14Asx15N1-x15, where 0 < x14 < 1 and 0 < x15 < 1; the general formula AlInGaN represents Alx16Inx17Ga1-x16-x17N, where 0 < x16 < 1 and 0 < x17 < 1. The content of each element can be adjusted for different purposes, such as, but not limited to, adjusting the energy level, or, when the semiconductor element is a light-emitting element, adjusting the peak wavelength or domain wavelength of the light-emitting element.

[0025] The semiconductor devices disclosed herein are, for example, optoelectronic devices, such as light-emitting devices (e.g., light-emitting diodes or laser diodes), light-absorbing devices (e.g., photo-detectors or solar cells), or non-optoelectric devices. The composition of each layer and / or dopant contained in the semiconductor devices disclosed herein can be analyzed by any suitable method, such as secondary ion mass spectrometer (SIMS), energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), or ultraviolet photoelectron spectroscopy (UPS). The thickness and other dimensions of each layer can also be analyzed using any suitable method, such as transmission electron microscopy (TEM), scanning electron microscopy (SEM), or scanning transmission electron microscopy (STEM).

[0026] Those skilled in the art will understand that other components can be added to the embodiments described below. For example, unless otherwise specified, a description such as "the first layer (or structure) is located on the second layer (or structure)" may include embodiments where the first layer (or structure) and the second layer (or structure) are in direct contact, or embodiments where the first layer (or structure) and the second layer (or structure) have other structures between them and are not in direct contact. Furthermore, it should be understood that the vertical positional relationship of each layer (or structure) may change depending on the viewing angle.

[0027] Furthermore, in this disclosure, the statement that a layer or structure is "substantially composed of M" indicates that the main component of the layer or structure is M, but does not exclude that the layer or structure contains dopants or unavoidable impurities.

[0028] Figure 1 is a cross-sectional structural schematic diagram of a semiconductor device 10 according to an embodiment of the present disclosure. As shown in Figure 1, the semiconductor device 10 includes a substrate 100 and a semiconductor structure 102 located on the substrate 100. The semiconductor structure 102 may be an epitaxial structure and may include a first semiconductor layer 104, a second semiconductor layer 106, and an active region 108 located between the first semiconductor layer 104 and the second semiconductor layer 106. In one embodiment, the semiconductor structure 102 further includes a third semiconductor layer 110 located between the active region 108 and the first semiconductor layer 104. A p-type or n-type layer (contact layer) 112 is located on the first semiconductor layer 104. As shown in Figure 1, a structure 114 containing a first metal element and a structure 116 containing a second metal element are disposed on the semiconductor structure 102. Specifically, the first semiconductor layer 104 has a first surface 104a facing the substrate 100 and a second surface 104b facing the structure containing the first metal element and the structure containing the second metal element. The second surface 104b includes a first portion P1 and a second portion P2.

[0029] In one embodiment, the second semiconductor layer 106, the active region 108, and the third semiconductor layer 110 are located on the first portion P1 but not on the second portion P2. A p-type or n-type layer 112 is located on the second portion P2 but not on the first portion P1, and a structure 114 containing a first metal element is located on this p-type or n-type layer 112. Specifically, this p-type or n-type layer 112 is located between and in direct contact with the structure 114 containing the first metal element and the first semiconductor layer 104. In one embodiment, on the first semiconductor layer 104, the second semiconductor layer 106, the active region 108, and the third semiconductor layer 110 form a first mesa structure S1, and the first semiconductor layer 104 forms a second mesa structure S2. As shown in Figure 1, the first mesa structure S1 has a first width W1, and the second mesa structure S2 has a second width W2 greater than the first width W1. The first width W1 is the maximum width of the first platform structure S1, and the second width W2 is the maximum width of the second platform structure S2. In a cross-section, the first platform structure S1 and the second platform structure S2 may each be trapezoidal or rectangular.

[0030] In one embodiment, in a cross-section, the side surface of the first platform structure S1 is not flush with the side surface of the second platform structure S2. In one embodiment, the first platform structure S1 and the second platform structure S2 may each be rounded rectangles in the top view to reduce point discharge and improve stability. In one embodiment, viewed from above, the semiconductor element 10 may have a length of less than 150 μm or 100 μm and a width of less than 150 μm or 100 μm. The length-to-width ratio of the semiconductor element 10 may be in the range of 0.3 to 1.

[0031] The substrate 100 may include conductive or insulating materials. The conductive materials include gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), germanium (Ge), or silicon (Si), etc.; the insulating materials include sapphire, etc. In one embodiment, the substrate 100 is a growth substrate, that is, the semiconductor structure 102 may be formed on the substrate 100 epitaxially by a method such as metal organic chemical vapor deposition (MOCVD). In one embodiment, the substrate 100 is a bonding substrate rather than a growth substrate, and may be connected to the semiconductor structure 102 by a bonding structure 124 (as shown in Figure 2B). In one embodiment, the semiconductor element 10 may not have a substrate 100. The total thickness t0 of the semiconductor structure 102 may be less than or equal to 10 µm. The ratio of the total thickness t0 to the length or width of the semiconductor element 10 can be less than or equal to 0.5, for example less than 0.3 or 0.1, to ensure the structural stability of the semiconductor element 10 during manufacturing.

[0032] In one embodiment, the first semiconductor layer 104 includes a first dopant, and the second semiconductor layer 106 includes a second dopant, such that the first semiconductor layer 104 and the second semiconductor layer 106 have different conductivity types. For example, the first semiconductor layer 104 is n-type, and the second semiconductor layer 106 is p-type; or the first semiconductor layer 104 is p-type, and the second semiconductor layer 106 is n-type. In one embodiment, the first dopant and the second dopant may respectively include elements from Group II, Group IV, or Group VI of the periodic table. For example, the first dopant and the second dopant may respectively include C, Zn, Si, Ge, Sn, Se, Mg, or Te. The first semiconductor layer 104 and the second semiconductor layer 106 respectively provide electrons and holes, or holes and electrons. In one embodiment, the third semiconductor layer 110 has the same conductivity type as the first semiconductor layer 104. In one embodiment, the first semiconductor layer 104, the second semiconductor layer 106, the active region 108, and the third semiconductor layer 110 each comprise a III-V group semiconductor material. In one embodiment, the aforementioned III-V group semiconductor material comprises Al, Ga, As, P, N, or In elements. Specifically, in one embodiment, the aforementioned III-V group semiconductor material may be a binary compound semiconductor (such as GaAs, GaP, or GaN), a ternary compound semiconductor (such as InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN), or a quaternary compound semiconductor (such as AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In one embodiment, the active region 108 is substantially composed of a ternary compound semiconductor (such as InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary compound semiconductor (such as AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In some embodiments, the first semiconductor layer 104, the second semiconductor layer 106, the active region 108, and the third semiconductor layer 110 do not contain nitrogen (N) elements. In some embodiments, the first semiconductor layer 104, the second semiconductor layer 106, the active region 108, and the third semiconductor layer 110 respectively contain a phosphide compound or an arsenide compound.

[0033] According to one embodiment, when the semiconductor element 10 is a light-emitting element, the active region 108 can emit light when the semiconductor element 10 is operating. The light includes visible light or invisible light. The peak wavelength emitted by the semiconductor element 10 depends on the material composition of the active region 108. The material of the active region 108 may include ternary compound semiconductors (such as InGaN, InGaAs, AlGaN, AlGaAs, or InGaP) or quaternary compound semiconductors (such as InGaAsP, AlGaInAs, or AlGaInP). According to some embodiments, the semiconductor element 10 can emit blue or deep blue light with a peak wavelength of 400 nm to 490 nm, green light with a peak wavelength of 490 nm to 550 nm, ultraviolet light with a peak wavelength of 250 nm to 400 nm, red light with a peak wavelength of 610 nm to 700 nm, yellow light with a peak wavelength of 530 nm to 600 nm, or infrared light with a peak wavelength of 700 to 1700 nm.

[0034] The structure 114 containing the first metal element and the structure 116 containing the second metal element can each be a single layer or multiple layers. Both the structure 114 containing the first metal element and the structure 116 containing the second metal element can serve as contact portions. According to some embodiments, the structure 114 containing the first metal element and the structure 116 containing the second metal element can be directly electrically connected to an external power source (not shown), or electrically connected to an external power source (not shown) through other structures (such as the first electrode pad 120 and the second electrode pad 122 described later). In a cross-section, the structure 114 containing the first metal element and the structure 116 containing the second metal element can each be trapezoidal or rectangular. In one embodiment, the structure 114 containing the first metal element includes a first metal element M1, and the structure 116 containing the second metal element includes a second metal element M2. The first metal element M1 and the second metal element M2 can be the same or different. In one embodiment, the structure 114 containing the first metal element does not contain beryllium (Be).

[0035] In one embodiment, the structure 114 containing the first metal element further includes a third metal element M3, which is different from the first metal element M1. In one embodiment, the structure 114 containing the first metal element includes an alloy containing the first metal element M1 and the third metal element M3. In one embodiment, the structure 114 containing the first metal element may include a first layer and a second layer (not shown), the first layer directly contacting the p-type or n-type layer 112, and the second layer located on the first layer. In one embodiment, the first layer contains the first metal element M1, and the second layer contains the third metal element M3. In one embodiment, the structure 116 containing the second metal element further includes a fourth metal element M4, which is different from the second metal element M2. In one embodiment, the structure 116 containing the second metal element includes an alloy containing the second metal element M2 and the fourth metal element M4. In one embodiment, the structure 116 containing the second metal element may include a third layer and a fourth layer, the third layer directly contacting the second semiconductor layer 106, and the fourth layer located on the third layer. In one embodiment, the third layer contains a second metal element M2, and the fourth layer contains a fourth metal element M4. In one embodiment, the third metal element M3 and the fourth metal element M4 may be the same. In one embodiment, the first metal element M1, the second metal element M2, the third metal element M3, and the fourth metal element M4 may be selected from Ti, Ni, Al, Zn, Ge, Mo, W, V, Ga, Au, or Ag, respectively.

[0036] In one embodiment, the structure 114 containing the first metal element does not directly contact the first semiconductor layer 104. The structure 114 containing the first metal element can be electrically connected to the first semiconductor layer 104 via a p-type or n-type layer 112. In one embodiment, the material of the p-type or n-type layer 112 has a first contact resistivity in the vertical direction and a second contact resistivity in the horizontal direction. The second contact resistivity can be greater than the first contact resistivity, thereby allowing current to flow primarily through the p-type or n-type layer 112 in the vertical direction, and the p-type or n-type layer 112 is electrically connected to the structure 114 containing the first metal element and the first semiconductor layer 104. In some embodiments, the first contact resistivity and the second contact resistivity can be measured, for example, in Ω·cm². In some embodiments, when the p-type or n-type layer 112 has a different or the same conductivity type as the first semiconductor layer 104, the p-type or n-type layer 112 can serve as a tunneling layer. In some embodiments, when the p-type or n-type layer 112 has the same conductivity type as the first semiconductor layer 104, the p-type or n-type layer 112 can further reduce the energy barrier (e.g., Schottky barrier) between the first semiconductor layer 104 and the structure 114 containing the first metal element. In one embodiment, the p-type or n-type layer 112 does not overlap with the active region 108 in the vertical direction. In one embodiment, the first semiconductor layer 104 has a dopant concentration greater than or equal to 1 x 10¹⁹ / cm³ to reduce the contact impedance between the first semiconductor layer 104 and the structure 114 containing the first metal element.

[0037] The material of the first semiconductor layer 104 has a conduction band and a valence band, wherein the bottom edge of the conduction band is denoted by Ec, and the upper edge of the valence band is denoted by Ev. The material of a p-type or n-type layer 112 has a first work function WF1, and the first metal element M1 has a second work function WF2. In some embodiments, when the conduction mode of the first semiconductor layer 104 is n-type, the first work function WF1 satisfies WF1 < (Ec + Ev) / 2. In some embodiments, when the conduction mode of the first semiconductor layer 104 is p-type, the first work function WF1 satisfies WF1 > (Ec + Ev) / 2. In some embodiments, when the conduction mode of the p-type or n-type layer 112 is n-type, the second work function WF2 is greater than the first work function WF1. In some embodiments, when the conduction mode of the p-type or n-type layer 112 is p-type, the first work function WF1 is greater than the second work function WF2. In some embodiments, by employing a first semiconductor layer 104, a p-type or n-type layer 112, and a structure 114 containing a first metal element that conform to the above-described relationships, the contact resistivity between the p-type or n-type layer 112 and the structure 114 containing the first metal element can be further improved. In one embodiment, the material of the p-type or n-type layer 112 has a bandgap larger than that of the material bandgap of the first semiconductor layer 104 to prevent the p-type or n-type layer 112 from absorbing light emitted by the active region 108. In one embodiment, the material of the p-type or n-type layer 112 includes oxygen (O) and a fifth metal element M5. In one embodiment, the fifth metal element M5 is the same as the first metal element M1 or the third metal element M3, thereby further improving the adhesion between the p-type or n-type layer 112 and the structure 114 containing the first metal element, and also improving the thermal stability of the semiconductor device 10. In one embodiment, the fifth metallic element M5 is In, Ti, Al, Zn, Ni, Ga, Mo, V, W, or Nb.

[0038] Regarding the metal elements contained in the p-type or n-type layer 112, the p-type or n-type layer 112 may contain only a single metal element. The aforementioned metal element may include In, Ti, Al, Zn, Ni, Ga, Mo, V, W, or Nb. In some embodiments, the p-type or n-type layer 112 contains two or more metal elements. For example, in one embodiment, the p-type or n-type layer 112 further includes a sixth metal element M6, which is different from the fifth metal element M5. The fifth metal element M5 and the sixth metal element M6 may be In, Ti, Al, Zn, Ni, Ga, Mo, V, W, or Nb, respectively. In one embodiment, the p-type or n-type layer 112 further includes group 5 elements (such as N, P, or As). Specifically, in one embodiment, the p-type or n-type layer 112 may contain a first metal oxide compound formed by oxygen and the fifth metal element M5. In one embodiment, the p-type or n-type layer 112 may further comprise a second metal oxide formed of oxygen and the sixth metal element M6. In one embodiment, the p-type or n-type layer 112 may further comprise a third metal oxide formed of oxygen and a group 5 element. For example, the first or second metal oxide may be n-type (e.g., TiOx, InOx, MoOx, VOx, WOx, GaOx, or NbOx) or p-type (e.g., NiOx). The third metal oxide may be POx, NOx, or AsOx. In one embodiment, the p-type or n-type layer 112 has a thickness greater than 0 nm and less than or equal to 20 nm. For example, the thickness of the p-type or n-type layer 112 may be in the range of 0.5 nm to 15 nm, such as 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, or 14 nm. In some embodiments, when the thickness of the p-type or n-type layer 112 is less than or equal to 5 nm, the contact resistivity between the structure 114 containing the first metal element and the first semiconductor layer 104 can be improved by the tunneling effect.

[0039] In some embodiments, when the first semiconductor layer 104 includes a phosphide or arsenide, the presence of the p-type or n-type layer 112 can prevent the formation of an interfacial compound due to direct contact between the first semiconductor layer 104 and the structure 114 containing the first metal element. For example, when the structure 114 containing the first metal element contains Au and the first semiconductor layer 104 is a phosphide (e.g., GaP), the aforementioned interfacial compound can be Au2P3, whose bandgap energy is smaller than that of the active region 108 material, and therefore it will absorb the light emitted by the active region 108.

[0040] Figure 2A is a top view of a semiconductor element 20 according to an embodiment of the present disclosure. Figure 2B is a cross-sectional view of the semiconductor element 20 in Figure 2A along line X-X'. For clarity, Figure 2A only shows the components required for illustration (as indicated in the figure).

[0041] The semiconductor element 20 differs from the semiconductor element 10 in that the semiconductor element 20 further includes an insulating structure 118 located on the semiconductor structure 102, a first electrode pad 120 connected to the structure 114 containing the first metal element, a second electrode pad 122 connected to the structure 116 containing the second metal element, and a bonding structure 124 located under the first semiconductor layer 104. In one embodiment, the insulating structure 118 substantially conformally covers the semiconductor structure 102, the structure 114 containing the first metal element, and the structure 116 containing the second metal element. As shown in Figure 2B, the insulating structure 118 has a first opening 118a and a second opening 118b. The structure 114 containing the first metal element directly contacts the first electrode pad 120 through the first opening 118a, and the structure 116 containing the second metal element directly contacts the second electrode pad 122 through the second opening 118b.

[0042] The first electrode pad 120 and the second electrode pad 122 can be electrically connected to an external power source (not shown) and can act as buffers to absorb stress generated during processes such as wire bonding or solder bonding. The upper surfaces of the first electrode pad 120 and the second electrode pad 122 can be substantially at the same level (with an allowable error of approximately ±1 μm). In one embodiment, the first electrode pad 120 covers a portion of the insulating structure 118 and fills the first opening 118a, and the second electrode pad 122 covers a portion of the insulating structure 118 and fills the second opening 118b. In some embodiments, the first platform structure S1, the insulating structure 118, and the first electrode pad 122 can overlap in the vertical direction. The first electrode pad 120 and the second electrode pad 122 can be single-layered or multi-layered, respectively. In one embodiment, the materials of the first electrode pad 120 and the second electrode pad 122 include Ni, Ti, Pt, Pd, Ag, Au, Al, Sn or Cu, or alloys containing the above elements.

[0043] The insulating structure 118 protects the semiconductor structure 102 from moisture or contamination and improves the reliability of the semiconductor element 20. In one embodiment, the insulating structure 118 comprises a dielectric material, such as an oxide (e.g., SiO2) or a nitride (e.g., SiNx). In one embodiment, the insulating structure 118 comprises a reflective structure, such as a distributed Bragg reflector (DBR) formed by alternating stacks of two or more semiconductor materials with different refractive indices. In one embodiment, the insulating structure 118 has a thickness t1, which may be less than 15% or 10% of the total thickness t0 of the semiconductor structure 102.

[0044] The bonding structure 124 may be an electrically-insulative structure. In one embodiment, the bonding structure 124 includes a main layer (not shown) containing a thermosetting polymer. In one embodiment, the thermosetting polymer includes, for example, polyimide, epoxy resin, polyester, polyurethane, benzocyclobutene (BCB), or combinations thereof. In one embodiment, the bonding structure 124 further includes an auxiliary layer (not shown) located between the main layer and the first semiconductor layer 104, or between the main layer and the substrate 100, to further improve the adhesion between the two. The material of the auxiliary layer may be different from that of the main layer. In one embodiment, the material of the auxiliary layer includes oxides (such as SiO2) or nitrides (such as SiNx). The positions, relative relationships, material compositions, and structural variations of other layers or structures have been described in detail in the previous embodiments and will not be repeated here.

[0045] Figures 3A to 3J are schematic diagrams illustrating a method for manufacturing a semiconductor device 30A according to an embodiment of this disclosure. It should be understood that although multiple semiconductor devices can be formed during the process, for the sake of simplicity, the following paragraphs mainly describe the structural changes of a single semiconductor device during the process.

[0046] As shown in Figure 3A, firstly, a growth substrate 101 is provided. A semiconductor stack 102' is formed on the growth substrate 101. The semiconductor stack 102' includes a first semiconductor layer 104, a second semiconductor layer 106, and an active region 108 located between the first semiconductor layer 104 and the second semiconductor layer 106. A third semiconductor layer 110 is formed between the first semiconductor layer 104 and the active region 108.

[0047] Then, referring to Figures 3B and 3C, the semiconductor stack 102' is bonded to the bonding substrate 101' through the bonding structure 124, and the growth substrate 101 is removed.

[0048] Next, as shown in Figure 3D, the structure of Figure 3C is flipped and a portion of the semiconductor stack 102' is removed to expose a portion of the first semiconductor layer 104, and a first platform structure S1 is formed on the first semiconductor layer 104.

[0049] Then, as shown in Figure 3E, a p-type or n-type layer 112 is formed on the exposed portion of the first semiconductor layer 104, and a structure 114 containing the first metal element is formed on this p-type or n-type layer 112. In one embodiment, the p-type or n-type layer 112 may be formed by film deposition, such as atomic layer deposition (ALD) or electron beam evaporation.

[0050] In one embodiment, forming the structure 114 containing the first metal element includes forming a structure containing the first metal element M1 on a p-type or n-type layer 112 and performing a first heating step at a first temperature. In one embodiment, the heating step may be an alloying process, such as a process for forming an alloy containing the first metal element M1 and other metal elements (e.g., the aforementioned third metal element M3). The first temperature may be the ambient temperature provided by the equipment (e.g., a furnace) for the first heating step. In one embodiment, the first temperature may be lower than the thermal decomposition temperature of the thermosetting polymer contained in the bonding structure 124, or the difference between the first temperature and the aforementioned thermal decomposition temperature may be less than or equal to 50°C or less than or equal to 30°C, thereby ensuring process stability. The aforementioned thermal decomposition temperature may be the temperature at which the aforementioned thermosetting polymer experiences a weight loss exceeding 1% within one hour.

[0051] As shown in Figures 3F and 3G, a structure 116 containing a second metal element is further formed on the first platform structure S1, and a portion of the first semiconductor layer is removed to form a second platform structure S2. Forming the structure 116 containing the second metal element may include forming a structure containing the second metal element M2 on the second semiconductor layer 106, and performing a second heating step at a second temperature. The second temperature may be the ambient temperature provided by the device (e.g., furnace tube) for the second heating step. In one embodiment, the difference between the first temperature and the second temperature is less than 50°C or less than 30°C. In one embodiment, the first temperature and the second temperature are respectively less than 500°C or less than 400°C. In one embodiment, the first temperature and the second temperature are respectively greater than or equal to 200°C or greater than or equal to 300°C.

[0052] As shown in Figure 3H, an insulating structure 118 is then conformally formed on the first platform structure S1, the second platform structure S2, the structure 114 containing the first metal element, and the structure 116 containing the second metal element. The sidewalls of the first platform structure S1 and the second platform structure S2 are completely covered by the insulating structure 118, thereby completely protecting the semiconductor structure 102. A first opening 118a and a second opening 118b are formed by removing a portion of the insulating structure 118.

[0053] Next, as shown in Figure 3I, a first electrode pad 120 is formed on a structure 114 containing a first metal element, and a second electrode pad 122 is formed on a structure 116 containing a second metal element.

[0054] As shown in Figure 3I, the structure can be further separated into multiple semiconductor elements 30A by a cutting method such as laser cutting. Figure 3J shows the structure of each semiconductor element 30A.

[0055] Figure 3K is a cross-sectional structural schematic diagram of a semiconductor device 30B according to an embodiment of the present disclosure. As shown in Figure 3K, in one embodiment, the first electrode pad 120 may also be formed on a portion of the first platform structure S1 to improve the structural strength of the semiconductor device. In one embodiment, the first electrode pad 120 may have a varying thickness, or the first electrode pad 120 may have a non-planar upper surface. As shown in Figure 3K, the first electrode pad 120 may include a first portion 120a and a second portion 120b, the first portion 120a being on the structure 114 containing the first metal element and having a first thickness h1, and the second portion 120b being on the first platform structure S1 and having a second thickness h2, wherein the second thickness h2 may be less than the first thickness h1.

[0056] Figure 3L is a cross-sectional view of a semiconductor device 30C according to an embodiment of the present disclosure. As shown in Figure 3L, a p-type or n-type layer 112 is conformally formed on the upper surface of the semiconductor structure 102. In one embodiment, the p-type or n-type layer 112 directly contacts the structure 114 containing the first metal element, the structure 116 containing the second metal element, and the insulating structure 118. Specifically, as shown in Figure 3L, the p-type or n-type layer 112 covers and directly contacts the first side surface e1, the second side surface e2, and the upper surface e3 of the first platform structure S1, and the upper surface e4 of the second platform structure S2. In one embodiment, the p-type or n-type layer 112 does not cover the sidewalls of the first semiconductor layer 104. The p-type or n-type layer 112 directly contacts the structure 116 containing the second metal element, and may not overlap with the structure 116 containing the second metal element in the vertical direction. In one embodiment, the p-type or n-type layer 112 has a lower contact resistivity in the vertical direction compared to the horizontal direction. Therefore, when the semiconductor device 30C is operating, no current path is formed between the structure 116 containing the second metal element and the structure 114 containing the first metal element, or between the structure 116 containing the second metal element and the first semiconductor layer 104. Figure 3M is a schematic cross-sectional view of a semiconductor device 30D according to an embodiment of the present disclosure. As shown in Figure 3M, the p-type or n-type layer 112 may further cover a portion of the upper surface e5, the third side surface e6, and the fourth side surface e7 of the structure 116 containing the second metal element, thereby allowing the second electrode pad 122 to directly contact the portion of the upper surface e5 of the structure 116 containing the second metal element that is not covered by the p-type or n-type layer 112. In order to form the structure shown in Figure 3M, in the manufacturing process, a structure 116 containing a second metal element is first formed on the first platform structure S1, then a p-type or n-type layer 112 is formed on the first platform structure S1 and a portion of the structure 116 containing the second metal element, and then a structure 114 containing a first metal element is further formed on the p-type or n-type layer 112.

[0057] The positions, relative relationships, material composition, and structural variations of other layers or structures have been described in detail in the previous embodiments and will not be repeated here.

[0058] Figure 4A is a cross-sectional schematic diagram of a semiconductor device 400 according to an embodiment of the present disclosure. Figure 4B is a cross-sectional schematic diagram of a semiconductor device 400' according to an embodiment of the present disclosure.

[0059] As shown in Figures 4A and 4B, semiconductor device 400 or semiconductor device 400' includes a plurality of semiconductor elements 40. The structure of each semiconductor element 40 in Figure 4A is similar to the structure of the aforementioned semiconductor element 30A. Specifically, the semiconductor element 40 may be a semiconductor element described in any embodiment of this disclosure (such as semiconductor element 10, 20, 30B, 30C, or 30D).

[0060] In Figures 4A and 4B, the semiconductor element 40 does not have a growth substrate 101. Referring to Figure 4A, a plurality of semiconductor elements 40 are disposed on a bonding substrate 101'. In one embodiment, the bonding substrate 101' includes a first region A1 and a second region A2, the first region A1 being covered by a bonding structure 124, while the second region A2 is not covered by the bonding structure 124. Specifically, the first region A1 overlaps with the semiconductor element 40 in the vertical direction. That is, in Figure 4A, the bonding structure 124 is not continuously distributed on the bonding substrate 101'. In Figure 4A, the bonding structure 124 has an upper edge 124e and a sidewall Q1, and an insulating structure 118 covers the upper edge but not the sidewall Q1. In one embodiment, the insulating structure 118 has a sidewall Q2 that overlaps with the sidewall Q1 in the vertical direction. The sidewall Q1 and the sidewall Q3 of the first semiconductor layer 104 do not overlap in the vertical direction. In one embodiment, the upper surface near the upper edge of the bonding structure 124 is not covered by the insulating structure 118. In another embodiment, the bonding structure 124 has a width less than or equal to the width of the first semiconductor layer 104.

[0061] Figure 4B illustrates another configuration in which a plurality of semiconductor elements 40 are embedded in a bonding structure 124. The bonding structure 124 is continuously distributed on the bonding substrate 101' and directly contacts more than one semiconductor element 40. In some embodiments, the bonding structure 124 may help to hold the semiconductor element 40 in a predetermined position and may protect the semiconductor structure 102 within the semiconductor element 40 during transport.

[0062] In one embodiment, a blue tape, a thermal release sheet or tape, or a light release tape (such as polyethylene terephthalate, PET) may be disposed between the semiconductor element 40 and the bonding substrate 101'. Specifically, the blue tape, thermal release sheet or tape, or light release tape may be disposed between the bonding structure 124 and the bonding substrate 101', or may directly contact and cover the first electrode pad 120 and the second electrode pad 122 of the semiconductor element 40.

[0063] The positions, relative relationships, material composition, and structural variations of other layers or structures have been described in detail in the previous embodiments and will not be repeated here.

[0064] Figure 5A is a top view of a display panel 500 according to an embodiment of the present disclosure. Figures 5B and 5C are partial cross-sectional structural diagrams of the display panel 500 according to an embodiment of the present disclosure. Specifically, Figure 5B shows a cross-sectional view along line A-A' in Figure 5A, and Figure 5C shows a cross-sectional view along line B-B' in Figure 5A.

[0065] In one embodiment, the display panel 500 includes a carrier substrate 101” and a plurality of pixel units 50 located on the carrier substrate 101”. The plurality of pixel units 50 are arranged along the row direction x and the column direction y. The plurality of pixel units 50 may be formed on the carrier substrate 101” by a transfer method. The carrier substrate 101” may be glass, plastic, silicon substrate, or printed circuit board (PCB). Each pixel unit 50 includes a plurality of semiconductor elements. In one embodiment, each pixel unit 50 includes three semiconductor elements, namely semiconductor element 50a, semiconductor element 50b, and semiconductor element 50c. Specifically, in this embodiment, semiconductor elements 50a, semiconductor element 50b, and semiconductor element 50c are arranged with a first spacing d1 in the row direction x and a second spacing d2 in the column direction y. In one embodiment, the first spacing d1 is less than or equal to 100 µm, and the second spacing d2 is less than or equal to 50 µm. Semiconductor elements 50a, 50b, and 50c can each emit light in different wavelength ranges. For example, semiconductor elements 50a, 50b, and 50c can each emit red, green, and blue light, respectively. A driving circuit and a control unit (not shown) can be further provided on the carrier substrate 101” to drive the pixel unit 50 and control the emission time of the pixel unit 50.

[0066] As shown in Figures 5B and 5C, each semiconductor element 50a, semiconductor element 50b, and semiconductor element 50c is electrically connected to the carrier substrate 101 through a contact structure 60. The contact structure 60 includes a connection layer 60a and a circuit electrode 60b. In one embodiment, semiconductor element 50a may be any of the semiconductor elements described in any embodiment of this disclosure (such as semiconductor elements 10, 20, 30A, 30B, 30C, or 30D), and semiconductor elements 50b and 50c may have structures different from those of semiconductor element 50a.

[0067] As shown in Figure 5C, each semiconductor element 50b and semiconductor element 50c includes a semiconductor stack 102', an insulating structure 118, and an electrode pad 120. The semiconductor stack 102' has a first semiconductor layer 104', a second semiconductor layer 106', an active region 108' located between the first semiconductor layer 104' and the second semiconductor layer 106', and a third semiconductor layer 110' located between the first semiconductor layer 104' and the active region 108'. The insulating structure 118 covers the sidewalls and a portion of the surface of the semiconductor stack 102'. The electrode pad 120' is electrically connected to the semiconductor stack 102'. In some embodiments, the active region 108' overlaps with the electrode pad 120', while the electrode pad 120 and the active region 108 may overlap or not overlap (not shown). In one embodiment, the material of the active region 108' is different from the material of the active region 108. For example, active region 108' includes nitrogen (N) while active region 108 includes as (As) or phosphorus (P) elements. In one embodiment, a conductive layer (not shown) may be further disposed between the second semiconductor layer 106' and the electrode pad 120'. The conductive layer may contain a conductive oxide such as indium tin oxide (ITO).

[0068] Figures 5D and 5E are partial cross-sectional structural diagrams of a display panel 500 according to another embodiment of this disclosure. Specifically, Figure 5D shows a cross-sectional view along line A-A' in Figure 5A, and Figure 5E shows a cross-sectional view along line B-B' in Figure 5A. In one embodiment, semiconductor elements 50a, 50b, and 50c do not have bonding structures 124, thereby further reducing the thickness of each semiconductor element.

[0069] The positions, relative relationships, material composition, and structural variations of other layers or structures have been described in detail in the previous embodiments and will not be repeated here.

[0070] Based on the above, this disclosure provides a semiconductor element, a method for manufacturing a semiconductor element, a semiconductor device, or a display panel. The semiconductor element provided by this disclosure can achieve improvements in photoelectric properties such as contact resistance and process stability. Specifically, the semiconductor element or semiconductor device disclosed herein can be applied to various fields, such as products in lighting, medical, display, communication, sensing, and power systems, including lamps, monitors, mobile phones, tablets, automotive dashboards, televisions, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signals, outdoor displays, and medical devices.

[0071] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art should understand that some modifications or changes can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. Furthermore, the above embodiments can be combined or substituted with each other where appropriate, and are not limited to the specific embodiments described. For example, the relevant parameters of a specific component or the connection relationship between a specific component and other components disclosed in one embodiment can also be applied to other embodiments, and all fall within the scope of protection of the present invention. [Simplified Explanation of the Diagram]

[0012] Figure 1 is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 2A is a top view of a semiconductor device according to an embodiment of the present disclosure. Figure 2B is a cross-sectional view of the semiconductor device in Figure 2A along line X-X'.

[0014] Figures 3A to 3J are schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 3K is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 3L is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 3M is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present disclosure.

[0018] Figure 4A is a cross-sectional structural schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

[0019] Figure 4B is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0020] Figure 5A is a top view schematic diagram of a display panel according to an embodiment of the present disclosure.

[0021] Figures 5B and 5C are schematic cross-sectional views of a display panel according to an embodiment of the present disclosure.

[0022] Figures 5D and 5E are schematic cross-sectional views of a display panel according to an embodiment of the present disclosure.

Claims

1. A semiconductor element, comprising: A semiconductor structure includes: a first semiconductor layer having a surface including a first portion and a second portion; an active region located on the first portion; a contact layer located on the second portion, the contact layer having a conductivity type of p-type or n-type and including oxygen (O) and a metal element; and a structure containing a first metal element located on the contact layer; wherein the contact layer directly contacts the structure containing the first metal element and the first semiconductor layer, and the band gap of the contact layer is greater than the band gap of the first semiconductor layer.

2. The semiconductor element as described in claim 1, wherein the conductivity type of the contact layer is different from that of the first semiconductor layer.

3. The semiconductor device as described in claim 1, wherein the semiconductor structure further includes a second semiconductor layer and a third semiconductor layer, wherein the active region is located between the first semiconductor layer and the second semiconductor layer, and the third semiconductor layer is located between the active region and the first semiconductor layer.

4. The semiconductor device as described in claim 3, wherein the second semiconductor layer, the active region, and the third semiconductor layer form a first platform structure, the first semiconductor layer forms a second platform structure, the first platform structure has a first width W1, and the second platform structure has a second width W2 greater than the first width W1.

5. The semiconductor element as described in claim 1, wherein the semiconductor structure has a total thickness, the ratio of the total thickness to a length or a width of the semiconductor element being less than or equal to 0.

5.

6. The semiconductor element as described in claim 1 further includes a substrate and a bonding structure, wherein the bonding structure is located between the first semiconductor layer and the substrate and includes a thermosetting polymer.

7. The semiconductor element as described in claim 1, wherein the structure containing the first metal element does not contain beryllium.

8. The semiconductor device as described in claim 1, wherein the active region comprises AlGaInAs, InGaAsP, AlGaAsP, or AlGaInP.

9. The semiconductor element as described in claim 1, wherein the contact layer and the active region do not overlap in the vertical direction.

10. The semiconductor element as described in claim 1, wherein the contact layer has a thickness greater than 0 nm and less than or equal to 20 nm.

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