Test structure, semiconductor device and method for forming the same

Abstract

A semiconductor device includes a memory region of a memory cell array and a test region including a test memory cell structure. The test memory cell structure includes a first gate stack on a first protrusion of a substrate, a first polysilicon structure adjacent to the first protrusion and in a region between the first protrusion and a second protrusion of the substrate, a first spacer adjacent to the first polysilicon structure, and a second gate stack on a second protrusion, a second polysilicon structure adjacent to the second protrusion and in a region between the first protrusion and the second protrusion, and a second spacer adjacent to the second polysilicon structure. The semiconductor device includes an interlayer dielectric layer over at least a portion of the memory region and at least a portion of the test region.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] Flash memory elements are a type of non-volatile electronic computer storage medium that can be electrically programmed, read, and erased. For storing information, flash memory elements comprise addressable arrays of flash memory cell elements, typically formed from floating-gate transistors. Common types of flash memory cell elements include split-gate flash memory cell elements and stacked-gate flash memory cell elements. [Summary of the Invention]

[0003] None

Implementation Method

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, the formation of a first feature on or above a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "below," "lower part," "above," and "upper part" may be used herein to describe the relationship between one element or feature and another element(s), as shown in the figures. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0007] An array of memory cell elements, such as a split-gate flash memory cell array, is formed in the memory region of a semiconductor substrate, and logic elements (e.g., elements supporting the operation of the split-gate flash memory cell array) are formed in a (separate) logic region of the semiconductor substrate. Typically, contacts with the split-gate flash memory cell elements extend through an interlayer dielectric (ILD) layer formed above the memory region and the logic region.

[0008] In a memory cell array (e.g., a split-gate flash memory cell array), a region exists between a given pair of adjacent memory cells (e.g., between spacers on the word line polysilicon structure of a given pair of adjacent memory cells). However, as the size of the memory cells decreases, the width of this region decreases, meaning the aspect ratio (e.g., height-to-width ratio) of the region increases. The reduced width of the region (i.e., the increased aspect ratio) adversely affects the gap-filling performance of the ILD layer within the region, meaning that voids may exist in the ILD layer within the region when the ILD layer is formed over the memory region. Therefore, the aspect ratio of the region will determine whether voids will form during subsequent semiconductor processing operations. It should be noted that voids in the ILD layer within the region may adversely affect the formation of contacts later formed via the region (e.g., after etching the ILD layer). The presence of voids reduces wafer yield and increases wafer scrap.

[0009] Furthermore, the thickness of the backside anti-reflective coating (BARC) layer deposited during the formation of memory cell elements affects the width of the region between a given pair of adjacent memory cell elements. Typically, the BARC layer is deposited using a spin-coating process. However, due to the surface shape of the memory cell elements, the spin-coating of the BARC layer used during the fabrication of the memory cell element array can result in uneven BARC layer thickness between the memory cell elements. For example, the surface shape of the memory cell elements may result in a thicker BARC layer closer to the wafer center than a thicker BARC layer closer to the wafer edge. The resulting variation in BARC layer thickness affects the etching of the polysilicon layer used to form the word line structure of the memory cell elements, and therefore means that the width of the region between memory cell elements may vary between them. A given semiconductor element on a wafer comprises several (e.g., thousands or millions) memory cell structures, meaning that monitoring the memory cell topology and / or void ratio is impractical or impossible.

[0010] Some embodiments described herein provide techniques and apparatus for monitoring gaps and surface shapes in flash memory devices, including test memory cell structures. In some embodiments, the semiconductor device may include a memory region comprising an array of memory cell elements and a test region comprising a test memory cell structure. In some embodiments, the test memory cell structure includes a first gate stack on a first protrusion of a substrate, a first polysilicon structure adjacent to the first protrusion and in a region between the first and second protrusions of the substrate, and a first spacer adjacent to the first polysilicon structure in the region between the first and second protrusions. The test memory cell structure may further include a second gate stack on a second protrusion, a second polysilicon structure adjacent to the second protrusion and in a region between the first and second protrusions, and a second spacer adjacent to the second polysilicon structure in the region between the first and second protrusions. The test memory cell structure may further include an ILD layer over at least a portion of the memory region and at least a portion of the test region.

[0011] In some embodiments, the test memory cell structure described herein enables monitoring of the gaps and surface shapes of an array of memory cell elements in a semiconductor device. For example, in some embodiments, the test memory cell structure is formed such that the aspect ratio of the region between the gate stacks of the test memory cell structure is matched to or greater than the "worst-case" aspect ratio of the region between the gate stacks of the memory cell elements in the array. Therefore, the regions formed in the test memory cell structure can be used for gap and surface shape monitoring to, for example, determine the performance of the BARC layer deposition and / or whether the regions between the memory cell elements are formed according to specifications (e.g., such that the ILD gap filling performance is acceptable). That is, the test memory cell structure can be monitored to determine whether one or more structures or layers are properly formed in the memory cell elements and / or whether there are gaps in the regions between the memory cell elements of the semiconductor device (e.g., without monitoring the memory cell elements themselves). In some embodiments, the test memory cell structure can be used to increase yield. Furthermore, monitoring of gaps and surface shapes achieved by testing memory cell structures can improve cycle time associated with manufacturing semiconductor devices (e.g., by reducing the amount of time spent performing over-etching and the amount of time spent performing gap and surface shape monitoring).

[0012] Figure 1 is a diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Example environment 100 includes semiconductor processing tools that can be used to form semiconductor elements and structures, such as the semiconductor elements and test memory cell structures described herein.

[0013] As shown in Figure 1, environment 100 may include a plurality of semiconductor processing tools 102-114 and wafer / die handling elements 116. The plurality of semiconductor processing tools 102-114 may include deposition tools 102, exposure tools 104, developing tools 106, etching tools 108, removal tools 110, planarization tools 112, implantation tools 114, and / or other types of semiconductor processing tools. The tools included in example environment 100 may be found in semiconductor cleanrooms, semiconductor factories, semiconductor processing and / or manufacturing facilities, etc.

[0014] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more elements capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin-coating tool capable of depositing a photoresist layer, an anti-reflective coating, or another type of layer on a substrate such as a wafer. In some embodiments, the deposition tool 102 may deposit metallic materials to form one or more conductors or conductive layers, may deposit insulating materials to form dielectric or insulating layers, and so on, as described herein. In some embodiments, the deposition tool 102 includes chemical vapor deposition (CVD) tools, such as plasma-enhanced CVD (PECVD) tools, high-density plasma CVD (HDP-CVD) tools, sub-atmospheric CVD (SACVD) tools, plasma-enhanced atomic layer deposition (PEALD) tools, or other types of CVD tools. In some implementations, the deposition tool 102 includes physical vapor deposition (PVD) tools, such as sputtering tools or another type of PVD tool. In some implementations, instance environment 100 includes multiple types of deposition tools 102.

[0015] Exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., deep ultraviolet light source, far ultraviolet light source, and / or etc.), an X-ray source, etc. Exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor element layer patterns for forming one or more semiconductor elements, patterns for forming one or more structures of semiconductor elements, patterns for etching various portions of semiconductor elements, etc. In some embodiments, exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0016] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer exposed to a radiation source to develop a pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by using a chemical developer to dissolve the exposed or unexposed portions of the photoresist layer.

[0017] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials, including substrates, wafers, or semiconductor devices. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and so on. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using ionized gas to etch one or more portions locally or directionally.

[0018] The removal tool 110 is a semiconductor processing tool that can remove a portion of a layer deposited on a substrate, such as a photoresist layer, an anti-reflective coating, etc. For example, the removal tool 110 can remove one or more portions of the photoresist layer after the etching tool 108 etches the substrate with the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0019] The planarization tool 112 is a semiconductor processing tool capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, the polishing element may include a chemical mechanical polishing (CMP) element and / or another type of polishing element. In some embodiments, the polishing element may polish or planarize a deposited or electroplated material layer. The CMP process may include depositing a slurry (or polishing compound) onto a polishing pad. The wafer may be mounted on a carrier, which may rotate the wafer when it is pressed against the polishing pad. The slurry and polishing pad act as abrasives, polishing or planarizing one or more layers of the wafer as the wafer rotates. The polishing pad may also be rotated to ensure that a continuous supply of slurry is applied to the polishing pad.

[0020] The implantation tool 114 is a semiconductor processing tool capable of implanting ions into a substrate of a semiconductor wafer. In some embodiments, the implantation tool 114 generates ions from a source material, such as a gas or solid, in an arc chamber. The source material is provided to the arc chamber, and an arc voltage is released between the cathode and the electrode to generate a plasma containing ions from the source material. One or more extraction electrodes are used to extract ions from the plasma in the arc chamber and to accelerate the ions to form an ion beam.

[0021] The wafer / die handling element 116 includes a mobile robot, robotic arm, tram or railcar, and / or another type of element for handling wafers and / or dies and / or transporting wafers and / or dies between semiconductor processing tools 102-114 and / or to and from other locations such as wafer racks, storage rooms, etc. In some embodiments, the wafer / die handling element 116 may be a programmed element that travels along a specific path, and / or may operate semi-autonomously or autonomously.

[0022] The number and configuration of the elements shown in Figure 1 are provided as one or more instances. In practice, there may be additional elements, fewer elements, different elements, or elements with different configurations compared to those shown in Figure 1. Furthermore, two or more elements shown in Figure 1 may be implemented in a single element, or a single element shown in Figure 1 may be implemented as multiple distributed elements. Alternatively or additionally, a group of elements of environment 100 (e.g., one or more elements) may perform one or more functions described as being performed by another group of elements of environment 100.

[0023] Figure 2 is a diagram of an example semiconductor element 200 described herein. Semiconductor element 200 includes an example of a semiconductor element comprising a test memory cell structure for monitoring gaps and surface shapes, as described herein.

[0024] As shown in Figure 2, the semiconductor device 200 includes a memory region 202 and one or more test regions 204. In some embodiments, the semiconductor device 200 is one of a plurality of semiconductor devices 200 on a wafer (not shown). The memory region 202 is a region of the semiconductor device 200 in which an array of memory cell elements (e.g., a split-gate flash memory cell array) is formed. The test region 204 is a region of the semiconductor device 200 in which one or more test memory cell structures (e.g., test memory cell structure 300, described below with reference to Figure 3) are formed. In some embodiments, the test region 204 is outside the shallow trench isolation (STI) region of the semiconductor device 200. That is, one or more test regions 204 are disposed outside the region of the semiconductor device 200 in which one or more STI structures are formed.

[0025] In some embodiments, the semiconductor device 200 includes a plurality of test regions 204, each test region including one or more test memory cell structures (e.g., an array of test memory cell structures). In some embodiments, the test regions 204 are configured around the memory region 202. For example, as shown in Figure 2, in some embodiments, the test regions 204 may be configured in different corners or edges of the semiconductor device 200. The configuration of the test regions 204 around the memory region 202 (e.g., at different corners or edges of the semiconductor device 200) enables void and surface shape monitoring, regardless of the location of the semiconductor device 200 on the wafer. That is, the configuration of the test regions 204 around the memory region 202 ensures that the most significant deviation in the BARC deposition thickness present in the semiconductor device 200 (due to spin coating of the BARC layer) occurs in the test regions 204 of the semiconductor device 200 (e.g., such that the thickness of the BARC layer in a region of the semiconductor device 200 will be the largest among the test regions 204). This means that the region of semiconductor element 200 most significantly affected by the change in BARC layer thickness will appear in the test memory cell structure of one of the test regions 204.

[0026] As indicated above, Figure 2 is provided as an example. Other examples may differ from those described with respect to Figure 2. The number and configuration of memory areas 202 and test areas 204 shown in Figure 2 are provided as examples. In practice, there may be additional memory areas 202 and / or test areas 204, fewer memory areas 202 and / or test areas 204, or different configurations of memory areas 202 and / or test areas 204 compared to those shown in Figure 2.

[0027] Figure 3 is a diagram of the example test memory cell structure 300 described herein. The test memory cell structure 300 includes an example of a test memory cell structure for implementing gap and surface shape monitoring, as described herein.

[0028] As shown in Figure 3, the test memory cell structure 300 (more generally referred to as the test structure) includes a substrate 302 and a pair of gate stacks 303 (e.g., gate stack 303a, gate stack 303b) disposed on a protrusion of the substrate 302. As shown, each gate stack 303 includes a dielectric region 304, a polysilicon region 306, a masking region 308, and a dielectric pad 310. As further shown, the test memory cell structure 300 further includes a polysilicon structure 312 adjacent to the protrusion of the substrate 302 and the gate stack 303 (e.g., in a recess of the substrate 302) and spacers 314 adjacent to the polysilicon structure 312. As further shown, the test memory cell structure 300 includes an ILD layer 316, gate stacks 303, polysilicon structure 312, spacers 314, and a substrate 302 between the spacers 314.

[0029] The substrate 302 is a semiconductor die substrate, a semiconductor wafer, or another type of substrate, wherein one or more semiconductor elements, such as a split-gate flash memory cell array, a stacked gate flash memory cell array, etc., can be formed. In some embodiments, the substrate 302 is formed of silicon, a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon-on-insulator (SOI), or another type of semiconductor material.

[0030] As described above, the gate stack 303 (more generally referred to as a layer stack) includes a dielectric region 304, a polysilicon region 306, a masking region 308, and a dielectric pad 310. The dielectric region 304 and the polysilicon region 306 are disposed above the protrusion of the substrate 302, with the dielectric region 304 located between the protrusion of the substrate 302 and the polysilicon region 306. The dielectric region 304 may be, for example, an oxide-nitride-oxide (ONO) film, such as silicon oxide-silicon nitride-oxide, another type of multilayer film, or another type of dielectric material. The polysilicon region 306 may be, for example, doped polysilicon or another type of conductive material. The masking region 308 may be disposed above the polycrystalline silicon region 306 and may be formed of, for example, a nitride-oxide-nitride (NON) film, such as silicon nitride-silicon oxide-silicon nitride, another type of multilayer film, or another type of dielectric material.

[0031] As shown in the figure, the dielectric pad 310 corresponding to the gate stack 303 extends from the protruding portion of the substrate 302 to line the dielectric region 304, the polysilicon region 306, and the masking region 308. For example, the dielectric pad 310 is lining the sidewalls of the dielectric region 304, the polysilicon region 306, and the masking region 308. In some embodiments, as shown in the figure, the dielectric pad 310 may be lining the top surface of the masking region 308. In some embodiments, the dielectric pad 310 is, for example, an ONO film or another type of dielectric material.

[0032] As further shown, the polysilicon structure 312 corresponding to the gate stack 303 is configured adjacent to the corresponding gate stack 303. Each gate stack 303 is associated with a corresponding pair of polysilicon structures 312 (e.g., each gate stack 303 is located between a corresponding pair of adjacent polysilicon structures 312), as shown in Figure 3. It should be noted that, as shown in Figure 3, the polysilicon structure 312 is configured in the region between the protrusions of the substrate 302 in the test memory cell structure 300. The polysilicon structure 312 may be formed of, for example, doped polysilicon or another type of conductive material. As further shown, spacers 314 are configured along the sidewalls of the polysilicon structure 312. The spacers 314 may be formed of, for example, silicon dioxide, silicon nitride or another type of dielectric material. In some implementations, the polycrystalline silicon structure 312 and the spacer 314 are formed in the region between the protrusions of the substrate 302, rather than on opposite sides of the gate stack 303.

[0033] ILD layer 316 is a film, layer, or material that provides electrical isolation between a metal layer, a conductive layer, or adjacent semiconductor elements. ILD layer 316 may include a low-k material, such as a material having a dielectric constant of 3.9 or less. Examples of materials that can be used for ILD layers include silicon dioxide, fluorinated silicon dioxide (also known as fluorinated silica glass or fluorosilicate glass), or carbon-doped silicon dioxide (also known as organosilicon glass).

[0034] In some embodiments, the spacing p between gate stacks 303a and 303b can define the aspect ratio (i.e., height-to-width ratio) of the region 318 between adjacent spacers 314 of the test memory cell structure 300. That is, the distance between gate stacks 303a and 303b can be defined by controlling the distance between gate stacks 303a and 303b (which affects the aspect ratio of region 318). Therefore, the spacing p can be selected to control the aspect ratio of region 318 such that the aspect ratio of the region between spacers 314 matches or is greater than the maximum aspect ratio of the region between adjacent spacers in the memory cell elements of memory region 202. For example, in some embodiments, the aspect ratio of region 318 can be in the range of about 6 to about 13. However, other values ​​of the aspect ratio of region 318 are within the range of this disclosure. In some implementations, the spacing p may be less than or equal to about 200 nanometers (nm), such as 200 nm, 190 nm, 180 nm, 170 nm, 160 nm, 150 nm, etc. However, other values ​​of spacing p are within the scope of this disclosure. In some implementations, a given test region 204 includes multiple test memory cell structures 300, and the spacing p between the test memory cell structures 300 of a given test region 204 may vary. Variation of the spacing p between the test memory cell structures 300 may allow regions 318 in different test memory cell structures 300 to have different aspect ratios that can be monitored using a single test region 204.

[0035] It should be noted that some embodiments of the test memory cell structure 300 do not include a floating gate layer. That is, in some embodiments, the gate stacks 303 in the test memory cell structure 300 do not include a floating gate layer. The memory cell elements in the memory region 202 will include a floating gate layer because the operation of the memory cell elements requires a floating gate layer. However, because the test memory cell structure 300 is used for gap and surface shape monitoring (rather than as a memory cell element), the test memory cell structure 300 does not need to include a floating gate layer. In this way, the structure of the test memory cell structure 300 differs from that of a typical memory cell element of the semiconductor device 200. In some embodiments, the floating gate layer is removed from the test region 204 during the formation of the test memory cell structure 300 so that the substrate 302 can be etched in the region between the gate stacks 303 during the floating gate etching in the memory region 202. As shown in the figure, the absence of a floating gate layer in the test area 204 facilitates the simultaneous formation of the test memory cell structure 300 with the memory cell elements in the memory area 202.

[0036] Furthermore, the test memory cell structure 300 includes a protruding portion of the substrate 302 below the gate stack 303. A polysilicon structure 312 is formed in the region between the first protruding portion and the second protruding portion of the substrate 302 (e.g., in a recess in the substrate 302) such that the aspect ratio of the region 318 is greater than the aspect ratio of the region between adjacent spacers in the memory cell elements of the memory region 202, because the substrate 302 does not include the protruding portion 202 in the memory region (e.g., the recess in the substrate 302 does not exist between the memory cell elements in the memory region 202). Therefore, the test memory cell structure 300 can have a greater height than a typical memory cell element, so that the aspect ratio of region 318 (e.g., between the spacer 314 on the right side of gate stack 303a in Figure 3 and the spacer 314 on the left side of gate stack 303b) can be greater than the aspect ratio of the region between the spacers of a pair of adjacent memory cell elements in memory region 202. In this way, the protrusion of substrate 302 allows region 318 to be used to facilitate monitoring of the "worst-case" gaps and surface shapes of the structure or layers in the region between memory cell elements (e.g., without monitoring the memory cell elements themselves).

[0037] The number and configuration of the structures, layers, etc., shown in Figure 3 are provided as examples. In practice, the test memory cell structure 300 may include additional structures and / or layers, fewer structures and / or layers, different structures and / or layers, and / or structures and / or layers with different configurations than those shown in Figure 3. That is, as described above, Figure 3 is provided as an example, and other examples may differ from those described with respect to Figure 3.

[0038] Figures 4A to 4S are diagrams illustrating an example embodiment 400 of forming the test memory cell structure 300 described herein. Figures 4A to 4S illustrate the formation of the test memory cell structure 300 in the test region 204. In some embodiments, the test memory cell structure 300 may be formed simultaneously with the formation of the memory cell element array in the memory region 202 (e.g., using the same sequence of semiconductor processing steps).

[0039] As shown in Figure 4A, a substrate 302 is provided. In some embodiments, the substrate 302 is a substrate on which one or more semiconductor elements 200 (including one or more test regions 204 and memory regions 202) will be formed.

[0040] As shown in Figure 4B, Example 400 may include forming a floating gate layer 402 on a substrate 302. In some embodiments, a deposition tool 102 may deposit the floating gate layer 402 on the substrate 302. The deposition tool 102 may deposit the floating gate layer 402 in association with the floating gate forming a memory cell element in a memory region 202 of a semiconductor device 200 (not shown). In some embodiments, a planarization tool (e.g., planarization tool 112) may polish and / or planarize the floating gate layer 402.

[0041] As shown in Figure 4C, Example 400 may include removing the floating gate layer 402 from the substrate 302 in the test region 204. In some embodiments, the floating gate layer 402 is removed from the test region 204 of the semiconductor device 200, and a portion of the floating gate layer 402 may remain within the memory region 202 (e.g., the floating gate layer 402 may be etched to form a floating gate for memory cell elements in the memory region 202). In some embodiments, to remove the floating gate layer 402, the deposition tool 102 may deposit a photoresist layer on the floating gate layer 402 (e.g., by spin coating). The exposure tool 104 may form a pattern in the photoresist layer by exposing the photoresist layer to a radiation source, such as a UV source (e.g., a deep UV light source, an extreme UV (EUV) light source, an X-ray source, or an electron beam (e-beam) source), to transfer the pattern from a photomask to the photoresist layer. The developing tool 106 can perform a developing operation, which includes one or more techniques to develop a pattern in the photoresist layer. The etching tool 108 can etch the floating gate layer 402 based on the pattern formed in the photoresist layer to remove the floating gate layer 402 from the test area 204. For example, the etching tool 108 can perform a wet etching technique (e.g., where the floating gate layer 402 is exposed or immersed in chemicals that etch or remove material at a specific etching rate), a dry etching element (e.g., where plasma is used to sputter material), or another type of etching technique. After etching the floating gate layer 402 to remove it, the remaining portion of the photoresist layer can be removed by the removal tool 110. As shown, in Example 400, the floating gate layer 402 is removed from the test area 204 on which the test memory cell structure 300 will be formed.

[0042] As shown in Figure 4D, Example 400 may include forming a dielectric layer 404, a polysilicon layer 406, and a masking layer 408 over a substrate 302. The dielectric layer 404, the polysilicon layer 406, and the masking layer 408 are layers from which the dielectric region 304, the polysilicon region 306, and the masking region 308 of the test memory cell structure 300 are respectively formed in the test region 204. In some embodiments, the deposition tool 102 may deposit the dielectric layer 404 on the substrate 302, deposit the polysilicon layer 406 on the dielectric layer 404, and deposit the masking layer 408 on the polysilicon layer 406. In some implementations, the planarization tool 112 may polish and / or planarize the dielectric layer 404 before depositing the polysilicon layer 406, may polish and / or planarize the polysilicon layer 406 before depositing the masking layer 408, and / or may polish and / or planarize the masking layer 408. In some implementations, the dielectric layer 404, the polysilicon layer 406, and the masking layer 408 are also layers from which the memory cell element structure in the memory region 202 is to be formed.

[0043] As shown in Figure 4E, Example 400 may include forming a photoresist structure 410 on a mask layer 408. In some embodiments, the photoresist structure 410 is used to define the width of the gate stack 303 and the spacing p between the gate stacks 303, as described herein. In some embodiments, to form the photoresist structure 410, a deposition tool 102 may deposit a photoresist layer on the mask layer 408 (e.g., by spin coating). An exposure tool 104 may form a pattern in the photoresist layer by exposing the photoresist layer to a radiation source, such as a UV source (e.g., a deep UV light source, an extreme UV (EUV) light source, etc.), an X-ray source, or an electron beam (e-beam) source, to transfer the pattern from the photomask to the photoresist layer. A development tool 106 may perform a development operation, which includes one or more techniques to develop the pattern in the photoresist layer. In some implementations, the photoresist structure 410 is formed simultaneously with the photoresist structure in the memory region 202 that defines the memory cell elements in the memory region 202.

[0044] As shown in Figure 4F, Example 400 may include removing portions of dielectric layer 404, polysilicon layer 406, and masking layer 408 to form dielectric region 304, polysilicon region 306, and masking region 308. In some embodiments, etching tool 108 may etch dielectric layer 404, polysilicon layer 406, and masking layer 408 based on a pattern formed in the photoresist layer (e.g., a pattern defining photoresist structure 410) to remove portions of dielectric layer 404, polysilicon layer 406, and masking layer 408. For example, etching tool 108 may perform wet etching techniques (e.g., where dielectric layer 404, polysilicon layer 406, and masking layer 408 are exposed or immersed in chemicals that etch or remove material at a specific etching rate), dry etching of elements (e.g., where plasma sputtering materials are used), or other types of etching techniques. After etching the dielectric layer 404, polysilicon layer 406, and masking layer 408 to form the dielectric region 304, polysilicon region 306, and masking region 308, the photoresist structure 410 can be removed by the removal tool 110. In practice, the etching performed by the etching tool 108 is further used to define the structure of the memory cell elements in the memory region 202 using the photoresist structure formed in the memory region 202, as described above.

[0045] As shown in Figure 4G, Example 400 may include forming a dielectric layer 412 on a substrate 302, a dielectric region 304, a polysilicon region 306, and a masking region 308. The dielectric layer 412 is a layer from which a dielectric pad 310 from which a test memory cell structure 300 is to be formed. In some embodiments, a deposition tool (e.g., deposition tool 102) may deposit the dielectric layer 412 on the substrate 302, the dielectric region 304, the polysilicon region 306, and the masking region 308. In some embodiments, the dielectric layer 412 may also be formed in the memory region 202 in association with the dielectric pad from which memory cell elements are formed in the memory region 202.

[0046] As shown in Figure 4H, Example 400 may include the removal of portions of dielectric layer 412 and substrate 302. In some embodiments, the portion of dielectric layer 412 removed forms a gate stack 303, and the portion of substrate 302 removed forms a first protrusion 302 and a second protrusion of substrate 302, on which gate stacks 303a and 303b are respectively disposed. In some embodiments, in order to remove portions of dielectric layer 412 and substrate 302, deposition tool 102 may deposit a photoresist layer on dielectric layer 412 (e.g., by spin coating). Exposure tool 104 may form a pattern in photoresist layer by exposing the photoresist layer to a radiation source, such as a UV source (e.g., a deep UV light source, an extreme UV (EUV) light source, etc.), an X-ray source, or an electron beam source, to transfer the pattern from a photomask to the photoresist layer. The developing tool 106 can perform a developing operation, which includes one or more techniques to develop a pattern in the photoresist layer. The etching tool 108 can etch the dielectric layer 412 and substrate 302 based on the pattern formed in the photoresist layer to remove portions of the dielectric layer 412 and substrate 302. For example, the etching tool 108 can perform wet etching techniques (e.g., where the dielectric layer 412 and substrate 302 are exposed or immersed in chemicals that etch or remove material at a specific etching rate), dry etching of elements (e.g., where plasma sputtering materials are used), or other types of etching techniques. After etching the dielectric layer 412 and substrate 302, the remaining portions of the photoresist layer can be removed by the removal tool 110. In some embodiments, the operation for removing portions of the dielectric layer 412 and substrate 302 can be the same as the operation for removing portions of a floating gate layer and / or one or more other layers from the memory region 202 in association with the structure forming memory cell elements in the memory region 202.

[0047] As shown in Figure 4I, Example 400 may include forming a polysilicon layer 414 on a substrate 302 and a gate stack 303. The polysilicon layer 414 is a layer from which a polysilicon structure 312 is to be formed of a test memory cell structure 300. In some embodiments, a deposition tool (e.g., deposition tool 102) may deposit the polysilicon layer 414 on the substrate 302 and the gate stack 303. In some embodiments, the polysilicon layer 414 may also be formed in the memory region 202 in association with a layer of one or more structures (e.g., word lines, erase gates, etc.) from which memory cell elements are to be formed in the memory region 202.

[0048] As shown in Figure 4J, Example 400 may include forming a BARC layer 415 over at least a portion of the polysilicon layer 414. In some embodiments, the deposition tool 102 may use a spin-coating technique to deposit the BARC layer 415 on the polysilicon layer 414, as described above. In some embodiments, the BARC layer 415 may also be formed in the memory region 202 in association with a layer forming one or more structures (e.g., word lines, erase gates, etc.) to be used to form memory cell elements in the memory region 202. In some embodiments, the topology of the semiconductor element 200 (e.g., in the memory region 202, in the test region 204) may result in a "worst-case" thickness of the BARC layer 415 existing in the test memory cell structure 300 in the test region 204, as described above.

[0049] As shown in Figure 4K, Example 400 may include removing a portion of polysilicon layer 414. In some embodiments, the removal of a portion of polysilicon layer 414 is performed in association with the formation of polysilicon structure 312. For example, etching tool 108 may perform one or more etching operations to remove exposed portions of polysilicon layer 414 (e.g., portions of polysilicon layer 414 not covered by BARC layer 415). Here, BARC layer 415 prevents portions of polysilicon layer 414 (e.g., a portion of polysilicon layer 414 between a first protrusion and a second protrusion of substrate 302) from being removed during one or more etching operations. After etching polysilicon layer 414 to form polysilicon structure 312, removal tool 110 may remove BARC layer 415 from the remaining portion of polysilicon layer 414. In some implementations, the etching or removal operation associated with removing a portion of the polysilicon layer 414 may be the same as the etching or removal operation used to form one or more structures (e.g., word lines, erase gates, etc.) of memory cell elements in memory region 202 from the polysilicon layer 414.

[0050] As shown in Figure 4L, Example 400 may include forming a hard mask 416 over the gate stack 303 and the polysilicon layer 414. The hard mask 416 is a layer used to mask one or more other structures of the test memory cell structure 300 (e.g., portions of the gate stack 303 and the polysilicon layer 414) in association with the formation of the test memory cell structure 300. In some embodiments, the deposition tool 102 may deposit the hard mask 416 over the gate stack 303 and the polysilicon layer 414. In some embodiments, the hard mask 416 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, another nitride, another oxide, or a metallic material. In some implementations, the hard mask 416 may also be formed in the memory region 202 in association with a mask that is associated with forming one or more structures (e.g., word lines, erase gates, etc.) of the memory cell elements in the memory region 202.

[0051] As shown in Figure 4M, Example 400 may include forming a BARC layer 418 over a rigid mask 416 and a photoresist layer 420 over the BARC layer 418. The BARC layer 418 is used to prevent radiation used for patterning the photoresist layer 420 from being reflected by the underlying layer of the semiconductor element 200 (e.g., to improve the quality of etching performed using the patterned photoresist layer 420). In some embodiments, the deposition tool 102 may use a spin coating technique to deposit the BARC layer 418 on the rigid mask 416, as described above. In some embodiments, the BARC layer 418 and the photoresist layer 420 may also be formed in the memory region 202 in association with a layer forming one or more structures (e.g., word lines, erase gates, etc.) to be used to form memory cell elements in the memory region 202. In some implementations, the topology of semiconductor element 200 (e.g., in memory region 202, in test region 204) may cause the "worst-case" thickness of BARC layer 418 to appear in test memory cell structure 300 in test region 204, as described above.

[0052] As shown in Figure 4N, Example 400 may include forming an opening 422 in a rigid mask 416. In some embodiments, the opening 422 defines the width of a region between the polysilicon structures 312 of the test memory cell structure 300. In some embodiments, the exposure tool 104 may form a pattern in the photoresist layer 420 by exposing the photoresist layer 420 to a radiation source, such as a UV source (e.g., a deep UV light source, an extreme UV (EUV) light source, etc.), an X-ray source, or an electron beam source, to transfer the pattern from the photomask to the photoresist layer. Here, the BARC layer 418 is used to prevent radiation from reflecting off the underlying layers of the memory cell structure 300 under test. The developing tool 106 may perform a developing operation including one or more techniques to develop the pattern in the photoresist layer 420. Etching tool 108 can etch the BARC layer 418 and hard mask 416 based on a pattern formed in the photoresist layer 420 to remove portions of the hard mask 416 to form an opening 422. For example, etching tool 108 can perform wet etching techniques (e.g., exposing or immersing the BARC layer 418 and hard mask 416 in chemicals that etch or remove material at a specific etching rate), dry etching of the element (e.g., where plasma sputtering materials are used), or other types of etching techniques. In some implementations, the operation for forming the opening 422 can be the same as the operation for forming an opening in the hard mask 416 associated with one or more structures (e.g., word lines, erase gates, etc.) defining memory cell elements in memory region 202.

[0053] As shown in Figure 40, Example 400 may include forming a polysilicon structure 312 from a polysilicon layer 414. In some embodiments, the width of the polysilicon structure 312 is defined by the width of the opening 422 in the rigid mask 416. In some embodiments, etching tool 108 may etch the polysilicon layer 414 based on a pattern formed in the photoresist layer 420 to remove a portion of the polysilicon layer 414 to form the opening 422. For example, etching tool 108 may perform wet etching techniques (e.g., where the polysilicon layer 414 is exposed or immersed in chemicals that etch or remove material at a specific etching rate), dry etching of elements (e.g., where plasma is used to sputter material), or another type of etching technique. After etching the polysilicon layer 414 to form the polysilicon structure 312, the remaining portion of the BARC layer 418 and the photoresist layer 420 may be removed by removal tool 110. In some implementations, the operation for etching the polysilicon layer 414 may be the same as the operation for defining one or more structures (e.g., word lines) of memory cell elements in memory region 202.

[0054] As shown in Figure 4P, Example 400 may include removing a hard mask 416 from the gate stack 303 and the polysilicon structure 312. For example, removal tool 110 may remove the remainder of the hard mask 416 from the gate stack 303 and the polysilicon structure 312 after the polysilicon structure 312 has been formed. In some embodiments, the operation for removing the hard mask 416 may be the same operation as the operation for removing the hard mask 416 from one or more structures of memory cell elements in memory region 202.

[0055] As shown in Figure 4Q, Example 400 may include the formation of spacers 314 adjacent to the polycrystalline silicon structure 312. For example, deposition tool 102 may deposit a conformal spacer layer (e.g., the layer to be formed along the polycrystalline silicon structure 312 to create spacers 314). In some embodiments, to form spacer layers 314 from the conformal spacer layer, deposition tool 102 may deposit photoresist layers between and over the polycrystalline silicon structure 312, and exposure tool 104 may form a pattern in the photoresist layer by exposing the photoresist layer to a radiation source, such as a UV source (e.g., a deep UV source, an extreme UV (EUV) source, etc.), an X-ray source, or an e-beam source, to transfer the pattern from a photomask to the photoresist layer. Development tool 106 may perform a development operation, which includes one or more techniques to develop the pattern in the photoresist layer. Etching tool 108 may then etch a conformal spacer layer based on a pattern formed in the photoresist layer to form spacer 314. Removal tool 110 may then remove the remaining portion of the photoresist layer. In some embodiments, the operation for forming spacer 314 may be the same as the operation for forming spacers for memory cell elements in memory region 202.

[0056] As shown in Figure 4R, Example 400 may include forming an ILD layer 316 over a test memory cell structure 300. In some embodiments, a deposition tool 102 may deposit the ILD layer 316 of the test memory cell structure 300. In some embodiments, a planarization tool 112 may polish and / or planarize the ILD layer 316. In some embodiments, the deposition operation for forming the ILD layer 316 may be the same as the deposition operation for forming an ILD layer over a memory cell element in the memory region 202.

[0057] As shown in Figure 4R, an ILD layer 316 is formed in a region 318 between adjacent spacers 314 of gate stacks 303a and 303b. In some embodiments, as shown, region 318 extends from the surface of ILD layer 316 to or near the region between gate stacks 303 (i.e., the region between the first protrusion of substrate 302 and the second protrusion of substrate 302). In some embodiments, the gap-filling performance of ILD layer 316 in a portion of region 318 between adjacent spacers 314 can be monitored to evaluate the gap-filling performance of semiconductor device 200. For example, region 318 may be used to have an aspect ratio that matches or is greater than the aspect ratio of the corresponding region between adjacent memory cell elements in memory region 202. Therefore, the gap-filling performance in region 318 can be monitored to assess whether gaps may exist in the corresponding region between adjacent memory cell elements in memory region 202.

[0058] As shown in Figure 4S, Example 400 may include forming a recess 424 in region 318. In some embodiments, to form the recess 424, deposition tool 102 may deposit a photoresist layer on ILD layer 316 (e.g., by spin coating). Exposure tool 104 may form a pattern in the photoresist layer by exposing the photoresist layer to a radiation source, such as a UV source (e.g., a deep UV light source, an extreme UV (EUV) light source, etc.), an X-ray source, or an electron beam source, to transfer the pattern from a photomask to the photoresist layer. Development tool 106 may perform a development operation, which includes one or more techniques to develop the pattern in the photoresist layer. Etching tool 108 may etch ILD layer 316 based on the pattern formed in the photoresist layer to form the recess 424. For example, etching tool 108 can perform wet etching techniques (e.g., where the ILD layer 316 is exposed or immersed in chemicals that etch or remove material at a specific etching rate), dry etching of the element (e.g., where plasma is used to sputter the material), or another type of etching technique. After etching the ILD layer 316, the remaining portion of the photoresist layer can be removed by removal tool 110. In some embodiments, the operation for forming the recess 424 can be the same as the operation for forming contact etching through the ILD layer 316 in the memory region 202 in association with contact plugs formed in the memory cell elements in the memory region 202. Therefore, in some embodiments, the recess 424 (and its subsequent filling) can be used in association with monitoring the formation of contact plugs for the memory cell elements in the memory region 202.

[0059] As described above, Figures 4A to 4S are provided as examples. Other examples may differ from those described with respect to Figures 4A to 4S.

[0060] Figure 5 is a diagram of an example assembly of element 500, which may correspond to deposition tool 102, exposure tool 104, developing tool 106, etching tool 108, removal tool 110, planarization tool 112, implantation tool 114, and / or wafer / die processing element 116. In some embodiments, deposition tool 102, exposure tool 104, developing tool 106, etching tool 108, removal tool 110, planarization tool 112, implantation tool 114, and / or wafer / die processing element 116 may include one or more elements 500 and / or one or more components of element 500. As shown in Figure 5, element 500 may include bus 510, processor 520, memory 530, storage component 540, input component 550, output component 560, and communication component 570.

[0061] Bus 510 includes components for wired and / or wireless communication between the components of implementing element 500. Processor 520 includes a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuit, and / or other types of processing components. Processor 520 is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor 520 includes one or more processors that can be programmed to perform functions. Memory 530 includes random access memory, read-only memory, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory).

[0062] Storage component 540 stores information and / or software related to the operation of component 500. For example, storage component 540 may include a hard disk drive, disk drive, optical disk drive, solid-state disk drive, optical disc, digital multifunction disk, and / or another type of non-transitory computer-readable media. Input component 550 enables component 500 to receive input, such as user input and / or sensed input. For example, input component 550 may include a touch screen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS component, accelerometer, gyroscope, and / or actuator. Output component 560 enables component 500 to provide output, such as via a display, speaker, and / or one or more light-emitting diodes. Communication component 570 enables component 500 to communicate with other components, for example via wired and / or wireless connections. For example, communication component 570 may include a receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0063] Element 500 may perform one or more processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 530 and / or storage component 540) may store a set of instructions (e.g., one or more instructions, program code, software code, and / or program code) for execution by processor 520. Processor 520 may execute the set of instructions to perform one or more processes described herein. In some embodiments, one or more processors 520 execute a set of instructions to cause one or more processors 520 and / or element 500 to perform one or more processes described herein. In some embodiments, hard-wired circuitry may be used in place of or in combination with instructions to perform one or more processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuitry and software.

[0064] The number and configuration of components shown in Figure 5 are provided as examples. Component 500 may include additional components, fewer components, different components, or components with different configurations compared to those shown in Figure 5. Alternatively or additionally, a set of components of component 500 (e.g., one or more components) may perform one or more functions described as being performed by another set of components of component 500.

[0065] Figure 6 is a flowchart of an example process 600 related to forming a test memory cell structure for monitoring gaps and surface shapes. In some implementations, one or more processing blocks of Figure 6 may be executed by one or more semiconductor processing tools (e.g., one or more semiconductor processing tools 102-116). Alternatively, one or more processing blocks of Figure 6 may be executed by one or more components of element 500, such as processor 520, memory 530, storage component 540, input component 550, output component 560, and / or communication component 570.

[0066] As shown in Figure 6, process 600 may include forming a first gate stack and a second gate stack on a substrate (block 610). For example, one or more semiconductor processing tools may form a first gate stack (e.g., gate stack 303a) and a second gate stack (e.g., gate stack 303b) on a substrate (e.g., substrate 302), as described above.

[0067] As further shown in Figure 6, process 600 may include removing a portion of the substrate in the region between the first gate stack and the second gate stack to form a recessed portion in the substrate in the region between the first gate stack and the second gate stack (block 620). For example, one or more semiconductor processing tools may remove a portion of the substrate in the region between the first gate stack and the second gate stack to form a recessed portion in the substrate in the region between the first gate stack and the second gate stack, as described above.

[0068] As further shown in Figure 6, process 600 may include forming a polysilicon layer (block 630) on the first gate stack, the second gate stack, and in recesses in the substrate. For example, one or more semiconductor processing tools may form a polysilicon layer (e.g., polysilicon layer 414) on the first gate stack, the second gate stack, and in recesses in the substrate, as described above.

[0069] As further shown in Figure 6, process 600 may include forming a recessed portion (block 640) in a polysilicon layer in a region between the first gate stack and the second gate stack. For example, one or more semiconductor processing tools may form the recessed portion in a polysilicon layer in a region between the first gate stack and the second gate stack, as described above.

[0070] As further shown in Figure 6, process 600 may include forming a first spacer (block 650) adjacent to a first remaining portion of the polysilicon layer. For example, one or more semiconductor processing tools may form a first spacer (e.g., spacer 314) adjacent to the first remaining portion of the polysilicon layer, as described above.

[0071] As further shown in Figure 6, process 600 may include forming a second spacer (block 660) adjacent to a second remaining portion of the polysilicon layer. For example, one or more semiconductor processing tools may form a second spacer (e.g., spacer 314) adjacent to a second remaining portion of the polysilicon layer, as described above.

[0072] As further shown in Figure 6, process 600 may include forming an ILD layer (block 670) over the first gate stack, over the second gate stack, and in the region between the first gate stack and the second gate stack. For example, one or more semiconductor processing tools may form an ILD layer (e.g., ILD layer 316) over the first gate stack, over the second gate stack, and in the region between the first gate stack and the second gate stack, as described above.

[0073] Process 600 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or described elsewhere herein.

[0074] In a first embodiment, process 600 includes removing a floating gate layer (e.g., floating gate layer 402) from the substrate before forming the first gate stack and the second gate stack.

[0075] In the second embodiment, either alone or in combination with the first embodiment, the first gate stack and the second gate stack are formed in a test area (e.g., test area 204) of the substrate, and the test area is separate from the memory area (e.g., memory area 202) in which an array of memory cell elements is formed.

[0076] In the third embodiment, the test area is one of a plurality of test areas, which are configured around the memory area, either alone or in combination with either the first or second embodiment.

[0077] In the fourth embodiment, either alone or in combination with any of the first to third embodiments, the spacing between the first gate stack and the second gate stack is different from the spacing between the third gate stack and the fourth gate stack in the test area.

[0078] In the fifth embodiment, either alone or in combination with any of the first to fourth embodiments, the aspect ratio of the region between the first spacer and the second spacer is greater than the aspect ratio of the region between the spacers of a pair of adjacent memory cell elements in the memory cell element array.

[0079] In the sixth embodiment, alone or in combination with any of the first to fifth embodiments, process 600 includes forming a recess (e.g., recess 424) in the ILD layer in the region between the first spacer and the second spacer, the recess extending from the surface of the ILD layer to the substrate.

[0080] Although Figure 6 shows an example block of process 600, in some implementations, process 600 may include additional blocks, fewer blocks, different blocks, or blocks with different configurations compared to those depicted in Figure 6. Alternatively, two or more blocks of process 600 may be executed in parallel.

[0081] In this manner, the test memory cell structure 300 can be used to monitor the voids and surface shapes in the semiconductor element 200 (e.g., a flash memory element). For example, in some embodiments, the test memory cell structure 300 configured in the test region 204 is formed such that the aspect ratio of the region 318 between the gate stacks 303 of the test memory cell structure 300 is matched to or greater than the "worst-case" aspect ratio of the region between the gate stacks of the memory cell elements in the memory region 202. Therefore, the region 318 formed in the test memory cell structure 300 can be used for void and surface shape monitoring, for example, to determine whether the performance of the BARC layer deposition and / or whether the regions between the memory cell elements in the memory region 202 are formed according to specifications (e.g., such that the gap filling performance of the ILD layer 316 is acceptable). That is, the memory cell structure 300 can be monitored to determine whether one or more structures or layers are properly formed in the memory cell elements and / or whether there are gaps in the area between the memory cell elements of the semiconductor device 200 (e.g., without monitoring the memory cell elements themselves). In some implementations, testing the memory cell structure can be used to increase yield and / or improve the cycle time associated with manufacturing the semiconductor device 200 (e.g., by reducing the amount of time used to perform over-etching).

[0082] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a memory region comprising an array of memory cell elements. The semiconductor device includes a test region comprising a test memory cell structure, the test memory cell structure including a first gate stack on a first protrusion of a substrate, a first polysilicon structure adjacent to the first protrusion and in a region between the first and second protrusions of the substrate, a first spacer adjacent to the first polysilicon structure in the region between the first and second protrusions, and a second gate stack on a second protrusion, a second polysilicon structure adjacent to the second protrusion and in a region between the first and second protrusions, and a second spacer adjacent to the second polysilicon structure in the region between the first and second protrusions. The semiconductor device includes an interlayer dielectric layer located above at least a portion of the memory region and at least a portion of the test region. In some embodiments, a floating gate layer is not present in the first or second gate stack. In some embodiments, the aspect ratio of a region between the first spacer and the second spacer is greater than the aspect ratio of a region between the spacers of a pair of adjacent memory cell elements in the memory cell element array. In some embodiments, the test region is one of a plurality of test regions of a semiconductor element, each of the plurality of test regions including one or more test memory cell structures. In some embodiments, each of the plurality of test regions is disposed at or near a different corner of the semiconductor element. In some embodiments, the test memory cell structure is one of a plurality of test memory cell structures in the test region. In some embodiments, a spacing between the first gate stack and the second gate stack is different from a spacing between a pair of gate stacks included in another of the plurality of test memory cell structures.

[0083] As described in more detail above, some embodiments described herein provide a method. The method includes forming a first gate stack and a second gate stack on a substrate. The method includes removing a portion of a region of the substrate located between the first gate stack and the second gate stack to form a recessed portion in the substrate within the region between the first gate stack and the second gate stack. The method includes forming a polysilicon layer on the first gate stack, on the second gate stack, and in the recessed portion of the substrate. The method includes forming a recessed portion in the polysilicon layer within the region between the first gate stack and the second gate stack. The method includes forming a first spacer adjacent to a first remaining portion of the polysilicon layer. The method includes forming a second spacer adjacent to a second remaining portion of the polysilicon layer. The method includes forming an interlayer dielectric layer over the first gate stack, over the second gate stack, and in the region between the first gate stack and the second gate stack. In some embodiments, the method further includes the step of removing a floating gate layer from the substrate before forming the first gate stack and the second gate stack. In some embodiments, the first gate stack and the second gate stack are formed in a test region of the substrate, the test region being separated from a memory in which a memory cell array is formed. In some embodiments, the test region is one of a plurality of test regions disposed around the memory region. In some embodiments, a spacing between the first gate stack and the second gate stack is different from a spacing between a third gate stack and a fourth gate stack in the test region. In some embodiments, an aspect ratio of a region between the first spacer and the second spacer is greater than an aspect ratio of a region between spacers of a pair of adjacent memory cell elements in the memory cell array. In some embodiments, the method further includes the step of forming a recess in the ILD layer in the region between the first spacer and the second spacer, the recess extending from a surface of the ILD layer to the substrate.

[0084] As described in more detail above, some embodiments described herein provide a test structure. The test structure includes a substrate having a first raised portion and a second raised portion. The test structure includes a first layer stack on the first raised portion. The test structure includes a second layer stack on the second raised portion. The test structure includes one or more first structures located on the side of the first raised portion closest to the second raised portion. The test structure includes one or more second structures located on the side of the second raised portion closest to the first raised portion. The test structure includes a dielectric layer above the first layer stack, above the second layer stack, above the one or more first structures, above the one or more second structures, and in a region between the one or more first structures and the one or more second structures. In some embodiments, an aspect ratio of the region between the one or more first structures and the one or more second structures is used to enable void monitoring of a plurality of other structures formed on the substrate. In some embodiments, the test structure is located in a test area of ​​the substrate, the test area being one of a plurality of test areas of the substrate. In some embodiments, each of the plurality of test regions is disposed at or near a different corner of a semiconductor device. In some embodiments, the test structure is one of a plurality of test structures in a test region of a substrate. In some embodiments, a distance between a first stack and a second stack is different from a distance between a pair of stacks included in another test structure of the plurality of test structures in the test region.

[0085] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] The nature of this disclosure can be best understood in conjunction with the accompanying drawings, based on the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 is a diagram of an example environment in which the system and / or method described herein may be implemented. Figure 2 is a diagram of an example semiconductor element described herein. Figure 3 is a diagram of an example semiconductor structure described herein. Figures 4A through 4S are diagrams of example implementations described herein. Figure 5 is a diagram of an example assembly of one or more elements of Figure 1. Figure 6 is a flowchart of an example process related to forming a test structure for monitoring voids and surface shapes. [Biomaterial Storage]

[0087] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A semiconductor device comprising: a test region including a test memory cell structure, the test memory cell structure comprising: A first gate stack on a first protrusion of a substrate, wherein the first gate stack includes a first dielectric material, a first polysilicon material on the first dielectric material, and one or more additional dielectric materials on the first polysilicon material; a first polysilicon structure disposed on one side of the first protrusion and in a region between the side of the first protrusion and one side of a second protrusion of the substrate, and without any other protrusions between the first and second protrusions; a first spacer disposed in the region between the side of the first and second protrusions and on one side of the first polysilicon structure; and a second gate stack on the second protrusion, wherein the second gate stack includes a second dielectric material, a second polysilicon material on the second dielectric material, and one or more additional dielectric materials on the second polysilicon material. A second polycrystalline silicon structure disposed on one side of the second protrusion and in the region between the one side of the first protrusion and the one side of the second protrusion, and a second spacer disposed in the region between the one side of the first protrusion and the one side of the second protrusion and on one side of the second polycrystalline silicon structure. And an inter-dielectric layer above at least a portion of the test area.

2. The semiconductor device as described in claim 1, wherein, There is no floating gate layer in either the first gate stack or the second gate stack.

3. The semiconductor device as claimed in claim 1, wherein the test memory cell structure is one of a plurality of test memory cell structures in the test region, and a spacing between the first gate stack and the second gate stack is different from a spacing between a pair of gate stacks included in another test memory cell structure of the test memory cell structures.

4. A method for forming a semiconductor device, comprising the following steps: forming a first gate stack and a second gate stack on a substrate, wherein the first gate stack includes a first dielectric material, a first polysilicon material on the first dielectric material, and one or more additional dielectric materials on the first polysilicon material, and the second gate stack includes a second dielectric material, a second polysilicon material on the second dielectric material, and one or more additional dielectric materials on the second polysilicon material; removing a portion of a region of the substrate located between one side of the first gate stack and one side of the second gate stack to form a recessed portion in the substrate in the region between the first gate stack and the second gate stack, thereby allowing the first gate stack to be stacked on a first protruding portion of the substrate, allowing the second gate stack to be stacked on a second protruding portion of the substrate, and there are no other protruding portions between the first protruding portion and the second protruding portion; A polycrystalline silicon layer is formed on the first gate stack, the second gate stack, and in the recessed portion of the substrate; a recessed portion is formed in the polycrystalline silicon layer in the region between the side of the first gate stack and the side of the second gate stack to form a first polycrystalline silicon structure on one side of the first protrusion and a second polycrystalline silicon structure on one side of the second protrusion; a first spacer is formed on one side of the first polycrystalline silicon structure, wherein the first spacer is in the region between the side of the first protrusion and the side of the second protrusion; a second spacer is formed on one side of the second polycrystalline silicon structure, wherein the second spacer is in the region between the side of the first protrusion and the side of the second protrusion; and an inter-dielectric layer is formed above the first gate stack, above the second gate stack, and in the region between the first gate stack and the second gate stack.

5. The method of claim 4 further comprises the step of removing a floating gate layer from the substrate prior to forming the first gate stack and the second gate stack.

6. A test structure comprising: a substrate including a first protrusion and a second protrusion; a first layer stack on the first protrusion, wherein the first layer stack includes a first dielectric material, a first polysilicon material on the first dielectric material, and one or more additional dielectric materials on the first polysilicon material; a second layer stack on the second protrusion, wherein the second layer stack includes a second dielectric material, a second polysilicon material on the second dielectric material, and one or more additional dielectric materials on the second polysilicon material; one or more first polysilicon structures located on the side of the first protrusion closest to the second protrusion; and one or more second polysilicon structures located on the side of the second protrusion closest to the first protrusion, wherein there are no other protrusions in a region between that side of the first protrusion and that side of the second protrusion. A first spacer disposed in the region between the side of the first protrusion and the side of the second protrusion and on one side of the one or more first polycrystalline silicon structures; a second spacer disposed in the region between the side of the first protrusion and the side of the second protrusion and on one side of the one or more second polycrystalline silicon structures; and a dielectric layer disposed above the first layer stack, above the second layer stack, above the one or more first polycrystalline silicon structures, above the one or more second polycrystalline silicon structures, and in a region between the one or more first polycrystalline silicon structures and the one or more second polycrystalline silicon structures.

7. The test structure as described in claim 6, wherein the test structure is used to enable void monitoring of an element comprising the substrate, based on a size of an aspect ratio of the region between the one or more first polycrystalline silicon structures and the one or more second polycrystalline silicon structures.

8. A semiconductor element, comprising: A test memory cell region includes: a first-layer stacked structure located on a first protrusion of a substrate, wherein the first-layer stacked structure includes a first dielectric material, a first polysilicon material on the first dielectric material, and one or more additional dielectric materials on the first polysilicon material; and a second-layer stacked structure located on a second protrusion of the substrate, wherein the second-layer stacked structure includes a second dielectric material, a second polysilicon material on the second dielectric material, and one or more additional dielectric materials on the second polysilicon material. One or more first structures are located on the side of the first protrusion closest to the second protrusion, wherein the one or more first structures include at least one first polysilicon structure and at least one first spacer layer on one side of the at least one first polysilicon structure; and one or more second structures are located on the side of the second protrusion closest to the first protrusion, wherein the one or more second structures include at least one second polysilicon structure and at least one second spacer layer on one side of the at least one second polysilicon structure, and there are no other protrusions between the first protrusion and the second protrusion; and a dielectric layer is located on at least a portion of the test memory cell region.

9. A method for forming a semiconductor device, comprising: A first-layer stacked structure and a second-layer stacked structure are formed on a substrate, wherein the first-layer stacked structure includes a first dielectric material, a first polycrystalline silicon material on the first dielectric material, and one or more additional dielectric materials on the first polycrystalline silicon material; the second-layer stacked structure includes a second dielectric material, a second polycrystalline silicon material on the second dielectric material, and one or more additional dielectric materials on the second polycrystalline silicon material; a recessed portion of the substrate is formed in a region between the first-layer stacked structure and the second-layer stacked structure, wherein the step of forming the recessed portion of the substrate forms a first protrusion and a second protrusion, the first protrusion being located under the first-layer stacked structure and the second protrusion being located under the second-layer stacked structure, and there are no other protrusions between the first protrusion and the second protrusion; One or more first structures are formed on the side of the first protrusion closest to the second protrusion, the one or more first structures including at least one first polycrystalline silicon structure and at least one first spacer layer on one side of the at least one first polycrystalline silicon structure; one or more second structures are formed on the side of the second protrusion closest to the first protrusion, the one or more second structures including at least one second polycrystalline silicon structure and at least one second spacer layer on one side of the at least one second polycrystalline silicon structure; and a dielectric layer is formed on the first layer stack structure, on the second layer stack structure, on the one or more first structures, on the one or more second structures, and in a region between the one or more first structures and the one or more second structures.

10. A method for forming a semiconductor device, comprising: A first stacked structure and a second stacked structure are formed in a test memory cell region and on a substrate. The first stacked structure includes a first dielectric material, a first polysilicon material on the first dielectric material, and one or more additional dielectric materials on the first polysilicon material. The second stacked structure includes a second dielectric material, a second polysilicon material on the second dielectric material, and one or more additional dielectric materials on the second polysilicon material. A recessed portion of the substrate is formed in a region between the first stacked structure and the second stacked structure. The step of forming the recessed portion of the substrate forms a first protrusion and a second protrusion. The first protrusion is located under the first stacked structure, and the second protrusion is located under the second stacked structure. There are no other protrusions between the first protrusion and the second protrusion. One or more first structures are formed on the side of the first stacked structure closest to the second stacked structure, wherein the one or more first structures include at least one first polysilicon structure and at least one first spacer layer on one side of the first polysilicon structure; one or more second structures are formed on the side of the second stacked structure closest to the first stacked structure, wherein the one or more second structures include at least one second polysilicon structure and at least one second spacer layer on one side of the second polysilicon structure; and a dielectric layer is formed on at least a portion of the test memory cell region.

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