Circuit device aging assessment and compensation

Abstract

One embodiment relates to an apparatus comprising: a set of one or more receivers; a first replica circuit that is a substantial replica of at least a portion of one of the receivers in the set of one or more receivers; a first control circuit that generates an output signal selectively coupled to an input of the first replica circuit; a second replica circuit that is a substantial replica of at least a portion of one of the receivers in the set of one or more receivers; a comparator that includes a first input coupled to a first output of the first replica circuit, a second input coupled to a second output of the second replica circuit, and an output; and a second control circuit that includes an input coupled to the output of the comparator, and an output coupled to both the first replica circuit and the set of one or more receivers.

Description

[Technical Field]

[0001] Priority Claim

[0002] This patent application claims priority to U.S. formal application No. 17 / 339,195, filed on June 4, 2021 and assigned to its assignee, which is incorporated herein by reference as is fully set forth below for all applicable purposes.

[0003] The various embodiments disclosed herein generally relate to integrated circuits (ICs) or discrete circuits, and more specifically, to apparatus and methods for aging assessment and compensation of circuit elements. [Previous Technology]

[0004] The performance of circuit elements (e.g., field-effect transistors, FETs) often cannot remain constant throughout their entire operating life. For example, when a FET is operated over time by applying a varying gate-source voltage Vgs according to the operation in which the FET is used, carriers are injected into the gate oxide of the FET and trapped in the oxide. Carriers trapped in the FET oxide typically increase the FET's threshold voltage Vth, thus requiring a larger Vgs drive voltage to achieve the same drain current through the FET. If such aging effects on the FETs of integrated circuits (ICs) are not corrected, the operation of the IC may fail to meet specifications or may even malfunction. [Summary of the Invention]

[0005] The following is a simplified summary of one or more embodiments to provide a basic understanding of such embodiments. This summary is not a broad overview of all conceived embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to define the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description provided below.

[0006] One aspect of this disclosure relates to an apparatus. The apparatus includes: a set of one or more receivers; a first replica circuit that is a substantial replica of at least a portion of one of the receivers in the set of one or more receivers; a first control circuit that generates an output signal selectively coupled to an input of the first replica circuit; a second replica circuit that is a substantial replica of at least a portion of one of the receivers in the set of one or more receivers; a comparator that includes a first input coupled to a first output of the first replica circuit, a second input coupled to a second output of the second replica circuit, and an output; and a second control circuit that includes an input coupled to the output of the comparator, and an output coupled to the first replica circuit and coupled to the set of one or more receivers.

[0007] Another aspect of this disclosure provides a method. The method includes: providing a receiver with one of a data signal and a clock signal; in an aging mode: substantially providing an aging signal to a first replica circuit, which is a substantial replica of the receiver, while the data signal and the clock signal are substantially provided to the receiver, wherein the aging signal causes the first replica circuit to operate substantially the same as or more heavily than the data signal and the clock signal; and keeping a second replica circuit, which is a substantial replica of the receiver, disabled; in a calibration mode: enabling the second replica circuit, stopping the provision of the aging signal to the first replica circuit, applying input voltages to the inputs of the first and second replica circuits, wherein the first and second replica circuits generate first and second output voltages based on the input voltages, respectively, generating a compensation voltage based on the difference between the first and second output voltages of the first and second replica circuits, and calibrating the receiver and the first replica circuit based on the compensation voltage.

[0008] Another aspect of this disclosure relates to an apparatus. The apparatus includes: components for providing a data signal and a clock signal to a receiver; in an aging mode: components for providing an aging signal to a first replica circuit, which is a substantial replica of the receiver, substantially simultaneously with the provision of the data signal and the clock signal to the receiver, wherein the aging signal causes the first replica circuit to operate substantially the same as or more heavily than the data signal and the clock signal; and components for keeping a second replica circuit, which is a substantial replica of the receiver, disabled; in a calibration mode: components for enabling the second replica circuit, components for stopping the provision of the aging signal to the first replica circuit, components for applying input voltages to the inputs of the first and second replica circuits, wherein the first and second replica circuits generate first and second output voltages based on the input voltages, respectively; components for generating a compensation voltage based on the difference between the first and second output voltages of the first and second replica circuits; and components for calibrating the receiver and the first replica circuit based on the difference between the first and second output voltages.

[0009] Another aspect relates to an automotive control system. The automotive control system includes: a set of automotive control signal transmitters; a set of automotive control signal receivers coupled to the set of automotive control signal transmitters via a set of transmission lines; and an aging compensation circuit. The aging compensation circuit includes: a first replica circuit that is a substantial replica of one of the receivers in the set of automotive control signal receivers; a first control circuit including an output selectively coupled to an input of the first replica circuit; a second replica circuit that is a substantial replica of one of the receivers in the set of automotive control signal receivers; a comparator including a first input coupled to a first output of the first replica circuit and a second input coupled to a second output of the second replica circuit; and a second control circuit including an input coupled to the output of the comparator and an output coupled to both the first replica circuit and the set of automotive control signal receivers.

[0010] To achieve the foregoing and related objectives, the one or more embodiments include the features fully described below and specifically pointed out in the claims. The following description and drawings illustrate certain exemplary patterns of the one or more embodiments in detail. However, these patterns only indicate a few of the various ways in which the principles of various embodiments can be employed, and the descriptive embodiments are intended to encompass all such patterns and their equivalents.

Implementation Method

[0019] The detailed descriptions following the diagrams are intended to describe various configurations, and not to represent only the configurations in which the concepts described herein can be practiced. The detailed descriptions include specific details to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, familiar structures and elements are shown in block diagram form to avoid confusing such concepts.

[0020] This disclosure relates to providing an aged replica circuit for a target circuit (e.g., a receiver) to be compensated for aging effects, and an unaged replica circuit for the target circuit. At the beginning (start-up) of the circuit's operating lifetime, the aged replica circuit (not aged at this time) and the unaged replica circuit are calibrated to generate substantially the same output voltage. During the circuit's operating lifetime, the aged replica circuit is operated in a manner similar to the target circuit, such that the aging of the aged replica circuit is substantially the same as or more aggressive than that of the target circuit. The unaged replica circuit is disabled for most of the circuit's operating lifetime and is periodically or in some time-based manner enabled to assess the aging of the aged replica circuit, and then compensated for aging effects, subsequently applied to the target circuit.

[0021] FIG1 shows a block diagram of an exemplary device 100 including an exemplary aging compensation circuit 130 according to one embodiment of the present disclosure. The device 100 includes a data transmission element 105, which may be, for example, a double data rate (DDR) memory data transmission component or a low power DDR (LPDDR) memory data transmission component, etc. The data transmission element 105 may include a set of one or more transmitters (Tx) 110-1 to 110-N, a set of one or more receivers (Rx) 115-1 to 115-N, and a set of one or more transmission media 120-1 to 120-N, the transmission media coupling the set of one or more transmitters 110-1 to 110-N to the set of one or more receivers 115-1 to 115-N, respectively.

[0022] Each of these transmitters 110-1 to 110-N can be configured to transmit a data signal DQ or a clock (CLK) via a corresponding one of the transmission media 120-1 to 120-N to a corresponding one of the receivers 115-1 to 115-N. Typically, one of the transmitters (e.g., 110-N) is configured to transmit the clock (CLK), and the remaining transmitters (e.g., 110-1 to 110-N-1) are configured to transmit data signals DQ1 to DQN-1 respectively. As illustrated, the set of transmitters 110-1 to 110-N is configured to transmit data signals DQ1 to DQN-1 and the clock (CLK) via the set of transmission media 120-1 to 120-N to the set of receivers 115-1 to 115-N. Each transmission medium can be configured as one or more metallized lines or traces on a printed circuit board (PCB), for example, one differential transmission line pair for each transmitter-receiver pair.

[0023] The aging compensation circuit 130 includes an aging control circuit 140, a voltage generator 145, a first multiplexer 150, an aging copy circuit 155, an unaged copy circuit 160 (e.g., which may be referred to as a "gold reference"), a second multiplexer 165, a comparator 170, and a calibration control circuit 180. The aging compensation circuit 130 may also include a controller 190, which is configured to generate mode signals controlling the operating mode of the aging compensation circuit 130. As discussed in more detail herein, the operating mode may include a startup mode, an aging mode, and a calibration mode.

[0024] The aging control circuit 140 is configured to generate an analog aging signal or voltage VSAS to cause the aging replica circuit 155 to operate or function substantially the same as or more heavily (e.g., at a higher rate) as the data signal DQ1 or the clock signal (CLK) to the target circuit (e.g., any of receivers 115-1 to 115-N). In this example, a receiver enable signal VEN_RX is coupled to the set of receivers 115-1 to 115-N and to the aging control circuit 140. When the receiver enable signal VEN_RX is active, the set of receivers 115-1 to 115-N receives the data signals DQ1 to DQN-1 and the clock signal from the set of transmitters 110-1 to 110-N via the set of transmission media 120-1 to 120-N. When the receiver enable signal V EN_RX is not active, no data or clock signals are transmitted between transmitters 110-1 to 110-N and receivers 115-1 to 115-N.

[0025] Similarly, when the receiver enable signal VEN_RX is active, the aging control circuit 140 operates to generate an analog aging signal or voltage VSAS, causing the aging replica circuit 155 to operate or function substantially the same as or more heavily than the data signals DQ1 to DQN-1 and the clock signal (CLK) for the receivers 115-1 to 115-N. When the receiver enable signal VEN_RX is not active, the aging control circuit 140 can be disabled (e.g., VSAS is not generated) to save power.

[0026] The aging control circuit 140 includes an output coupled to a first input of the multiplexer 150. The voltage generator 145 includes at least one output coupled to a second input of the multiplexer 150 via an associated or integrated single-pole double-throw (SPDT) switch 146. The multiplexer 150 includes a selection input configured to receive a mode signal generated by the controller 190. The multiplexer 150 includes an output coupled to the first input of the aging replica circuit 155. As an example, if the mode signal indicates an aging mode, the multiplexer 150 passes an analog aging signal or voltage VSAS to the first input of the aging replica circuit 155. If the mode signal indicates a startup or calibration mode, the multiplexer 150 passes a voltage Vin received from the voltage generator 145 via the SPDT 146 to the first input of the aging replica circuit 155. As an example, when the aging replica circuit 155 (and the set of receivers 115-1 to 115-N) is configured as a differential circuit, the voltage VIN can be the common-mode voltage VCM.

[0027] Optionally, a mode can be provided to disable the aging replica circuit 155 to save power; in such a case, the voltage generator 145 can be configured to generate a disable voltage VDSB. In this mode, the multiplexer 150 receives the disable voltage VDSB from the voltage generator 145 via the SPDT 146 and passes the disable voltage VDSB to the first input of the aging replica circuit 155, which effectively disables the aging replica circuit 155. It should be understood that the voltage generator 145 can generate other voltages, including a lower voltage rail potential Vss, which can be the ground potential for other operating or application modes.

[0028] The aging replica circuit 155 may be a substantial replica of at least a portion of one of the receivers in the set of receivers 115-1 to 115-N. For example, each receiver in the set of receivers 115-1 to 115-N may include a preamplifier stage, an equalizer, clock and data recovery (CDR) circuitry, a deserializer, etc. The aging replica circuit 155 may be a substantial replica of the preamplifier stage, but not of other components of that receiver. Furthermore, the aging replica circuit 155 may not be an exact replica of the front-end amplification stage, but may include more or fewer components (one or more) without substantially affecting the similar aging effect between receivers 115-1 to 115-N and the aging replica circuit 155. Alternatively or additionally, the aging replica circuit 155 may be a smaller-scale version of at least a portion of one of the receivers in the set of receivers 115-1 to 115-N (e.g., using transistors ten times (or other scales) smaller). As illustrated, the aging replica circuit 155 includes a second input that receives an aging control signal (AGING CS) and an output configured to generate a first output voltage V1 (e.g., a direct current (DC) voltage).

[0029] The second multiplexer 165 includes first and second inputs, which may also be coupled to the voltage generator 145. For example, the first input of the second multiplexer 165 may be configured to receive a disable signal VDSB from the voltage generator 145. Similarly, the second input of the second multiplexer 165 may be configured to receive a voltage VIN from the voltage generator 145. The second multiplexer 165 further includes a selection input configured to receive a mode signal generated by the controller 190. Additionally, the second multiplexer 165 includes an output coupled to the unburned copy circuit 160.

[0030] Similar to the aged replica circuit 155, the unaged replica circuit 160 may be a substantial replica of at least a portion of one of the receivers in the set of receivers 115-1 to 115-N. For example, the unaged replica circuit 160 may be a substantial replica of the front-end amplification stage of one of the receivers 115-1 to 115-N, but not of other components of that receiver (e.g., equalizer, CDR, deserializer, etc.). Furthermore, the unaged replica circuit 160 need not be an exact replica of the front-end amplification stage, but may include more or fewer components. As discussed, the unaged replica circuit 160 may be a smaller-scale version of at least a portion of one of the receivers in the set of receivers 115-1 to 115-N (e.g., using transistors ten times (or other scales) smaller). For example, the unaged replica circuit 160 may be a substantial replica of the aged replica circuit 155. As illustrated, the unaged copy circuit 160 includes an output configured to generate a second output voltage V2 (e.g., a DC voltage).

[0031] Comparator 170 includes first and second inputs coupled to the outputs of aged copy circuit 155 and unaged copy circuit 160, respectively. Accordingly, comparator 170 is configured to receive a first output voltage V1 and a second output voltage V2 at its first and second inputs, respectively. Comparator 170 includes an output configured to generate a compensation voltage VCOM based on the difference between the first output voltage V1 and the second output voltage V2.

[0032] The calibration control circuit 180 includes a first input coupled to the output of the comparator 170. Accordingly, the first input of the calibration control circuit 180 is configured to receive a compensation voltage VCOMP. The calibration control circuit 180 includes a second input configured to receive a mode signal generated by the controller 190, and a first output configured to generate an aging control signal (AGING CS). The first output of the calibration control circuit 180 is coupled to a second input of the aging replica circuit 155. The calibration control circuit 180 also includes a second output configured to generate a broadcast aging control signal (AGING CS B). The second output is coupled to inputs of the set of receivers 115-1 to 115-N, respectively.

[0033] At startup, the collection of receivers 115-1 to 115-N, the aged replica circuit 155, and the unaged replica circuit 160 are unaged or may have negligible aging due to testing or other preliminary operations. During startup, the aged replica circuit 155 is calibrated to generate a first output voltage V1 that is substantially equal to the second output voltage V2 generated by the unaged replica circuit 160.

[0034] In this regard, controller 190 sets the operating mode to startup mode. In this mode, first and second multiplexers 150 and 165 pass voltage VIN to the inputs of aged and unaged replica circuits 155 and 160, respectively. In response, aged and unaged replica circuits 155 and 160 generate a first output voltage V1 and a second output voltage V2 based on the input voltage VIN. Comparator 170 generates a compensation voltage VCOM based on the difference between the first output voltage V1 and the second output voltage V2. Calibration control circuit 180 generates an aging control signal (AGING CS) based on the compensation voltage VCOM to adjust the aged replica circuit 155 such that the output of the aged replica circuit 155 is substantially equal to the first output voltage V1 of the second output voltage V2 (e.g., VCOM = 0 volts (V)). Since both the aged replica circuit 155 and the unaged replica circuit 160 are substantially unaged at startup, the equality of the first output voltage V1 and the second output voltage V2 indicates that these circuits are at the same aging level.

[0035] After the startup mode, the aging compensation circuit 130 operates in the aging mode. In this mode, the first and second multiplexers 150 and 165 respectively deliver voltages VSAS and VDSB to the inputs of the aging and non-aging replica circuits 155 and 160. The disable voltage VDSB delivered to the non-aging replica circuit 160 effectively disables the non-aging replica circuit 160. This prevents the non-aging replica circuit 160 from aging while in the aging mode, thereby keeping the aging of the non-aging replica circuit 160 minimal or very low. The analog aging signal or voltage VSAS delivered to the aging replica circuit 155 causes the aging replica circuit 155 to operate substantially the same as or more heavily than the data signals DQ1 to DQN-1 and the clock signal (CLK) to the corresponding receivers 115-1 to 115-N. Therefore, when the receiver enable signal V EN_RX is active, receivers 115-1 to 115-N operate or function via the signal they receive; and in response to the active enable signal V EN_RX, the aging control circuit 140 enables or functions the aging replication circuit 155 via the analog aging signal V SAS.

[0036] Periodically or in some time-based manner, the aging compensation circuit 130 operates in a calibration mode, for example, a mode signal generated by the controller 190 indicates the calibration mode. In the calibration mode, the aging effect is evaluated on the aging replica circuit 155 based on changes in the first output voltage V1. For example, for a particular embodiment of the aging replica circuit 155, the first output voltage V1 tends to decrease with aging. Then, the comparator 170 generates a compensation voltage VCOM, which indicates the aging of the aging replica circuit 155 based on the difference between the first output voltage V1 and the second output voltage V2. Then, the calibration control circuit 180 generates or adjusts an aging control signal (AGING CS) to make the first output voltage V1 substantially the same as the second output voltage V2. Thus, the aging replica circuit 155 has been compensated for aging at this time. Then, the final aging control signal (AGING CS) for each calibration cycle is broadcast (AGING CS B) to the set of receivers 115-1 to 115-N in order to compensate these receivers for aging.

[0037] More specifically, in calibration mode, the first and second multiplexers 150 and 165 transmit voltage VIN to the inputs of the aging and non-aging replica circuits 155 and 160, respectively. Therefore, in calibration mode, the aging control circuit 140 is decoupled from the aging replica circuit 155, and thus the aging replica circuit 155 stops receiving the analog aging signal VSAS. Furthermore, in calibration mode, the disable voltage VDSB is not coupled to the non-aging replica circuit 160; instead, VIN is applied to the non-aging replica circuit 160. In response to receiving the input voltage VIN, the aging and non-aging replica circuits 155 and 160 generate a first output voltage V1 and a second output voltage V2 based on the input voltage VIN. The comparator 170 generates a compensation voltage VCOM based on the difference between the first output voltage V1 and the second output voltage V2. The calibration control circuit 180 adjusts the aging control signal (AGING CS) so that the aging replication circuit 155 generates a first output voltage V1, such that the first output voltage V1 is substantially equal to a second output voltage V2. In response to V1 and V2 being substantially equal, the calibration control circuit 180 broadcasts the final aging signal (AGING CS B) for each calibration cycle to a set of receivers 115-1 to 115-N for aging compensation to these receivers.

[0038] The frequency of the calibration cycle can be based on a metric or function related to the usage of the data transmission element 105. If the usage rate of the data transmission element 105 is relatively high, the frequency of the calibration cycle should also be relatively high. Conversely, if the usage rate of the data transmission element 105 is relatively low, the frequency of the calibration cycle should also be relatively low. As an example, if the device 100 is used in an automotive application, the usage rate of the data transmission element 105 may be higher than when the device 100 is used in a cellular telephone application. Since the unaged copy circuit 160 is enabled during the calibration cycle, the frequency of the calibration cycle should be kept low enough to prevent significant aging of the unaged copy circuit 160.

[0039] Figure 2 shows a block diagram of another exemplary device 200 according to another aspect of this disclosure, including another exemplary aging compensation circuit 230. Device 200 is a more specific implementation of device 100 because the aging control circuit 140 of device 100 can be configured as an oscillator, for example, a voltage-controlled oscillator (VCO). Components of device 200 that are the same as or common to those of device 100 are denoted by the same component symbols, except that the most significant digit (MSD) of the components in device 200 is “2” instead of “1”. Details of these common components have been discussed with reference to device 100.

[0040] As mentioned, the aging control circuit 140 of device 100 can be implemented as an oscillator or VCO 240 in device 200. Accordingly, VCO 240 is configured to generate an analog aging signal or voltage VSAS as an oscillation signal, which can also be substantially periodic. The frequency of the oscillation signal VSAS can be consistent with the frequency of the data rate or clock signal (CLK) of the data signals DQ1 to DQN-1 provided to the receivers 215-1 to 215-N. For example, the frequency of the oscillation signal VSAS can be within a expected or specified range for the data rate or clock signal (CLK) of the data signals DQ1 to DQN-1. According to another example, the frequency of the oscillation signal VSAS can be at the higher end of the expected or specified range for the data rate or clock signal (CLK) of the data signals DQ1 to DQN-1 or higher than that range. The reason for this is that it may be more advantageous to assess the aging of the set of receivers 215-1 to 215-N as being higher than the actual aging of these receivers.

[0041] Therefore, in aging mode, when the receiver enable signal VEN_RX is active (indicating that receivers 215-1 to 215-N are receiving data signals DQ1 to DQN-1 and clock signal (CLK)), VCO 240 generates an oscillating aging signal VSAS, which is transmitted by multiplexer 250 to aging copy circuit 255. Thus, the oscillating aging signal VSAS causes aging copy circuit 255 to operate substantially the same as or more heavily than the data signals DQ1 to DQN-1 and clock signal (CLK) causing receivers 215-1 to 215-N to operate. When the receiver enable signal V EN_RX is not active (indicating that receivers 215-1 to 215-N are not receiving data signals DQ1 to DQN-1 and clock signals (CLK)), VCO240 is deactivated by the receiver enable signal V EN_RX.

[0042] Figure 3 shows a block diagram of yet another exemplary device 300 according to another aspect of this disclosure, including yet another exemplary aging compensation circuit 330. Similarly, device 300 is an example of a more specific implementation of device 100, since the aging control circuit 140 of device 100 can be coupled to the output of one of the receivers in a set of receivers, such that the analog aging signal VSAS is based on a data signal or clock signal received by such receiver. Components in device 300 that are the same as or common to those in device 100 are indicated by the same component symbols, except that the MSD of the components in device 300 is “3” instead of “1”. Details of these common components have been discussed with reference to device 100.

[0043] In device 300, aging control circuitry 340 can be implemented as a voltage level shifter or current-mode logic (CML) circuit. In this example, voltage level shifter or CML circuitry 340 is differential, but it can also be single-ended. Voltage level shifter or CML circuitry 340 includes differential inputs coupled to the differential output of one receiver (e.g., receiver 315-1) in a set of receivers. As mentioned above, the differential input of voltage level shifter or CML circuitry 340 can be coupled to the differential output of a first amplification stage of receiver 315-1, because receiver 315-1 can include additional stages such as equalizers, CDRs, deserializers, etc. The voltage level shifter or CML circuit 340 then receives the differential data signal DQ1 or clock signal (CLK) from the differential output (OUT-1) of the receiver 315-1, and the voltage level shifts the differential signal to generate an analog aging signal or voltage VSAS at a voltage level suitable for the input of the aging replica circuit 355. Since the analog aging signal VSAS is based on the data signal DQ1 or clock signal (CLK), it can cause the aging replica circuit 355 to operate or function substantially the same as the data signal DQ1 or clock signal (CLK) that causes the receiver 315-1 to operate or function.

[0044] Therefore, in aging mode, when receiver 315-1 receives data signal DQ1 or clock signal (CLK), voltage level shifter or CML 340 generates analog aging signal VSAS. The analog aging signal VSAS is transmitted by multiplexer 350 to aging copy circuit 355. Thus, the analog aging signal VSAS causes aging copy circuit 355 to operate in substantially the same way as the data signal DQ1 or clock signal (CLK) causes receiver 315-1 to operate. When receiver 315-1 is not receiving data signal DQ1 or clock signal (CLK), voltage level shifter or CML 340 is effectively disabled because it does not generate analog aging signal VSAS.

[0045] Figure 4 shows a schematic diagram of an exemplary aging compensation circuit 400 according to another aspect of this disclosure. The aging compensation circuit 400 may be an example of a more detailed implementation of the aging compensation circuit 230 discussed earlier.

[0046] Specifically, the aging compensation circuit 400 includes a calibration control circuit 410, a voltage controlled oscillator (VCO) 420, a first multiplexer 430, an aging replica circuit 440, an unaged replica circuit 450, a comparator 460, and a controller 490. Starting with VCO 420, it includes a set of cascaded differential buffers or inverters 422-1 to 422-4. In this example, VCO 420 includes four (4) buffers or inverters 422-1 to 422-4. However, it should be understood that VCO 420 may include a different number of cascaded differential buffers or inverters. For the purpose of feedback oscillation, the last buffer or inverter 422-4 includes a complementary output cross-coupled to the complementary input of the first buffer or inverter 422-1. As discussed above, when the set of receivers 215-1 to 215-N is enabled to receive data signals DQ1 to DQN-1 and clock signal (CLK), VCO 420 is configured to receive receiver enable signal VEN_RX to enable VCO 420 to generate differential ratio aging signal or voltage VSAS; otherwise, it will be disabled as discussed above.

[0047] The first multiplexer 430 includes a pair of tri-state buffers 432 and 434 and a pair of switching elements SW1 to SW2 (which can be configured as field-effect transistors (FETs)). Tri-state buffers 432 and 434 include inputs to the differential output of the last buffer or inverter 422-4 of VCO 420 (which is also the differential input of the first buffer or inverter 422-1). Switching elements SW1 and SW2 are coupled between the outputs VA and VB of a voltage generator (e.g., voltage generator 245) and the outputs of tri-state buffers 432 and 434, respectively. For flexibility, the voltage generator can apply independent or identical voltages to switching elements SW1 and SW2, such as different common-mode voltages VCMA and VCMB, a disable voltage VDSB (which can be the Vdd or VCSA potential at the source of FETs M1 and M2), or Vss or ground.

[0048] Tri-state buffers 432 and 434 and switching elements SW1 and SW2 include control inputs configured to receive mode signals generated by controller 490. For example, if the mode signal indicates a start-up or calibration mode, tri-state buffers 432 and 434 are tri-state, and switching elements SW1 and SW2 are in their closed state. If the mode signal indicates an aging mode, tri-state buffers 432 and 434 transmit the differential class ratio aging signal VSAS to the aging replica circuit 440, and switching elements SW1 and SW2 are in their open state.

[0049] As discussed, the aging replica circuit 440 may be a substantial replica of at least a portion of any receiver 215-1 to 215-N (such as, for example, the front-end differential amplification stage of each receiver). As an example, the aging replica circuit 440 includes a variable current source 442, an input differential FET pair M1 and M2 (e.g., each implemented as a p-channel metal oxide semiconductor FET (PMOS FET)), and a pair of output resistors R1 and R2. On the negative side of this differential implementation, the current source 442, FET M1, and resistor R1 are coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss (e.g., ground). On the positive side of this differential implementation, the current source 442, FET M2, and resistor R2 are coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss (e.g., ground). FETs M1 and M2 include gates coupled to the outputs of tri-state buffers 432 and 434, respectively.

[0050] Moreover, as discussed, the unburned replica circuit 450 may be a substantial replica of at least a portion of any receiver 215-1 to 215-N (such as, for example, the front-end differential amplification stage of each receiver). For example, the unburned replica circuit 450 includes a variable current source 452, an input differential FET pair M3 and M4 (e.g., each implemented as a PMOS FET), and a pair of output resistors R3 and R4. On the negative side of this differential implementation, the current source 452, FET M3, and resistor R3 are coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss (e.g., ground). On the positive side of this differential implementation, the current source 452, FET M4, and resistor R4 are coupled in series between the upper voltage rail Vdd and the lower voltage rail Vss (e.g., ground). FETs M3 and M4 include gates coupled to the outputs of multiplexers 454 and 456, respectively.

[0051] Referring to the aging compensation circuit 230, multiplexers 454 and 456 may correspond to multiplexer 265 (and in this example, multiplexers 454 and 456 are illustrated as portions of the unaged replica circuit 450). Multiplexers 454 and 456 are on the negative and positive sides, respectively, in this differential implementation, and include a corresponding first input configured to receive a disable voltage VDSB and a corresponding second input configured to receive a common-mode voltage VCM. As discussed above, when the disable voltage VDSB is applied to the gates of FETs M3 and M4, the disable voltage VDSB disables the unaged replica circuit 450 by turning off FETs M3 and M4. Since FETs M3 and M4 are PMOS FETs, the disable voltage VDSB can be at the Vdd or VCSB potential at the source of FETs M3 and M4 (making the gate-source voltage VGS substantially zero or below the threshold voltage of FETs M3 and M4). Alternatively, when the unaged replica circuit 450 is to be disabled, the switching element can be implemented to short the gates and sources of FETs M3 and M4 together. Multiplexers 454 and 456 include selection inputs configured to receive mode signals from controller 490.

[0052] As further discussed herein, in order to achieve fine resolution offset cancellation during startup mode, the unburned replica circuit 450 includes a first variable current source 458 coupled between the upper voltage rail Vdd and a node between the drain of the PMOS FET M3 of the unburned replica circuit 450 and the output resistor R3 (e.g., negative output). Furthermore, the unburned replica circuit 450 also includes a second variable current source 452 coupled between the upper voltage rail Vdd and a node between the drain of the PMOS FET M4 of the unburned replica circuit 450 and the output resistor R4 (e.g., positive output).

[0053] Comparator 460 includes a first multiplexer 462, a second multiplexer 464, and a differential amplifier 466. The first multiplexer 462 includes a first input coupled to the negative output of the aged replica circuit 440. The first multiplexer 462 also includes a second input coupled to the positive output of the unaged replica circuit 450. The second multiplexer 464 includes a first input coupled to the negative output of the unaged replica circuit 450. The second multiplexer 464 also includes a second input coupled to the positive output of the aged replica circuit 440. The first and second multiplexers 462 and 464 include selection inputs configured to receive a selection signal SEL generated by controller 490.

[0054] The differential amplifier 466 includes a first input (e.g., a negative input) coupled to the output of the first multiplexer 462, a second input (e.g., a positive input) coupled to the output of the second multiplexer 464, and an output configured to generate a compensation voltage VCOM. As further discussed herein, the compensation voltage VCOM may be based on the difference between: (1) the negative output voltage V2- of the unaged replica circuit 450 and the negative output voltage V1- of the aged replica circuit 440, if the selection signal SEL selects the respective first inputs of multiplexers 462 and 464 (e.g., SEL=0; VCOM=V2--V1-); or (2) the positive output voltage V1+ of the aged replica circuit 440 and the positive output voltage V2+ of the unaged replica circuit 450, if the selection signal selects the respective second inputs of multiplexers 462 and 464 (e.g., SEL=1; VCOM=V1+-V2+). In both cases, the compensation voltage V COMP provides an indication of the aging of the aging replica circuit 440; and by extension, provides an indication of the aging of the set of receivers 215-1 to 215-N.

[0055] The calibration control circuit 410 includes a digital encoder 412, a first control circuit 414, a second control circuit 418, and a third control circuit 416. The digital encoder 412 may be implemented as a thermometer encoder or an analog-to-digital converter (ADC). The digital encoder 412 includes an input coupled to the output of comparator 460 and configured to receive a compensation voltage VCOM from it. The digital encoder 412 is configured to generate a digital code based on the compensation voltage VCOM. The digital encoder 412 includes an output that generates the digital code thereon, which is coupled to the inputs of the first, second, and third control circuits 414, 418, and 416 and the input of controller 490.

[0056] As discussed further in more detail herein, the first control circuit 414 is configured to generate a first current source control signal or voltage VCS1 based on the code. The first current source control signal or voltage VCS1 is an example of the aging control signal AGING CS discussed above. The first control circuit 414 is also configured to generate a broadcast aging control signal (AGING CS B) for the set of receivers 215-1 to 215-N. Accordingly, the first control circuit 414 includes a first output that generates the control voltage VCS1 therein, which is coupled to a control input of the variable current source 442 of the aging replication circuit 440. The first control circuit 414 includes a second output that generates the broadcast control signal AGING CS B therein, which is coupled to the control inputs of the corresponding variable current sources of the set of receivers 215-1 to 215-N, respectively.

[0057] A second control circuit 418 is configured to generate a second current source control signal or voltage VCS2 based on the code. The second control circuit 418 includes an output that generates the control voltage VCS2, which is coupled to the control input of the variable current source 452 of the unaged replica circuit 450. A third control circuit 416 is configured to generate current control signals or voltages VCS3 and VCS4 based on the code. The third control circuit 416 includes outputs that generate control voltages VCS3 and VCS4, respectively, which are coupled to the inputs of current sources 458 and 460 of the unaged replica circuit 450.

[0058] The aging compensation circuit 400 can operate as follows: During startup, the aged copy circuit 440 and the unaged copy circuit 450 are effectively unaged or at substantially the same aging level. Accordingly, the compensation voltage VCOMP should be 0V to indicate that the aged copy circuit 440 and the unaged copy circuit 450 are at substantially the same aging level. However, due to process variations, the compensation voltage VCOMP may not be 0V. Therefore, during startup, the aged copy circuit 440 and the unaged copy circuit 450 are calibrated such that the compensation voltage based on V2--V1- and / or V1+-V2+ is substantially equal to 0V.

[0059] For example, controller 490 sets the mode signal to startup mode. In response to the startup mode signal, tri-state buffers 432 and 434 are tri-state, and switching elements SW1 and SW2 are closed. Voltage regulator 245 can provide common-mode voltage VCMA to the gates of PMOS FETs M1 and M2 via the closed switching elements SW1 and SW2, respectively. Voltage regulator 245 can also provide common-mode voltage VCMA to the second inputs of multiplexers 454 and 456 of the unburned replica circuit 450. Multiplexers 454 and 456, in response to the mode signal indicating startup mode, deliver the common-mode voltage VCMA to the gates of PMOS FETs M3 and M4, respectively.

[0060] Controller 490 can first select V2--V1- via selection signal SEL=0 to calibrate aged replica circuit 440 and unaged replica circuit 450. Initially, the compensation voltage VCOM may not be at 0V, meaning that aged replica circuit 440 and unaged replica circuit 450 have not yet been calibrated. Digital encoder 412 generates a code based on compensation voltage VCOM. Control circuits 414, 418, and 416 adjust current control voltages VCS1, VCS2, and VCS3 respectively to regulate the current generated by current sources 442, 452, and 458 until the code indicates that compensation voltage VCOM is substantially at 0V.

[0061] Then, controller 490 can select V1+-V2+ by selecting signal SEL=1. Initially, the compensation voltage VCOM based on V1+-V2+ may not be at 0V, which means that the aged copy circuit 440 and the unaged copy circuit 450 are not fully calibrated. Digital encoder 412 generates a code based on the compensation voltage VCOM. Control circuit 416 adjusts the current control voltage VCS4 to regulate the current generated by current source 459 until the code indicates that the compensation voltage VCOM is substantially at 0V. After calibration is initiated, control circuits 418 and 416 keep the current control voltage VCS2-VCS4 substantially constant because the unaged copy circuit 450 can be calibrated once initiated.

[0062] Next, the controller 490 sets the mode signal to aging mode. In response to aging mode, tri-state buffers 432 and 434 are not tri-state, and switching elements SW1 and SW2 are in the off state. When VCO 420 is enabled by the active receiver enable signal VEN_RX, tri-state buffers 432 and 434 pass the differential class aging signal VSAS to the gates of PMOS FETs M1 and M2 of the aging replica circuit 440. Accordingly, the aging replica circuit 440 ages substantially the same as or more aggressively than the set of receivers 215-1 to 215-N.

[0063] Regarding the unaged copy circuit 450 in aging mode, it is effectively disabled by passing the disable voltage VDSB to the gates of PMOS FETs M3 and M4 via multiplexers 454 and 456, thereby turning off these components. Furthermore, in response to aging mode, control circuit 418 can configure current control voltage VCS2 to turn off variable current source 452. Control circuit 416 can also configure current control voltages VCS3 and VCS4 to turn off variable current sources 458 and 459, respectively. This is done to effectively prevent the unaged copy circuit 450 from aging during aging mode, which occupies most of the time of operation of the aging compensation circuit 400. Additionally, comparator 460 is effectively disabled in aging mode. The control circuit 414 of the calibration control circuit 410 uses the current control voltage VCS1 of the variable current source 442 of the aging copy circuit 440 and the broadcast aging compensation signal (AGING CS B) to keep substantially constant, based on the final code determined in the previous calibration cycle.

[0064] As discussed, the controller 490 sets the mode signal to indicate the calibration mode periodically or otherwise in a time-based manner. As the set of aging replica circuits 440 and receivers 215-1 to 215-N ages in the aging mode, the conductivity of PMOS FETs M1 and M2 and the corresponding PMOS FETs in receivers 215-1 to 215-N decreases for the same gate-source voltage VGS. Accordingly, the differential output voltages V1+ and V1- tend to decrease with aging. Therefore, in the calibration mode, the aging compensation circuit 400 adjusts the differential output voltages V1+ and V1- so that they are substantially the same as the differential output voltages V2+ and V2- of the unaged replica circuit 450.

[0065] Accordingly, in response to the calibration mode, tri-state buffers 432 and 434 are tri-state, and switching elements SW1 and SW2 are closed. Voltage regulator 245 can provide a common-mode voltage VCMA to the gates of PMOS FETs M1 and M2 through the closed switching elements SW1 and SW2, respectively. Voltage regulator 245 can also provide a common-mode voltage VCMA to the second inputs of multiplexers 454 and 456 of the un-aged copy circuit 450. Multiplexers 454 and 456, in response to a mode signal indicating the calibration mode, pass the common-mode voltage VCMA to the gates of PMOS FETs M3 and M4, respectively. Moreover, in response to the calibration mode, control circuits 418 and 416 generate current control voltages VCS2-VCS4 according to the code finally determined during the startup mode.

[0066] Controller 490 can select V2--V1- via selection signal SEL=0 to calibrate aged replica circuit 440 and unaged replica circuit 450. Due to aging, the compensation voltage VCOM may no longer be substantially 0V, meaning that aged replica circuit 440 has aged compared to unaged replica circuit 450. Digital encoder 412 generates a code based on compensation voltage VCOM. Control circuit 414 adjusts current control voltage VCS1 to regulate the current generated by variable current source 442 until the code indicates that compensation voltage VCOM is substantially 0V. Controller 490 can optionally select V1+-V2+ via selection signal SEL=1 to determine whether calibration of V2--V1- still results in V1+-V2+ being substantially 0V. It should be understood that controller 490 can select V1+-V2+ via selection signal SEL=1 for calibration, and then optionally select V2--V1- via selection signal SEL=0 to determine whether the calibration still leaves V2--V1- substantially at 0V. Then, control circuitry 414 broadcasts an aging compensation signal (AGING CS B) for the set of receivers 215-1 to 215-N based on the final code arriving during the calibration cycle. Once the calibration cycle ends, controller 490 configures aging compensation circuitry 400 in aging mode.

[0067] Figure 5 shows a schematic diagram of a portion of an exemplary aging compensation circuit 500 according to another aspect of this disclosure. The aging compensation circuit 500 may include an offset voltage cancellation circuit 570, which is configured to substantially eliminate any offset between the output voltages V1+ and V1- generated by the aging replica circuit 540. Compared to the offset voltage cancellation circuit previously discussed, which can be implemented by current sources 458 and 459 of the unaged replica circuit 450, the offset voltage cancellation circuit 570 can perform offset voltage cancellation based on coarse (lower) resolution. As an example, the coarse offset cancellation circuit 570 can cancel an offset voltage of approximately 6.5 millivolts (mV) between V1+ and V1-; while the fine offset voltage cancellation, which can be implemented by current sources 458 and 459 of the unaged replica circuit 450, can cancel an offset voltage of approximately 1.25 mV between V2+ and V2-.

[0068] More specifically, the aging compensation circuit 500 includes an aging replica circuit 540 as described above, which includes a variable current source 542, input differential PMOS FET pairs M1 and M2, and differential output resistors R1 and R2. For offset calibration, a common-mode voltage VCM can be applied to the gates of the differential FET pairs M1 and M2.

[0069] The coarse offset cancellation circuit 570 includes a variable current source 572, input differential PMOS FET pairs M5 and M6, first and second multiplexers 574 and 576, offset control circuitry 580, and digital encoder 590. On the negative side, the current source 572 and PMOS FET M5 are coupled in series between the upper voltage rail Vdd and a node between the drain of PMOS FET M1 of the aging copy circuit 540 and the output resistor R1 (negative output). On the positive side, the current source 572 and PMOS FET M6 are coupled in series between the upper voltage rail Vdd and a node between the drain of PMOS FET M2 of the aging copy circuit 540 and the output resistor R2 (positive output).

[0070] The first multiplexer 574 includes first and second inputs configured to receive a disable voltage VDSB (e.g., Vdd or VCSO) and a common-mode voltage VCM, respectively. The first multiplexer 574 includes a selection input configured to receive a selection signal SEL A generated by the offset control circuit 580, and an output coupled to the gate of the PMOS FET M5. Similarly, the second multiplexer 576 includes first and second inputs configured to receive a disable voltage VDSB and a common-mode voltage VCM, a selection input configured to receive a selection signal SEL B generated by the offset control circuit 580, and an output coupled to the gate of the PMOS FET M6. Additionally, the offset control circuit 580 is configured to receive an offset code generated by the digital encoder 590 (which may be based on the difference between voltages V1+ and V1-), and to generate a current control signal or code DCS5 for the variable current source 572 based on this offset code.

[0071] The offset cancellation operation is as follows: The offset control circuit 580 receives an offset code from the digital encoder 590 and determines whether an offset exists between voltages V1+ and V1-. If the offset is positive as indicated by the offset code (meaning V1+ > V1-), the offset control circuit 580 sets the selection signal SEL A to deliver the common-mode voltage VCM to turn on PMOS FET M5, and sets the selection signal SEL B to deliver the disable voltage VDSB to turn off PMOS FET M6. Then, the offset control circuit 580 generates a current control code DCS5 to increase the current generated by the current source 572, thereby generating an additional current flowing through resistor R1; thus increasing V1- until it is substantially equal to V1+ as indicated by the offset code. If the offset is negative as indicated by the offset code (meaning V1+ < V1-), the offset control circuit 580 sets the selection signal SEL A to deliver the disable voltage VDSB to turn off PMOS FET M5, and sets the selection signal SEL B to deliver the common-mode voltage VCM to turn on PMOS FET M6. The offset control circuit 580 then generates a current control code DCS5 to increase the current generated by the current source 572, thereby producing an additional current flowing through resistor R2; this increases V1+ until it is substantially equal to V1- as indicated by the offset code.

[0072] Figure 6 shows a schematic diagram of a portion of an exemplary aging compensation circuit 600 according to another aspect of this disclosure. The aging compensation circuit 600 may include an offset voltage cancellation circuit 670, which is configured to substantially eliminate any offset between the output voltages V2+ and V2- generated by the unaged replica circuit 650. Compared to offset voltage cancellation that can be achieved through current sources 658 and 660 of the unaged replica circuit 650, the offset voltage cancellation circuit 670 can perform offset voltage cancellation based on coarse (lower) resolution. As an example, the coarse offset voltage cancellation circuit 670 can cancel an offset voltage of approximately 6.5 mV between V2+ and V2-; while the fine offset voltage cancellation that can be achieved through current sources 658 and 660 of the unaged replica circuit 650 can cancel an offset voltage of approximately 1.25 mV between V2+ and V2-.

[0073] More specifically, the aging compensation circuit 600 includes the unaged replica circuit 650 as described above. The unaged replica circuit 650 includes a variable current source 652, input differential PMOS FET pairs M3 and M4, differential output resistors R3 and R4, and a fine offset voltage calibration circuit including variable current sources 658 and 660. For coarse offset calibration, a common-mode voltage VCM can be applied to the gates of the differential FET pairs M3 and M4.

[0074] The coarse offset cancellation circuit 670 includes a variable current source 672, input differential PMOS FET pairs M7 and M8, first and second multiplexers 674 and 676, offset control circuitry 680, and digital encoder 690. On the negative side, the current source 672 and PMOS FET M7 are coupled in series between the upper voltage rail Vdd and a node between the drain of PMOS FET M3 of the unaged copy circuit 650 and the output resistor R3 (negative output). On the positive side, the current source 672 and PMOS FET M8 are coupled in series between the upper voltage rail Vdd and a node between the drain of PMOS FET M4 of the unaged copy circuit 650 and the output resistor R4 (positive output).

[0075] The first multiplexer 674 includes first and second inputs configured to receive a disable voltage VDSB (e.g., Vdd or VCSO) and a common-mode voltage VCM, respectively. The first multiplexer 674 includes a selection input configured to receive a selection signal SEL C generated by the offset control circuit 680, and an output coupled to the gate of the PMOS FET M7. Similarly, the second multiplexer 676 includes first and second inputs configured to receive a disable voltage VDSB and a common-mode voltage VCM, a selection input configured to receive a selection signal SEL D generated by the offset control circuit 680, and an output coupled to the gate of the PMOS FET M8. Additionally, the offset control circuit 680 is configured to receive an offset code generated by the digital encoder 690 (which may be based on the difference between voltages V2+ and V2-), and to generate a current control signal or code DCS6 for the variable current source 672 based on this offset code.

[0076] The offset cancellation operation is as follows: The offset control circuit 680 receives an offset code from the digital encoder 690 and determines whether an offset exists between voltages V2+ and V2-. If the offset is positive as indicated by the offset code (meaning V2+ > V2-), the offset control circuit 680 sets the selection signal SELC to deliver the common-mode voltage VCM to turn on PMOS FET M7, and sets the selection signal SELD to deliver the disable voltage VDSB to turn off PMOS FET M8. Then, the offset control circuit 680 generates a current control code DCS6 to increase the current generated by the current source 672, thereby generating an additional current flowing through resistor R3; thus increasing V2- until it is substantially equal to V2+ as indicated by the offset code. If the offset is negative as indicated by the offset code (meaning V2+ < V2-), the offset control circuit 680 sets the select signal SELC to deliver the disable voltage VDSB to turn off PMOS FET M7, and sets the select signal SELD to deliver the common-mode voltage VCM to turn on PMOS FET M8. The offset control circuit 680 then generates the current control code DCS6 to increase the current generated by the current source 672, thereby producing an additional current flowing through resistor R4; thus increasing V2+ until it is substantially equal to V2- as indicated by the offset code.

[0077] Figure 7 shows a flowchart of an exemplary method 700 for compensating for aging effects in a receiver according to another aspect of this disclosure. Method 700 includes providing a data signal and a clock signal to the receiver (block 710). Examples of components for providing the data signal and clock signal to the receiver include any of the transmitters and transmission media described herein.

[0078] Method 700 further includes, in an aging mode (block 720): providing an aging signal to a first replica circuit, which is a physical replica of the receiver, substantially while one of a data signal and a clock signal is provided to the receiver, wherein the aging signal causes the first replica circuit to operate substantially the same as or more heavily than one of the data signal and the clock signal (subblock 720A). Examples of components for providing the aging signal to the first replica circuit substantially while one of the data signal and the clock signal is provided to the receiver include aging control circuitry 140, VCO 240, and voltage level shifter or CML 340. Furthermore, method 700 includes keeping a second replica circuit disabled, which is a physical replica of the receiver (subblock 720B). Examples of components for keeping the second replica circuit disabled include a voltage generator and a multiplexer that apply a disable voltage VDSB to either of the unaged replica circuits.

[0079] Method 700 further includes, in calibration mode (block 730): enabling a second replica circuit (sub-block 730A). Examples of components for enabling the second replica circuit include either a voltage generator or a multiplexer that applies a common-mode voltage to either of the unaged replica circuits. Method 700 further includes stopping the supply of an aging signal to the first replica circuit (sub-block 730B). Examples of components for stopping the supply of an aging signal to the first replica circuit include multiplexers 150, 250, 350 and tri-state buffers 432 and 434. Furthermore, method 700 includes applying input voltages to the inputs of the first and second replica circuits, wherein the first and second replica circuits generate first and second output voltages based on the input voltages, respectively (sub-block 730C). Examples of components for applying input voltages to the inputs of the first and second replica circuits include either a voltage generator or a multiplexer that routes a common-mode voltage VCM to either of the aged and unaged replica circuits, respectively.

[0080] Furthermore, method 700 includes generating a compensation voltage (sub-block 730D) based on the difference between the first and second output voltages of the first and second replica circuits, respectively. Examples of components for generating the compensation voltage based on the difference between the first and second output voltages of the first and second replica circuits, respectively, include any of the comparators described herein. Method 700 also includes calibrating the receiver and the first replica circuit based on the compensation voltage (sub-block 730E). Examples of components for calibrating the receiver and the first replica circuit based on the compensation voltage include any of the calibration control circuits described herein.

[0081] Method 700 may further include applying an input voltage to the inputs of the first and second replica circuits in a startup mode, wherein the first and second replica circuits generate third and fourth output voltages, respectively, based on the input voltage. Examples of components for applying the input voltage to the first and second replica circuits include any of a voltage generator and a multiplexer that apply a common-mode voltage to either of the unaged replica circuits. Method 700 may additionally include applying a current to the second replica circuit to regulate the difference between the first and second output voltages. Examples of components for applying a current to the second replica circuit to regulate the difference between the first and second output voltages include a fine offset canceling current source. Furthermore, method 700 may also include calibrating at least one other receiver based on the difference between the first and second output voltages. Examples of components for calibrating at least one other receiver based on the difference between the first and second output voltages include any of the calibration control circuits described herein.

[0082] Figure 8 shows a block diagram of an exemplary automotive control system 800 according to another aspect of this disclosure. The automotive control system 800 includes an automatic control system (ACS) integrated circuit (IC) 810, such as a system-on-chip (SOC). The ACS SOC 810 includes a set of receivers RX-1 to RX-N and an aging compensation circuit 820. The aging compensation circuit 820 can be implemented according to any of the aging compensation circuits described herein. In this example, the aging compensation circuit 820 is coupled to receiver RX-1, for example, to receive a receiver enable signal VEN_RX according to aging compensation circuit 230, or to receive data or clock signals from an intermediate node or output of receiver RX-1 according to aging compensation circuit 330. As discussed above, the aging compensation circuit 820 is also coupled to the set of receivers RX-1 to RX-N to provide them with a broadcast aging control signal (AGING CS B).

[0083] The vehicle control system 800 also includes an ACS sensor 850, which includes a sensor data and clock source 860 and a set of transmitters TX-1 to TX-N. The sensor data and data clock source 860 are coupled to the set of transmitters TX-1 to TX-N to provide data signals and clock signals to the set of transmitters TX-1 to TX-N. The data signals may relate to different vehicle parameters (e.g., engine parameters, autonomous / assisted driving parameters, passenger comfort / entertainment parameters, etc.) that the ACS sensor 850 is configured to sense. The set of transmitters TX-1 to TX-N is coupled to the set of receivers RX-1 to RX-N via a set of transmission metallized lines 892-1 to 892-N formed on a printed circuit board (PCB) 890. The data / clock signals are transmitted from the set of transmitters TX-1 to TX-N to the set of receivers RX-1 to RX-N via the set of transmission lines 892-1 to 892-N, respectively. Although not shown, the ACS SOC 810 may include one or more data signal processing cores to process data signals from the ACS sensor 850 according to a specific automatic control application.

[0084] An overview of the various aspects of this disclosure will be provided below:

[0085] Sample 1: An apparatus comprising: a collection of one or more receivers; a first replica circuit that is a substantial replica of at least a portion of one of the receivers in the collection of one or more receivers; a first control circuit that generates an output signal selectively coupled to an input of the first replica circuit; a second replica circuit that is a substantial replica of at least a portion of one of the receivers in the collection of one or more receivers; a comparator that includes a first input coupled to a first output of the first replica circuit, a second input coupled to a second output of the second replica circuit, and an output; and a second control circuit that includes an input coupled to the output of the comparator, and an output coupled to the first replica circuit and coupled to the collection of one or more receivers.

[0086] State 2: The device of State 1, wherein the first control circuit includes an oscillator.

[0087] State 3: The device of State 1 or 2 further includes an enable signal coupled to the collection of the one or more receivers and coupled to the first control circuit.

[0088] State 4: Any of the states 1 to 3, further comprising a voltage generator including an output coupled to an input of the first replica circuit.

[0089] State 5: The device of State 4 further includes a multiplexer, which includes a first input coupled to the output of the first control circuit, a second input coupled to the output of the voltage generator, and an output coupled to the input of the first copy circuit.

[0090] State 6: A device of any one of States 1-5, wherein the first control circuitry includes an input coupled to the output of one of the collection of one or more receivers.

[0091] State 7: The device of State 6, wherein the first control circuit includes one of a voltage level shifter and a current mode logic (CML) circuit.

[0092] State 8: The device of State 7 further includes a voltage generator, which includes an output selectively coupled to the input of the first replica circuit.

[0093] State 9: The device of State 8 further includes a multiplexer, the multiplexer including a first input coupled to the output of one of the voltage level shifter and the CML circuit, a second input coupled to the output of the voltage generator, and an output coupled to the input of the first replica circuit.

[0094] State 10: The device of any one of States 1-9 further includes: a voltage generator including an output selectively coupled to an input of the second replica circuit; and a receiver disable signal selectively coupled to an input of the second replica circuit.

[0095] State 11: The device of State 10 further includes a multiplexer, the multiplexer including a first input coupled to the output of the voltage generator, a second input coupled to the output of the receiver disable signal, and an output coupled to the input of the second copy circuit.

[0096] State 12: A device of any one of States 1-11, wherein: the first replica circuit includes a first current source, a first field-effect transistor (FET) and a first resistor coupled in series between a first voltage rail and a second voltage rail; and the second replica circuit includes a second current source, a second FET and a second resistor coupled in series between the first voltage rail and the second voltage rail.

[0097] State 13: The device of State 12, wherein the output of the second control circuit is coupled to the first and second current sources of the first and second replica circuits, respectively.

[0098] State 14: The device of State 13, wherein the second control circuit includes: a digital encoder; and a first controller, the first controller including an input coupled to the output of the digital encoder, a first output coupled to a first current source coupled to a first copy circuit, and a second output coupled to a set of one or more corresponding current sources coupled to the set of one or more receivers.

[0099] State 15: The device of State 14, wherein the second control circuit further includes a second controller, the second controller including an input selectively coupled to a first output of the first controller and an output of a second current source coupled to the second replica circuit.

[0100] State 16: A device of any one of States 12-15, further comprising a second current source coupled to the second replica circuit and a receiver disable signal of the second FET.

[0101] State 17: A device of any one of States 12-16, wherein the second replica circuit includes a third current source coupled between the first voltage rail and the second resistor.

[0102] State 18: The device of any one of States 12-17 further includes: a first offset cancellation circuit coupled to a first node between a first FET and a first resistor of a first replica circuit; and a second offset cancellation circuit coupled to a second node between a second FET and a second resistor of a second replica circuit.

[0103] State 19: The device of State 18 further includes a voltage generator coupled to the first and second offset cancellation circuits.

[0104] State 20: A device of any one of States 1-19, wherein: the first replica circuit includes a first current source, a differential pair of a first field-effect transistor (FET), and a first resistor pair, respectively coupled in series between a first voltage rail and a second voltage rail; the second replica circuit includes a second current source, a differential pair of a second FET, and a second resistor pair, respectively coupled in series between the first voltage rail and the second voltage rail; and the comparator includes: a first multiplexer including first and second inputs respectively coupled to one of the resistors in the first and second resistor pairs; a second multiplexer including first and second inputs respectively coupled to the other resistor in the first and second resistor pairs; and a differential amplifier including inputs respectively coupled to the outputs of the first and second multiplexers.

[0105] State 21: A method comprising: providing a receiver with one of a data signal and a clock signal; in an aging mode: substantially providing an aging signal to a first replica circuit, which is a substantial replica of the receiver, while the data signal and the clock signal are substantially provided to the receiver, wherein the aging signal causes the first replica circuit to operate substantially the same as or more heavily than the data signal and the clock signal, and keeping a second replica circuit disabled, which is a substantial replica of the receiver; in a calibration mode: enabling the second replica circuit, stopping the provision of the aging signal to the first replica circuit, applying input voltages to inputs of the first and second replica circuits, wherein the first and second replica circuits generate first and second output voltages based on the input voltages, respectively, generating a compensation voltage based on the difference between the first and second output voltages of the first and second replica circuits, respectively, and calibrating the receiver and the first replica circuit based on the difference between the first and second output voltages.

[0106] State 22: The method of State 21, wherein the aging signal includes an oscillation signal having a frequency that is within or higher than one of the data rate of the data signal and the frequency of the clock signal.

[0107] State 23: The method of state 21 or 22, wherein the aging signal is based on one of a data signal and a clock signal.

[0108] Form 24: An apparatus comprising: means for providing a data signal and a clock signal to a receiver; in an aging mode: means for providing an aging signal to a first replica circuit, which is a substantial replica of the receiver, substantially simultaneously with the provision of the data signal and the clock signal to the receiver, wherein the aging signal causes the first replica circuit to operate substantially the same as or more heavily than the provision of the data signal and the clock signal to the receiver; and means for keeping a second replica circuit disabled, which is a substantial replica of the receiver; in a calibration mode: means for enabling the second replica circuit; means for stopping the provision of the aging signal to the first replica circuit; means for applying an input voltage to the inputs of the first and second replica circuits, wherein the first and second replica circuits generate first and second output voltages based on the input voltages, respectively; means for generating a compensation voltage based on the difference between the first and second output voltages of the first and second replica circuits, respectively; and means for calibrating the receiver and the first replica circuit based on the difference between the first and second output voltages.

[0109] State 25: The device of State 24, wherein the aging signal includes an oscillation signal having a frequency that is within or higher than one of the data rate of the data signal and the frequency of the clock signal.

[0110] State 26: The device of state 24 or 25, wherein the aging signal is based on one of the data signal and the clock signal.

[0111] Form 27: An automotive control system, comprising: a set of automotive control signal transmitters; a set of automotive control signal receivers coupled to the set of automotive control signal transmitters via a set of transmission lines; and an aging compensation circuit, the aging compensation circuit comprising: a first replica circuit being a substantial replica of one of the receivers in the set of automotive control signal receivers; a first control circuit including an output selectively coupled to an input of the first replica circuit; a second replica circuit being a substantial replica of one of the receivers in the set of automotive control signal receivers; a comparator including a first input coupled to a first output of the first replica circuit and a second input coupled to a second output of the second replica circuit; and a second control circuit including an input coupled to the output of the comparator and an output coupled to the first replica circuit and coupled to the set of automotive control signal receivers.

[0112] State 28: The vehicle control system of State 27, wherein the first control circuit includes an oscillator.

[0113] State 29: The vehicle control system of State 27 or 28, wherein the first control circuit includes an input to the output of one of a set of one or more receivers.

[0114] State 30: The vehicle control system of any one of States 27-29, wherein the set of vehicle control signal transmitters and the set of vehicle control signal receivers are part of a low power double data rate (LPDDR) interface.

[0115] The foregoing description of this disclosure is provided to enable anyone skilled in the art to make or use it. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit and scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but rather to be given the widest scope consistent with the principles and novel features disclosed herein. [Simplified Explanation of the Diagram]

[0011] Figure 1 shows a block diagram of an exemplary device including an exemplary aging compensation circuit according to one aspect of the present disclosure.

[0012] Figure 2 shows a block diagram of another exemplary device including another exemplary aging compensation circuit according to another aspect of this disclosure.

[0013] Figure 3 shows a block diagram of yet another exemplary device including yet another exemplary aging compensation circuit according to another aspect of the present disclosure.

[0014] Figure 4 shows a schematic diagram of an exemplary aging compensation circuit according to another aspect of this disclosure.

[0015] Figure 5 shows a schematic diagram of a portion of an exemplary aging compensation circuit according to another aspect of this disclosure.

[0016] Figure 6 shows a schematic diagram of another portion of an exemplary aging compensation circuit according to another aspect of this disclosure.

[0017] Figure 7 shows a flowchart of an exemplary method for compensating for aging effects according to another aspect of this disclosure.

[0018] Figure 8 shows a block diagram of an exemplary vehicle control system according to another aspect of this disclosure.

Claims

1. An apparatus for a circuit element, comprising: A collection of one or more receivers; A first replica circuit, the first replica circuit being a substantial replica of at least a portion of one of the one or more receivers; a first control circuit, the first control circuit generating an output signal selectively coupled to an input of the first replica circuit, wherein the first control circuit includes an input coupled to an output of one of the one or more receivers; A second replica circuit, the second replica circuit being a substantial replica of at least a portion of one of the one or more receivers; a comparator, the comparator including a first input coupled to a first output of the first replica circuit, a second input coupled to a second output of the second replica circuit, and an output; and a second control circuit, the second control circuit including an input coupled to the output of the comparator, and an output coupled to the first replica circuit and coupled to the one or more receivers.

2. The device as claimed in claim 1, wherein the first control circuitry includes an oscillator.

3. The device as claimed in claim 1 further includes an enable signal coupled to a set of the one or more receivers and coupled to the first control circuitry.

4. The device as claimed in claim 1 further includes a voltage generator, the voltage generator including an output coupled to the input of the first replica circuit.

5. The device as claimed in claim 4 further includes a multiplexer, the multiplexer including a first input coupled to the output of the first control circuit, a second input coupled to the output of the voltage generator, and an output coupled to the input of the first copy circuit.

6. The device as claimed in claim 1, wherein the first control circuitry includes one of a voltage level shifter and a current-mode logic (CML) circuitry.

7. The device as claimed in claim 6 further includes a voltage generator, the voltage generator including an output selectively coupled to the input of the first replica circuit.

8. The device as claimed in claim 7 further includes a multiplexer, the multiplexer including a first input coupled to the output of one of the voltage level shifter and the CML circuit, a second input coupled to the output of the voltage generator, and an output coupled to the input of the first copy circuit.

9. The device as described in claim 1, further comprising: A voltage generator, including an output selectively coupled to the input of the second replica circuit; And a receiver disable signal, selectively coupled to the input of the second replica circuit.

10. The device of claim 9 further includes a multiplexer, the multiplexer including a first input coupled to the output of the voltage generator, a second input coupled to the output of the receiver disable signal, and an output coupled to the input of the second copy circuit.

11. The device as claimed in claim 1, wherein: The first replica circuit includes a first current source, a first field-effect transistor (FET), and a first resistor, all coupled in series between a first voltage rail and a second voltage rail; and the second replica circuit includes a second current source, a second FET, and a second resistor, all coupled in series between the first voltage rail and the second voltage rail.

12. The device of claim 11, wherein the output of the second control circuit is coupled to the first current source and the second current source of the first copy circuit and the second copy circuit, respectively.

13. The device as claimed in claim 12, wherein the second control circuitry comprises: Digital encoder; And a first controller, the first controller including an input coupled to the output of the digital encoder, a first output coupled to the first current source of the first copy circuit, and a second output coupled to a set of one or more corresponding current sources of the set of one or more receivers.

14. The device of claim 13, wherein the second control circuitry further comprises a second controller, the second controller including an input coupled to the output of the digital encoder and an output of the second current source coupled to the second copy circuitry.

15. The device of claim 11 further includes a receiver disable signal coupled to the second current source and the second FET of the second replica circuit.

16. The device as claimed in claim 11, wherein the second copy circuit includes a third current source coupled between the first voltage rail and the second resistor.

17. The device as claimed in claim 11, further comprising: A first offset cancellation circuit is coupled to a first node between the first FET and the first resistor of the first replica circuit. And a second offset cancellation circuit, the second offset cancellation circuit being coupled to a second node between the second FET and the second resistor of the second replica circuit.

18. The device as claimed in claim 17 further includes a voltage generator coupled to the first offset cancellation circuit and the second offset cancellation circuit.

19. The device as claimed in claim 1, wherein: The first replica circuit includes a first current source, a first differential pair of field-effect transistors (FETs), and a first resistor pair, all connected in series between a first voltage rail and a second voltage rail; and the second replica circuit includes a second current source, a second differential pair of FETs, and a second resistor pair, all connected in series between the first voltage rail and the second voltage rail; and the comparator includes: a first multiplexer, including a first input and a second input coupled to one resistor in the first resistor pair and one resistor in the second resistor pair; a second multiplexer, including a first input and a second input coupled to the other resistor in the first resistor pair and the other resistor in the second resistor pair; and a differential amplifier, including inputs coupled to the outputs of the first multiplexer and the second multiplexer.

20. A method for using a circuit element, comprising: Provide the receiver with one of a data signal and a clock signal; In aging mode: While one of the data signal and clock signal is provided to the receiver, a first control circuit provides an aging signal to a first replica circuit, wherein the first control circuit includes an input coupled to the output of the receiver, the first replica circuit being a physical replica of the receiver, wherein the aging signal causes the first replica circuit to operate substantially the same as, or more heavily than, the receiver, as the data signal and clock signal. And keep the second copy circuit disabled, the second copy circuit being a physical copy of the receiver; In calibration mode: Enable the second copy circuit; Stop providing the aging signal to the first copy circuit; An input voltage is applied to the input of the first copy circuit and the input of the second copy circuit, wherein the first copy circuit and the second copy circuit generate a first output voltage and a second output voltage respectively based on the input voltage; a compensation voltage is generated based on the difference between the first output voltage and the second output voltage of the first copy circuit and the second copy circuit respectively. And based on the compensation voltage, calibrate the receiver and the first copy circuit.

21. The method of claim 20, wherein the aging signal includes an oscillation signal having a frequency that is within the range of or higher than either the data rate of the data signal or the frequency of the clock signal.

22. The method of claim 20, wherein the aging signal is based on one of the data signal and the clock signal.

23. An apparatus for a circuit element, comprising: A component used to provide a receiver with either a data signal or a clock signal; In aging mode: Components for providing an aging signal to a first replica circuit while substantially one of the data signal and clock signal is provided to the receiver, wherein the components for providing the aging signal to the first replica circuit include an input coupled to the output of the receiver, the first replica circuit being a substantial replica of the receiver, wherein the aging signal causes the first replica circuit to operate substantially the same as, or more heavily than, the receiver, as the data signal and clock signal. And components for keeping the second replica circuit disabled, the second replica circuit being a physical replica of the receiver; In calibration mode: components for enabling the second replica circuit; components for stopping the supply of the aging signal to the first replica circuit; components for applying input voltages to the inputs of the first replica circuit and the second replica circuit, wherein the first replica circuit and the second replica circuit generate a first output voltage and a second output voltage, respectively, based on the input voltages; components for generating a compensation voltage based on the difference between the first output voltage and the second output voltage of the first replica circuit and the second replica circuit, respectively; And components for calibrating the receiver and the first copy circuit based on the difference between the first output voltage and the second output voltage.

24. The device of claim 23, wherein the aging signal comprises an oscillation signal having a frequency that is within the range of or higher than either the data rate of the data signal or the frequency of the clock signal.

25. The device as claimed in claim 23, wherein the aging signal is based on one of the data signal and the clock signal.

26. A vehicle control system, comprising: A collection of automotive control signal transmitters; A set of vehicle control signal receivers is coupled to a set of vehicle control signal transmitters via a set of transmission lines; The aging compensation circuit includes: a first replica circuit, which is a substantial replica of one of the receivers in the set of vehicle control signal receivers; a first control circuit, including an output selectively coupled to an input of the first replica circuit, wherein the first control circuit includes an input coupled to an output of one of the receivers in the set of one or more receivers; a second replica circuit, which is a substantial replica of one of the receivers in the set of vehicle control signal receivers; a comparator, including a first input coupled to a first output of the first replica circuit and a second input coupled to a second output of the second replica circuit; and a second control circuit, including an input coupled to an output of the comparator and an output coupled to the first replica circuit and coupled to the set of vehicle control signal receivers.

27. The vehicle control system as claimed in claim 26, wherein the first control circuit includes an oscillator.

28. The vehicle control system of claim 26, wherein the set of vehicle control signal transmitters and the set of vehicle control signal receivers are part of a low power double data rate (LPDDR) interface.

Images