Semiconductor device and method of manufacturing the semiconductor device

Abstract

This disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes: a stacked structure comprising a plurality of alternately stacked interlayer insulating layers and a plurality of gate conductive layers; a channel plug that at least partially extends through the stacked structure over a cell region; and a plurality of support structures that at least partially extend through the stacked structure over a contact region.

Description

[Technical Field]

[0001] This disclosure relates to an electronic device, and more specifically, to a semiconductor device and a method of manufacturing the semiconductor device. Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0077473, filed on June 15, 2021, which is incorporated herein by reference in its entirety. [Previous Technology]

[0003] Non-volatile memory elements are memory elements that can retain stored data even when the power is cut off. In recent years, as the integration of two-dimensional non-volatile memory elements that form memory cells in a single layer on a substrate has reached its limit, three-dimensional non-volatile memory elements that vertically stack memory cells on a substrate have been proposed.

[0004] A three-dimensional non-volatile memory element comprises alternating stacked interlayer insulating layers and gate electrodes, and channel layers passing through the interlayer insulating layers and gate electrodes, with memory cells stacked along the channel layers. To improve the reliability of non-volatile memory elements having this three-dimensional structure, various structures and manufacturing methods have been developed. [Summary of the Invention]

[0005] According to embodiments of this disclosure, a semiconductor device may include: a stacked structure comprising a plurality of alternately stacked interlayer insulating layers and a plurality of gate conductive layers; a channel plug that at least partially passes through the stacked structure over a cell region; and a plurality of support structures that at least partially pass through the stacked structure over a contact region. The plurality of support structures include a linear first support structure and a via-type second support structure.

[0006] According to embodiments of the present disclosure, a semiconductor device may include: a stacked structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers stacked alternately; a first channel plug and a second channel plug formed on a cell region by perpendicularly passing through a portion or all of the stacked structure; a plurality of support structures formed on a contact region by perpendicularly passing through a portion or all of the stacked structure; and an auxiliary support structure disposed on the stacked structure and the plurality of support structures.

[0007] According to embodiments of this disclosure, a method of manufacturing a semiconductor device may include: forming a stacked structure in which a plurality of interlayer insulating layers and a plurality of sacrificial layers are alternately stacked on a substrate including cell regions and contact regions; etching the stacked structure on the contact regions to together form a first hole for forming a contact plug through a portion or all of the stacked structure, a trench for forming a first support structure, and a second hole for forming a second support structure; forming a contact plug by filling the first hole with a barrier layer and a conductive layer; filling the trench and the second hole with the barrier layer and the conductive layer; forming an auxiliary support structure on the stacked structure, the auxiliary support structure including a plurality of opening regions overlapping a portion of the trench and a portion of the second hole; removing the barrier layer and the conductive layer for gates retained in the trench and the second hole exposed through the plurality of opening regions of the auxiliary support structure; and forming the first support structure and the second support structure by filling the trench and the second hole with an insulating layer.

Implementation Method

[0018] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are shown only to describe embodiments based on the concepts disclosed herein. Embodiments based on the concepts disclosed herein may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0019] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0020] Embodiments of this disclosure provide a semiconductor device having a stable structure and improved characteristics, as well as a method for manufacturing the semiconductor device.

[0021] According to this technology, a semiconductor device with a stable structure can be manufactured, and thus the characteristics of the semiconductor device can be improved.

[0022] Figures 1A and 1B are block diagrams schematically illustrating a semiconductor device according to an embodiment of the present disclosure.

[0023] Referring to Figures 1A and 1B, each of the semiconductor devices according to embodiments of the present disclosure may include a peripheral circuit structure PC and a cell array CAR disposed on a substrate SUB.

[0024] The substrate SUB can be a single-crystal semiconductor layer. For example, the substrate SUB can be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin layer formed by selective epitaxial growth.

[0025] The cell array (CAR) may include multiple memory blocks. Each memory block may include multiple cell strings. Each cell string is electrically connected to a bit line, a source line, a word line, and a select line. Each cell string may include a memory cell and a select transistor connected in series. Each select line is used as the gate electrode of its corresponding select transistor, and each word line is used as the gate electrode of its corresponding memory cell.

[0026] The surrounding circuit structure PC may include NMOS and PMOS transistors, resistors, and capacitors electrically connected to the cell array CAR. The NMOS and PMOS transistors, resistors, and capacitors may be used as elements for configuring the row decoder, column decoder, page buffer, and control circuitry.

[0027] As shown in Figure 1A, the surrounding circuit structure PC can be set on a portion of the substrate SUB that does not overlap with the cell array CAR.

[0028] Alternatively, as shown in FIG1B, the surrounding circuit structure PC can be disposed between the cell array CAR and the substrate SUB. In this case, since the surrounding circuit structure PC overlaps with the cell array CAR, the area of ​​the substrate SUB occupied by the cell array CAR and the surrounding circuit structure PC can be reduced.

[0029] Figure 2 is a schematic cross-sectional view showing the surrounding circuit structure.

[0030] The peripheral circuit structure PC shown in Figure 2 can be included in the peripheral circuit structure shown in Figure 1A, or it can be included in the peripheral circuit structure shown in Figure 1B.

[0031] Referring to Figure 2, the peripheral circuit structure PC may include a peripheral gate electrode PEG, a peripheral gate insulating layer PGI, a junction Jn, a peripheral circuit line PCL, and a peripheral contact plug PCP. The peripheral circuit structure PC may be covered by a peripheral circuit insulating layer PIL formed on a substrate SUB.

[0032] Each of the peripheral gate electrodes PEG can be used as the gate electrode of the NMOS transistor and PMOS transistor of the peripheral circuit structure PC. The peripheral gate insulating layer PGI is disposed between each of the peripheral gate electrodes PEG and the substrate SUB.

[0033] The junction Jn is a region defined by implanting an n-type or p-type impurity into the active region of the substrate SUB. The junction Jn is disposed on both sides of each of the surrounding gate electrodes PEG and serves as a source junction or a drain junction. The active region of the substrate SUB can be separated by a separator layer ISO formed in the substrate SUB. The separator layer ISO is formed of an insulating material.

[0034] The peripheral circuit line PCL can be electrically connected to the transistors, resistors and capacitors of the circuit that constitute the peripheral circuit structure PC through the peripheral contact plug PCP.

[0035] The surrounding circuit insulation layer (PIL) may include multiple layers of stacked insulation layers.

[0036] Figures 3A to 3D are plan views and cross-sectional views of a semiconductor device according to an embodiment of the present disclosure.

[0037] Referring to FIG. 3A, the cell array CAR of FIG. 1A and FIG. 1B of the semiconductor device may include cell regions and contact regions CT. Multiple channel plugs CP1 and CP2 may be regularly arranged on the cell regions. Additionally, a linear first vertical structure VS1 disposed between the multiple channel plugs CP1 and CP2 may be disposed in the central portion of the cell region, and a second vertical structure VS2 may be disposed at both ends of the cell region. The multiple channel plugs CP1 and CP2 may be arranged between the second vertical structures VS2. Each of the multiple channel plugs CP1 and CP2 may include a channel layer 112 and a memory layer 111 surrounding the channel layer 112. The first vertical structure VS1 and the second vertical structure VS2 may be insulating layers and may be formed of, for example, an oxide layer.

[0038] Multiple contact plugs CT1 and CT2 can be regularly arranged on the contact area CT. Additionally, at least one support structure 119 and a second vertical structure VS2 can be arranged in the space between the multiple contact plugs CT1 and CT2 on the contact area CT. The support structure 119 can be formed of the same material as the first vertical structure VS1. The support structure 119 can be an insulating layer and can be formed of, for example, an oxide layer. The support structure 119 can include a linear first support structure 119A and a second support structure 119B, and a hole-shaped third support structure 119C. The width X1 of the first support structure 119A can be wider than the width X2 of the second support structure 119B. That is, the support structure 119 can include linear support structures and hole-shaped support structures with different widths. The linear first support structure 119A and second support structure 119B, and the hole-shaped third support structure 119C are arranged parallel to the second vertical structure VS2 and do not intersect or overlap each other.

[0039] Referring to Figure 3B, cross section A-A' is the cross section of the unit region, while cross section B-B' is the cross section of the contact region CT.

[0040] On a cell region of a semiconductor device, a source line layer 101, a stacked structure SS stacked on the source line layer 101, channel plugs CP1 and CP2 that contact the source line layer 101 by passing through part or all of the stacked structure SS in a vertical direction, a second vertical structure VS2 that is vertically disposed at both ends of the stacked structure SS and contacts the source line layer 101, and a first vertical structure VS1 that is disposed by passing through the portion of the stacked structure SS disposed between the channel plugs CP1 and CP2.

[0041] The source line layer 101 may be a doped semiconductor layer. For example, the source line layer 101 may be a semiconductor layer doped with an n-type impurity. As an embodiment, the source line layer 101 may be formed by implanting an impurity into the surface of the substrate SUB shown in FIG. 1A, or by depositing at least one doped silicon layer on the substrate SUB. As an embodiment, the source line layer 101 may be formed by forming an insulating layer on the surrounding circuit structure PC shown in FIG. 1B, and then depositing at least one doped silicon layer on the insulating layer.

[0042] The stacked structure SS may include a structure in which multiple gate conductive layers 123 and interlayer insulating layers 105 are alternately stacked, and in some embodiments, it has a structure in which the interlayer insulating layers 105 are disposed at the bottommost and topmost ends of the stacked structure SS. At least one gate conductive layer disposed at the bottommost end of the gate conductive layer 123 may be a source select line SSL, at least one gate conductive layer disposed at the topmost end of the gate conductive layer 123 may be a drain select line DSL, and the remaining gate conductive layers may be word lines WL.

[0043] Channel plugs CP1 and CP2 can be arranged vertically through the stacked structure SS and can include a channel layer 112 and a memory layer 111 surrounding the channel layer 112.

[0044] The first vertical structure VS1 may be configured to pass through at least one gate conductive layer 123 serving as the drain select line DSL, and is disposed at the uppermost portion of the stacked structure SS disposed between the channel plugs CP1 and CP2. That is, the first vertical structure VS1 electrically separates the gate conductive layer 123 for connecting the drain select line DSL to the first channel plug CP1 from the gate conductive layer 123 for connecting the drain select line DSL to the second channel plug CP2.

[0045] The contact area CT of the semiconductor device may include and be configured with a source line layer 101, a contact pad layer 103, an insulating layer 102 disposed between the source line layer 101 and the contact pad layer 103, a stacked structure SS stacked on the insulating layer 102 and the contact pad layer 103, contact plugs CT1 and CT2 that contact the contact pad layer 103 by passing through part or all of the stacked structure SS in the vertical direction, a second vertical structure VS2 that contacts the source line layer 101 by passing through part or all of the stacked structure SS in the vertical direction, and at least one support structure 119.

[0046] The source line layer 101 and the contact pad layer 103 are formed on the same layer, and are electrically separated from each other by an insulating layer 102 disposed between them. The insulating layer 102 may be formed of an insulating layer, such as an oxide layer. The contact pad layer 103 may be electrically connected to the surrounding circuit structure PC shown in Figures 1A and 1B.

[0047] Each of the contact plugs CT1 and CT2 may include a conductive layer 116 for the contact plug and a barrier layer 115 surrounding the conductive layer 116 for the contact plug. The barrier layer 115 may also be formed on the sidewall of the support structure 119.

[0048] Figures 3C and 3D are plan and cross-sectional views of a semiconductor device, showing the structure in which the auxiliary support structure 117 is disposed on the stacked structure SS of the contact area CT of the semiconductor device shown in Figures 3A and 3B.

[0049] Referring to Figures 3C and 3D, the auxiliary support structure 117 can be disposed on the stacked structure SS and the support structure 119 formed in the contact region CT of the semiconductor device. The auxiliary support structure 117 can have multiple opening regions OP, and the multiple opening regions OP can overlap with the support structure 119. For example, the multiple opening regions OP can be configured to overlap with the first support structure 119A, the second support structure 119B, and the third support structure 119C. The multiple opening regions OP can have a dash structure. The auxiliary support structure 117 can be formed as a mesh structure. The multiple opening regions OP can be configured as a matrix structure. At least one of the multiple opening regions OP can be configured to overlap with the first support structure 119A. At least one of the multiple opening regions OP can be configured to overlap with the second support structure 119B. At least one of the multiple third support structures 119C can overlap with one opening region OP. That is, at least one third support structure 119C can overlap with one opening region OP.

[0050] The auxiliary support structure 117 may include the same material as the mask pattern used to form the first vertical structure VS1 of FIG3A and FIG3B formed on the cell region of the semiconductor device.

[0051] In the semiconductor device according to the embodiments of the present disclosure described above, a support structure 119 for supporting the stacked structure SS can be provided in the contact region CT, and the support structure 119 is formed of a linear and hole-type structure. Therefore, in some embodiments, the problem of the support structure 119 expanding and tilting in one direction due to heat generated during subsequent processes can be suppressed. In addition, in some embodiments, by forming an auxiliary support structure 117 on the support structure 119, the expansion of the upper portion of the support structure 119 can be suppressed.

[0052] Figures 4 to 11 are cross-sectional and plan views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0053] Referring to FIG4, a source line layer 101 is formed on the cell region and contact region CT of the semiconductor device. The source line layer 101 may be a doped semiconductor layer, for example, a semiconductor layer doped with n-type impurities. As an embodiment, the source line layer 101 may be formed by implanting impurities into the surface of the substrate SUB shown in FIG1A, or by depositing at least one doped silicon layer on the substrate SUB. As an embodiment, the source line layer 101 may be formed by forming an insulating layer on the surrounding circuit structure PC shown in FIG1B, and then depositing at least one doped silicon layer on the insulating layer.

[0054] Subsequently, a portion of the source line layer 101 formed on the contact region CT is etched to form a region in which a contact pad layer is to be formed. The region in which the contact pad layer is to be formed can be defined as a region electrically connected to the surrounding circuit structure PC shown in Figures 1A and 1B. Thereafter, a contact pad layer 103 is formed in the portion of the etched and removed source line layer 101. An insulating layer 102 is formed between the contact pad layer 103 and the source line layer 101 to electrically separate the contact pad layer 103 and the source line layer 101. The insulating layer 102 can be formed of an insulating layer, such as an oxide layer.

[0055] Subsequently, stacks 105 and 107 are formed on the cell region and the contact region CT, wherein a first material layer 105 and a second material layer 107 are alternately stacked. The second material layer 107 may be used to form conductive layers such as character lines, select lines and pads, and the first material layer 105 may be used to insulate the stacked conductive layers from each other.

[0056] The first material layer 105 is formed of a material having high etch selectivity relative to the second material layer 107. For example, the first material layer 105 may include an insulating material such as an oxide, and the second material layer 107 may include a sacrificial material such as a nitride.

[0057] Referring to Figures 5A and 5B, a first masking pattern 109 is formed on the stacks 105 and 107 of the cell region and the contact region CT. The first masking pattern 109 is formed such that the portion of the cell region to be formed with a channel plug has a first opening OP1.

[0058] Referring to Figures 6A and 6B, stacks 105 and 107 are etched using a first masking pattern as a barrier to form a first hole H1 through a portion or all of stacks 105 and 107. At this time, the contact area CT is not etched due to the first masking pattern, and therefore no hole is formed.

[0059] Afterwards, remove the first mask pattern.

[0060] Subsequently, channel plugs CP1 and CP2, comprising a channel layer 112 and a memory layer surrounding the channel layer 112, are formed in the first hole H1. For example, a memory layer 111 is formed on the sidewall of the first hole H1. The memory layer 111 may include at least one of a charge blocking layer, a data memory layer, and a tunneling insulating layer, and the data memory layer may include a floating gate such as silicon, a charge trapping material such as nitride, a phase change material, nanodots, etc. Subsequently, channel plugs CP1 and CP2 are formed by completely filling the first hole H1 with the channel layer 112 up to the central region. As another embodiment, the channel layer 112 may be formed in a structure in which the central region of the first hole H1 is open, and a gap filling layer may be formed in the open central region.

[0061] Subsequently, a second masking pattern 113 is formed on the channel plugs CP1 and CP2 of the cell region and on the stacks 105 and 107 of the contact region CT. The second masking pattern 113 is formed such that the portion of the contact plug to be formed and the portion of the support structure to be formed in the contact region CT have second openings OP21 to OP24. For example, the second opening OP21 corresponding to the contact plug may have a hole shape, while the second openings OP22 and OP23 corresponding to the support structure may have a line shape. The widths X1 and X2 of the line-shaped second openings OP22 and OP23 may be different from each other.

[0062] In the embodiments of this disclosure, an example is described in which the support structure is formed as a line and the quadrilateral structure is a hole. However, this disclosure is not limited to this, and the support structure can be formed in various patterns, such as circles, ellipses, rhombuses, etc.

[0063] Referring to Figure 7, a second masking pattern is used as a barrier to etch the stacks 105 and 107 on the contact area CT to form a second hole H2 and a third hole H3 passing through part or all of the stacks 105 and 107, as well as a linear first trench T1 and a second trench T2. At this time, the second masking pattern prevents or mitigates the etching of the cell region. The widths of the first trench T1 and the second trench T2 can be different from each other.

[0064] After this, the second mask pattern can be removed.

[0065] Subsequently, a barrier layer 115 is formed on the sidewall of the second hole H2, and contact plugs CT1 and CT2 connected to the contact pad layer 103 are formed by filling the interior of the second hole H2 with the conductive layer 116 of the contact plugs. At this time, the barrier layer 115 and the conductive layer 116 for the contact plugs can be formed inside the third hole H3 and the linear first trench T1 and second trench T2.

[0066] Referring to Figures 8A and 8B, an auxiliary support structure 117 is formed on the channel plugs CP1 and CP2 of the cell region and on the stacks 105 and 107, and on the contact plugs CT1 and CT2 of the contact region CT and on the stacks 105 and 107. The auxiliary support structure 117 can be used as a third mask pattern for forming the first vertical structure. The auxiliary support structure 117 is formed with a third opening OP3, in which a portion of the region between the channel plugs CP1 and CP2 in the cell region and the region where the support structure of the contact region CT is to be formed are opened. That is, the auxiliary support structure 117 is formed with a third opening OP3, through which a portion of the region where the first vertical structure between the channel plugs CP1 and CP2 is to be formed and a portion of the region where the support structure is to be formed are opened. The third opening OP3 of the region where the first vertical structure is to be formed can be formed as a line, as shown in Figure 8B.

[0067] The auxiliary support structure 117 formed on the contact area CT can be formed as a mesh structure. That is, the third opening OP3 on the contact area CT can be configured as a matrix structure. Each of the third openings OP3 on the contact area CT can have a baffle structure. Each of the third openings OP3 on the contact area CT can be configured to overlap with the first groove T1 where the first support structure is to be formed, the second groove T2 where the second support structure is to be formed, and the third hole H3 where the third support structure is to be formed. At least one of the third openings OP3 on the contact area CT can be configured to overlap part or all of the first groove T1, at least one of the third openings OP3 on the contact area CT can be configured to overlap part or all of the second groove T2, and at least one of the third openings OP3 on the contact area CT can be configured to overlap part or all of at least one of the plurality of third holes H3. That is, at least one third hole H3 can overlap with one third opening OP3.

[0068] Referring to FIG9, an auxiliary support structure 117 is used as a mask pattern to etch a portion of the upper end of the stacks 105 and 107 formed between the channel plugs CP1 and CP2 of the cell region to form a first slit, and an insulating layer is filled in the first slit to form a first vertical structure VS1. The first vertical structure VS1 is formed to pass through at least one second material layer 107 disposed at the uppermost end of the drain selection line to be formed on the stacks 105 and 107.

[0069] Subsequently, in the contact area CT, the conductive layer 116 and barrier layer 115 formed in the first trench, second trench, and third hole exposed through the third opening OP3 of FIG8A and FIG8B through the auxiliary support structure 117 are removed. Then, an insulating layer is filled in the first trench, second trench, and third hole to form the first support structure 119A, second support structure 119B, and third support structure 119C.

[0070] The process of removing the conductive layer 116 and barrier layer 115 for the contact plug described above can be performed after the etching process in which the first slit is formed in the cell region using the auxiliary support structure 117 as a mask pattern. Additionally, the process of filling the insulating layer in the first trench, second trench, and third hole can be performed together with the process of filling the insulating layer in the first slit. The first vertical structure VS1 and the support structure 119 can be formed of an oxide layer.

[0071] Referring to FIGS. 10A and 10B, a fourth masking pattern 121 is formed on the auxiliary support structure 117 of the cell region and the contact region CT. The fourth masking pattern 121 is formed with a fourth opening OP4, through which the area between the two ends of the placement area of ​​the channel plugs CP1 and CP2 in the cell region and the area between the support structure 119 of the contact region CT is opened. That is, the fourth masking pattern 121 is formed with a fourth opening OP4, through which the area where the second vertical structure is to be formed at the two ends of the placement area of ​​the channel plugs CP1 and CP2 and the area between the support structure 119 where the second vertical structure is to be formed are opened. The fourth opening OP4 of the area where the second vertical structure is to be formed can be formed as a line as shown in FIG. 10B, and can be set to be parallel or perpendicular to each other. In addition, according to the embodiment, the fourth opening OP4 can be formed in various shapes.

[0072] Subsequently, the auxiliary support structures 117 and stacks 105 and 107 of FIG9 formed at both ends of the placement areas of the channel plugs CP1 and CP2 in the cell region are etched, as are the auxiliary support structures 117 and stacks 105 and 107 of FIG9 formed between the support structure 119 in the contact region CT, to form a second slit SI2. The second slit SI2 etches the stacks 105 and 107 of FIG9 to expose the sidewalls of the first material layer 105 and the second material layer 107 of FIG9.

[0073] Subsequently, the second material layer 107 of FIG9 is removed, the sidewalls of which are exposed through the second slit SI2, and a gate conductive layer 123 is formed in the space where the second material layer 107 of FIG9 is removed. At least one gate conductive layer 123 disposed at the lowermost end of the gate conductive layer 123 is a lower selection line (source selection line), at least one gate conductive layer 123 disposed at the uppermost end and separated by the first vertical structure VS1 is an upper selection line (drain selection line), and the remaining gate conductive layers 123 are word lines.

[0074] Referring to FIG11, a second vertical structure VS2 is formed by filling the second slit with an insulating layer. The second vertical structure VS2 may be formed of an oxide layer.

[0075] As described above, according to the method of manufacturing a semiconductor device according to an embodiment of the present disclosure, since the support structure 119 is formed of the same material as the first vertical structure VS1, i.e., formed of an oxide layer, the problem of oxidation and expansion of the support structure 119 due to heat generated during subsequent processes can be suppressed. Furthermore, by forming the support structure 119 as a line or a hole, the problem of the support structure 119 tilting in one direction can be suppressed. Additionally, in some embodiments, by forming an auxiliary support structure 117 on the support structure 119, expansion of the upper portion of the support structure 119 can be suppressed.

[0076] Figures 12A and 12B are plan views of a semiconductor device, illustrating a semiconductor device according to another embodiment of the present disclosure.

[0077] Referring to FIG12A, a linear support structure 119D including a protrusion P and a hole-shaped support structure 119C may be provided. In the embodiment, the linear support structure 119D including the protrusion P can suppress the expansion of the insulating layer constituting the support structure 119D in one direction due to heat. In addition, the hole-shaped support structure 119C may be arranged in a row adjacent to the second vertical structure VS2 as shown in the figure, and may also be provided in the space between the contact plugs (i.e., between contact plugs CT1 and CT2).

[0078] In addition, as another embodiment, the hole-shaped support structure 119C can be formed and provided in various shapes other than quadrilateral shapes, such as circular shapes, elliptical shapes and cross shapes (+).

[0079] Referring to FIG12B, linear support structures 119D and 119E, including protrusions P, can be arranged adjacent to each other. In this case, the protrusions P of each of the adjacent linear support structures 119D and 119E can be arranged so that they do not face each other.

[0080] FIG13 is an illustration of a memory block included in a semiconductor device according to an embodiment of the present disclosure.

[0081] The semiconductor device may include a plurality of memory blocks BLK1 to BLKz. The memory blocks BLK1 to BLKz may be arranged to be spaced apart from each other along a direction Y extending from bit lines BLK to BLM. For example, the first memory block BLK1 to the Zth memory block BLKz may be arranged to be spaced apart from each other along a second direction Y, and may include a plurality of memory cells stacked along a third direction Z. In this case, the first memory block BLK1 to the Zth memory block BLKz may be spaced apart from each other using slots.

[0082] Each of the multiple memory blocks BLK1 to BLKz may include multiple channel plugs, contact plugs and support structures, as shown in Figures 3A and 3B or Figures 12A and 12B.

[0083] FIG14 is a block diagram showing the configuration of a memory system according to an embodiment of the present invention.

[0084] Referring to FIG14, a memory system 1000 according to an embodiment of the present disclosure includes a memory device 1200 and a controller 1100.

[0085] The memory device 1200 is used to store data information of various data types, such as text, graphics, and software code. The memory device 1200 may be a semiconductor device described with reference to Figures 1A, 1B, 2, 3A to 3D, 12A, or 12B, and may be manufactured according to the manufacturing methods described with reference to Figures 4 to 11. Since the structure and manufacturing method of the memory device 1200 are the same as described above, a detailed description thereof will be omitted.

[0086] The controller 1100 is connected to the host and the memory device 1200 and is configured to access the memory device 1200 in response to a request from the host. For example, the controller 1100 is configured to control the reading, writing, erasing and background operations of the memory device 1200.

[0087] The controller 1100 includes random access memory (RAM) 1110, central processing unit (CPU) 1120, host interface 1130, error correction code circuit 1140, memory interface 1150, etc.

[0088] Here, RAM 1110 can be used as operating memory of CPU 1120, cache memory between memory device 1200 and host, buffer memory between memory device 1200 and host, etc. For reference, RAM 1110 can be replaced by static random access memory (SRAM), read-only memory (ROM), etc.

[0089] The CPU 1120 is configured to control the overall operation of the controller 1100. For example, the CPU 1120 is configured to operate firmware, such as a flash translation layer (FTL) stored in RAM 1110.

[0090] Host interface 1130 is configured to perform docking with a host. For example, controller 1100 communicates with the host via at least one of various interface protocols, such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and proprietary protocols.

[0091] The ECC circuit 1140 is configured to use error correction code (ECC) to detect and correct errors included in data read from the memory device 1200.

[0092] The memory interface 1150 is configured to perform docking with the memory device 1200. For example, the memory interface 1150 includes an inverse interface or an inverse-OR interface.

[0093] For reference, the controller 1100 may also include a buffer memory (not shown) for temporary data storage. Here, the buffer memory may be used to temporarily store data transferred to the outside via the host interface 1130, or to temporarily store data transferred from the memory device 1200 via the memory interface 1150. In addition, the controller 1100 may also include a ROM that stores code data for interfacing with the host.

[0094] As described above, since the memory system 1000 according to the embodiments of the present disclosure includes a memory device 1200 with improved integration and improved characteristics, the integration and characteristics of the memory system 1000 can also be improved.

[0095] FIG15 is a block diagram showing the configuration of a memory system according to an embodiment of the present disclosure. Hereinafter, descriptions that are repeated above will be omitted.

[0096] Referring to FIG15, the memory system 1000' according to the embodiment of the present disclosure includes a memory device 1200' and a controller 1100. In addition, the controller 1100 includes RAM 1110, CPU 1120, host interface 1130, ECC circuit 1140, memory interface 1150, etc.

[0097] The memory device 1200' may be a non-volatile memory. The memory device 1200' may be a semiconductor device described above with reference to FIG1A, FIG1B, FIG2, FIG3A to FIG3D, FIG12A or FIG12B, and may be manufactured according to the manufacturing method described with reference to FIG4 to FIG11. Since the structure of the memory device 1200' and the method of manufacturing the memory device 1200' are the same as those described above, their detailed description will be omitted.

[0098] Additionally, the memory device 1200' can be a multi-chip package configured with multiple memory chips. The multiple memory chips are divided into multiple groups, and the multiple groups are configured to communicate with the controller 1100 via first to k-th channels CH1 to CHk. Furthermore, memory chips belonging to one group are configured to communicate with the controller 1100 via a common channel. For reference, the memory system 1000' can be modified such that one memory chip is connected to one channel.

[0099] As described above, since the memory system 1000' according to the embodiments of this disclosure includes a memory device 1200' with improved integration and improved characteristics, the integration and characteristics of the memory system 1000' can also be improved. Specifically, by configuring the memory device 1200' in a multi-chip package, the data storage capacity of the memory system 1000' can be increased, and the drive speed can be improved.

[0100] FIG16 is a block diagram showing the configuration of a computing system according to an embodiment of the present disclosure. Hereinafter, descriptions that are repeated above will be omitted.

[0101] Referring to FIG16, the computing system 2000 according to the embodiments of the present disclosure includes a memory device 2100, a CPU 2200, a RAM 2300, a user interface 2400, a power supply 2500, a system bus 2600, etc.

[0102] The memory device 2100 stores data provided by the user interface 2400, data processed by the CPU 2200, etc. Furthermore, the memory device 2100 is electrically connected to the CPU 2200, RAM 2300, user interface 2400, power supply 2500, etc., via the system bus 2600. For example, the memory device 2100 can be connected to the system bus 2600 via a controller (not shown) or can be directly connected to the system bus 2600. When the memory device 2100 is directly connected to the system bus 2600, the functions of the controller can be executed by the CPU 2200, RAM 2300, etc.

[0103] Here, the memory device 2100 may be a non-volatile memory. The memory device 2100 may be a semiconductor device described above with reference to FIG1A, FIG1B, FIG2, FIG3A to FIG3D, FIG12A or FIG12B, and may be manufactured according to the manufacturing method described with reference to FIG4 to FIG11. Since the structure of the memory device 2100 and the method of manufacturing the memory device 2100 are the same as those described above, their detailed description will be omitted.

[0104] In addition, the memory device 2100 may be a multi-chip package including a plurality of memory chips as described with reference to FIG15.

[0105] A computing system with this configuration may be a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a cordless phone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3D television, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a device capable of sending and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, an RFID device, etc.

[0106] As described above, since the computing system 2000 according to the embodiments of the present disclosure includes a memory device 2100 with improved integration and improved characteristics, the characteristics of the computing system 2000 can also be improved.

[0107] Figure 17 is a block diagram illustrating a computing system according to an embodiment of the present disclosure.

[0108] Referring to FIG17, the computing system 3000 according to the embodiments of the present disclosure includes a software layer, which includes an operating system 3200, an application 3100, a file system 3300, a conversion layer 3400, etc. In addition, the computing system 3000 includes a hardware layer such as a memory device 3500.

[0109] The operating system 3200 is used to manage the software and hardware resources of the computing system 3000, and can control the program execution of the central processing unit. The application 3100 can be various application programs that run on the computing system 3000, and can be a utility program executed by the operating system 3200.

[0110] The file system 3300 refers to the logical structure used to manage data, files, etc., existing in the computing system 3000, and to organize the files or data to be stored in the memory device 3500 according to rules. The file system 3300 can be determined based on the operating system 3200 used in the computing system 3000. For example, when the operating system 3200 is a Microsoft Windows system, the file system 3300 can be a File Allocation Table (FAT), an NT File System (NTFS), etc. In addition, when the operating system 3200 is a Unix / Linux system, the file system 3300 can be an Extended File System (EXT), a Unix File System (UFS), a Journal File System (JFS), etc.

[0111] Although the operating system 3200, application 3100 and file system 3300 are shown as separate blocks in this figure, application 3100 and file system 3300 may be included in the operating system 3200.

[0112] In response to a request from the file system 3300, the translation layer 3400 translates the address into a form suitable for the memory device 3500. For example, the translation layer 3400 translates the logical address generated by the file system 3300 into a physical address of the memory device 3500. Here, the mapping information between the logical address and the physical address can be stored in an address translation table. For example, the translation layer 3400 can be a flash translation layer (FTL), a universal flash storage link layer (ULL), etc.

[0113] The memory device 3500 may be a non-volatile memory. The memory device 3500 may be a semiconductor device described above with reference to FIG1A, FIG1B, FIG2, FIG3A to FIG3D, FIG12A or FIG12B, and may be manufactured according to the manufacturing method described with reference to FIG4 to FIG11. Since the structure of the memory device 3500 and the method of manufacturing the memory device 3500 are the same as those described above, their detailed description will be omitted.

[0114] The computing system 3000 with this configuration can be divided into an operating system layer that executes in a higher-level region and a controller layer that executes in a lower-level region. Here, the application 3100, the operating system 3200, and the file system 3300 can be included in the operating system layer and can be driven by the operating memory of the computing system 3000. In addition, the conversion layer 3400 can be included in either the operating system layer or the controller layer.

[0115] As described above, since the computing system 3000 according to the embodiments of the present disclosure includes a memory device 3500 with improved integration and improved characteristics, the characteristics of the computing system 3000 can also be improved. [Simplified Explanation of the Diagram]

[0008] [Figures 1A and 1B] are block diagrams schematically illustrating a semiconductor device according to an embodiment of the present disclosure.

[0009] [Figure 2] is a schematic cross-sectional view showing the surrounding circuit structure.

[0010] [Figures 3A, 3B, 3C and 3D] are plan views and cross-sectional views of a semiconductor device according to embodiments of the present disclosure.

[0011] [Figures 4, 5A, 5B, 6A, 6B, 7, 8A, 8B, 9, 10A, 10B and 11] are cross-sectional and plan views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] [Figures 12A and 12B] are plan views illustrating a semiconductor device according to another embodiment of the present disclosure.

[0013] [Figure 13] is an illustration of a memory block included in a semiconductor device according to an embodiment of the present disclosure.

[0014] [Figure 14] is a block diagram showing the configuration of a memory system according to an embodiment of the present disclosure.

[0015] Figure 15 is a block diagram showing the configuration of a memory system according to an embodiment of the present disclosure.

[0016] [Figure 16] is a block diagram showing the configuration of a computing system according to an embodiment of the present disclosure.

[0017] [Figure 17] is a block diagram illustrating a computing system according to an embodiment of the present disclosure.

Claims

1. A semiconductor device, the semiconductor device comprising: A stacked structure comprising alternating stacked interlayer insulating layers and multiple gate conductive layers; A channel plug, the channel plug at least partially passing through the stacked structure above the unit region; and a plurality of support structures, the plurality of support structures at least partially passing through the stacked structure above the contact region, the plurality of support structures including a linear first support structure and a hole-type second support structure; and an auxiliary support structure formed above the stacked structure, the first support structure and the second support structure above the contact region, wherein the auxiliary support structure includes a plurality of opening regions, wherein the plurality of opening regions are spaced apart from each other in a first direction, and wherein the first support structure overlaps with at least two opening regions spaced apart from each other in the first direction.

2. The semiconductor device according to claim 1, wherein, The multiple opening areas have a baffle structure.

3. The semiconductor device according to claim 2, wherein, The multiple opening regions are arranged in a matrix structure.

4. The semiconductor device according to claim 1, wherein, The auxiliary support structure has a mesh structure.

5. The semiconductor device according to claim 1, further comprising: A linear vertical structure that passes through the upper portion of the stacked structure at the center of the unit region.

6. The semiconductor device according to claim 5, wherein, The auxiliary support structure extends into the unit region and has an opening region that overlaps with the vertical structure to expose a portion of the vertical structure.

7. The semiconductor device according to claim 5, wherein, The vertical structure passes through at least one of the plurality of gate conductive layers, which serves as the drain selection line.

8. A semiconductor device, the semiconductor device comprising: A stacked structure comprising alternating stacked interlayer insulating layers and multiple gate conductive layers; A first channel plug and a second channel plug, the first channel plug and the second channel plug being formed on the cell region by perpendicularly passing through part or all of the stacked structure; a plurality of support structures, the plurality of support structures being formed on the contact region by perpendicularly passing through part or all of the stacked structure; and an auxiliary support structure disposed on the stacked structure and the plurality of support structures, wherein the plurality of support structures includes a linear first support structure, wherein the auxiliary support structure includes a plurality of opening regions spaced apart from each other in a first direction, and wherein the first support structure overlaps with at least two opening regions spaced apart from each other in the first direction.

9. The semiconductor device according to claim 8, wherein, The plurality of support structures also includes a second support structure with a perforated shape.

10. The semiconductor device according to claim 8, wherein, The auxiliary support structure is formed as a mesh structure.

11. The semiconductor device according to claim 10, wherein, Each of the plurality of opening regions has a baffle structure.

12. The semiconductor device according to claim 8, further comprising: A linear vertical structure that passes through the upper portion of the stacked structure at the center of the unit region.

13. The semiconductor device according to claim 12, wherein, The opening region exposes the vertical structure.

14. A method of manufacturing a semiconductor device, the method comprising the steps of: forming a stacked structure in which a plurality of interlayer insulating layers and a plurality of sacrificial layers are alternately stacked on a substrate including a cell region and a contact region; etching the stacked structure over the contact region to together form a first hole for forming a contact plug through a portion or all of the stacked structure, a trench for forming a first support structure, and a second hole for forming a second support structure; A contact plug is formed by filling the first hole with a barrier layer and a conductive layer; the trench and the second hole are filled with the barrier layer and the conductive layer; an auxiliary support structure is formed on the stacked structure, the auxiliary support structure including a plurality of opening regions overlapping a portion of the trench and a portion of the second hole; Remove the barrier layer and the conductive layer remaining in the trenches and the second holes exposed through the plurality of opening areas of the auxiliary support structure; and form the first support structure and the second support structure by filling the trenches and the second holes with an insulating layer.

15. The method according to claim 14, wherein, The step of forming the auxiliary support structure includes forming the auxiliary support structure such that each of the plurality of opening regions has a baffle structure.

16. The method according to claim 14, wherein, The step of forming the auxiliary support structure includes forming the auxiliary support structure such that the auxiliary support structure extends above the stacked structure above the unit region to expose a portion of the unit region.

17. The method according to claim 16, the method further comprising, before removing the barrier layer and the conductive layer retained in the trench and the second hole: forming a slit by partially etching the upper end of the stacked structure above the cell region exposed by the auxiliary support structure.

18. The method according to claim 17, wherein, When forming the first support structure and the second support structure, the insulating layer is filled into the slit to form a vertical structure.

19. The method according to claim 14, wherein, The first support structure is formed in a linear shape, and the width of each of the first support structures is different from that of the others.

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